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Linux/arch/mips/include/asm/cacheops.h

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  1 /*
  2  * Cache operations for the cache instruction.
  3  *
  4  * This file is subject to the terms and conditions of the GNU General Public
  5  * License.  See the file "COPYING" in the main directory of this archive
  6  * for more details.
  7  *
  8  * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
  9  * (C) Copyright 1999 Silicon Graphics, Inc.
 10  */
 11 #ifndef __ASM_CACHEOPS_H
 12 #define __ASM_CACHEOPS_H
 13 
 14 /*
 15  * Most cache ops are split into a 2 bit field identifying the cache, and a 3
 16  * bit field identifying the cache operation.
 17  */
 18 #define CacheOp_Cache                   0x03
 19 #define CacheOp_Op                      0x1c
 20 
 21 #define Cache_I                         0x00
 22 #define Cache_D                         0x01
 23 #define Cache_T                         0x02
 24 #define Cache_V                         0x02 /* Loongson-3 */
 25 #define Cache_S                         0x03
 26 
 27 #define Index_Writeback_Inv             0x00
 28 #define Index_Load_Tag                  0x04
 29 #define Index_Store_Tag                 0x08
 30 #define Hit_Invalidate                  0x10
 31 #define Hit_Writeback_Inv               0x14    /* not with Cache_I though */
 32 #define Hit_Writeback                   0x18
 33 
 34 /*
 35  * Cache Operations available on all MIPS processors with R4000-style caches
 36  */
 37 #define Index_Invalidate_I              (Cache_I | Index_Writeback_Inv)
 38 #define Index_Writeback_Inv_D           (Cache_D | Index_Writeback_Inv)
 39 #define Index_Load_Tag_I                (Cache_I | Index_Load_Tag)
 40 #define Index_Load_Tag_D                (Cache_D | Index_Load_Tag)
 41 #define Index_Store_Tag_I               (Cache_I | Index_Store_Tag)
 42 #define Index_Store_Tag_D               (Cache_D | Index_Store_Tag)
 43 #define Hit_Invalidate_I                (Cache_I | Hit_Invalidate)
 44 #define Hit_Invalidate_D                (Cache_D | Hit_Invalidate)
 45 #define Hit_Writeback_Inv_D             (Cache_D | Hit_Writeback_Inv)
 46 
 47 /*
 48  * R4000-specific cacheops
 49  */
 50 #define Create_Dirty_Excl_D             (Cache_D | 0x0c)
 51 #define Fill_I                          (Cache_I | 0x14)
 52 #define Hit_Writeback_I                 (Cache_I | Hit_Writeback)
 53 #define Hit_Writeback_D                 (Cache_D | Hit_Writeback)
 54 
 55 /*
 56  * R4000SC and R4400SC-specific cacheops
 57  */
 58 #define Cache_SI                        0x02
 59 #define Cache_SD                        0x03
 60 
 61 #define Index_Invalidate_SI             (Cache_SI | Index_Writeback_Inv)
 62 #define Index_Writeback_Inv_SD          (Cache_SD | Index_Writeback_Inv)
 63 #define Index_Load_Tag_SI               (Cache_SI | Index_Load_Tag)
 64 #define Index_Load_Tag_SD               (Cache_SD | Index_Load_Tag)
 65 #define Index_Store_Tag_SI              (Cache_SI | Index_Store_Tag)
 66 #define Index_Store_Tag_SD              (Cache_SD | Index_Store_Tag)
 67 #define Create_Dirty_Excl_SD            (Cache_SD | 0x0c)
 68 #define Hit_Invalidate_SI               (Cache_SI | Hit_Invalidate)
 69 #define Hit_Invalidate_SD               (Cache_SD | Hit_Invalidate)
 70 #define Hit_Writeback_Inv_SD            (Cache_SD | Hit_Writeback_Inv)
 71 #define Hit_Writeback_SD                (Cache_SD | Hit_Writeback)
 72 #define Hit_Set_Virtual_SI              (Cache_SI | 0x1c)
 73 #define Hit_Set_Virtual_SD              (Cache_SD | 0x1c)
 74 
 75 /*
 76  * R5000-specific cacheops
 77  */
 78 #define R5K_Page_Invalidate_S           (Cache_S | 0x14)
 79 
 80 /*
 81  * RM7000-specific cacheops
 82  */
 83 #define Page_Invalidate_T               (Cache_T | 0x14)
 84 #define Index_Store_Tag_T               (Cache_T | Index_Store_Tag)
 85 #define Index_Load_Tag_T                (Cache_T | Index_Load_Tag)
 86 
 87 /*
 88  * R10000-specific cacheops
 89  *
 90  * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
 91  * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
 92  */
 93 #define Index_Writeback_Inv_S           (Cache_S | Index_Writeback_Inv)
 94 #define Index_Load_Tag_S                (Cache_S | Index_Load_Tag)
 95 #define Index_Store_Tag_S               (Cache_S | Index_Store_Tag)
 96 #define Hit_Invalidate_S                (Cache_S | Hit_Invalidate)
 97 #define Cache_Barrier                   0x14
 98 #define Hit_Writeback_Inv_S             (Cache_S | Hit_Writeback_Inv)
 99 #define Index_Load_Data_I               (Cache_I | 0x18)
100 #define Index_Load_Data_D               (Cache_D | 0x18)
101 #define Index_Load_Data_S               (Cache_S | 0x18)
102 #define Index_Store_Data_I              (Cache_I | 0x1c)
103 #define Index_Store_Data_D              (Cache_D | 0x1c)
104 #define Index_Store_Data_S              (Cache_S | 0x1c)
105 
106 /*
107  * Loongson2-specific cacheops
108  */
109 #define Hit_Invalidate_I_Loongson2      (Cache_I | 0x00)
110 
111 /*
112  * Loongson3-specific cacheops
113  */
114 #define Index_Writeback_Inv_V           (Cache_V | Index_Writeback_Inv)
115 
116 #endif  /* __ASM_CACHEOPS_H */
117 

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