1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
5 *
6 * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30 /*
31 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
32 */
33
34 #ifndef _AU1000_H_
35 #define _AU1000_H_
36
37 /* SOC Interrupt numbers */
38 /* Au1000-style (IC0/1): 2 controllers with 32 sources each */
39 #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
40 #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
41 #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
42 #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
43 #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
44
45 /* Au1300-style (GPIC): 1 controller with up to 128 sources */
46 #define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
47 #define ALCHEMY_GPIC_INT_NUM 128
48 #define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
49
50 /* common clock names, shared among all variants. AUXPLL2 is Au1300 */
51 #define ALCHEMY_ROOT_CLK "root_clk"
52 #define ALCHEMY_CPU_CLK "cpu_clk"
53 #define ALCHEMY_AUXPLL_CLK "auxpll_clk"
54 #define ALCHEMY_AUXPLL2_CLK "auxpll2_clk"
55 #define ALCHEMY_SYSBUS_CLK "sysbus_clk"
56 #define ALCHEMY_PERIPH_CLK "periph_clk"
57 #define ALCHEMY_MEM_CLK "mem_clk"
58 #define ALCHEMY_LR_CLK "lr_clk"
59 #define ALCHEMY_FG0_CLK "fg0_clk"
60 #define ALCHEMY_FG1_CLK "fg1_clk"
61 #define ALCHEMY_FG2_CLK "fg2_clk"
62 #define ALCHEMY_FG3_CLK "fg3_clk"
63 #define ALCHEMY_FG4_CLK "fg4_clk"
64 #define ALCHEMY_FG5_CLK "fg5_clk"
65
66 /* Au1300 peripheral interrupt numbers */
67 #define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE)
68 #define AU1300_UART1_INT (AU1300_FIRST_INT + 17)
69 #define AU1300_UART2_INT (AU1300_FIRST_INT + 25)
70 #define AU1300_UART3_INT (AU1300_FIRST_INT + 27)
71 #define AU1300_SD1_INT (AU1300_FIRST_INT + 32)
72 #define AU1300_SD2_INT (AU1300_FIRST_INT + 38)
73 #define AU1300_PSC0_INT (AU1300_FIRST_INT + 48)
74 #define AU1300_PSC1_INT (AU1300_FIRST_INT + 52)
75 #define AU1300_PSC2_INT (AU1300_FIRST_INT + 56)
76 #define AU1300_PSC3_INT (AU1300_FIRST_INT + 60)
77 #define AU1300_NAND_INT (AU1300_FIRST_INT + 62)
78 #define AU1300_DDMA_INT (AU1300_FIRST_INT + 75)
79 #define AU1300_MMU_INT (AU1300_FIRST_INT + 76)
80 #define AU1300_MPU_INT (AU1300_FIRST_INT + 77)
81 #define AU1300_GPU_INT (AU1300_FIRST_INT + 78)
82 #define AU1300_UDMA_INT (AU1300_FIRST_INT + 79)
83 #define AU1300_TOY_INT (AU1300_FIRST_INT + 80)
84 #define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81)
85 #define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82)
86 #define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83)
87 #define AU1300_RTC_INT (AU1300_FIRST_INT + 84)
88 #define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85)
89 #define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86)
90 #define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87)
91 #define AU1300_UART0_INT (AU1300_FIRST_INT + 88)
92 #define AU1300_SD0_INT (AU1300_FIRST_INT + 89)
93 #define AU1300_USB_INT (AU1300_FIRST_INT + 90)
94 #define AU1300_LCD_INT (AU1300_FIRST_INT + 91)
95 #define AU1300_BSA_INT (AU1300_FIRST_INT + 92)
96 #define AU1300_MPE_INT (AU1300_FIRST_INT + 93)
97 #define AU1300_ITE_INT (AU1300_FIRST_INT + 94)
98 #define AU1300_AES_INT (AU1300_FIRST_INT + 95)
99 #define AU1300_CIM_INT (AU1300_FIRST_INT + 96)
100
101 /**********************************************************************/
102
103 /*
104 * Physical base addresses for integrated peripherals
105 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
106 */
107
108 #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
109 #define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */
110 #define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */
111 #define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */
112 #define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */
113 #define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */
114 #define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */
115 #define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */
116 #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
117 #define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */
118 #define AU1300_GPIC_PHYS_ADDR 0x10200000 /* 5 */
119 #define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */
120 #define AU1200_AES_PHYS_ADDR 0x10300000 /* 45 */
121 #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
122 #define AU1300_GPU_PHYS_ADDR 0x10500000 /* 5 */
123 #define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
124 #define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
125 #define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */
126 #define AU1100_SD0_PHYS_ADDR 0x10600000 /* 245 */
127 #define AU1300_SD1_PHYS_ADDR 0x10601000 /* 5 */
128 #define AU1300_SD2_PHYS_ADDR 0x10602000 /* 5 */
129 #define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */
130 #define AU1300_SYS_PHYS_ADDR 0x10900000 /* 5 */
131 #define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */
132 #define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */
133 #define AU1300_PSC0_PHYS_ADDR 0x10A00000 /* 5 */
134 #define AU1300_PSC1_PHYS_ADDR 0x10A01000 /* 5 */
135 #define AU1300_PSC2_PHYS_ADDR 0x10A02000 /* 5 */
136 #define AU1300_PSC3_PHYS_ADDR 0x10A03000 /* 5 */
137 #define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */
138 #define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */
139 #define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */
140 #define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */
141 #define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */
142 #define AU1200_SWCNT_PHYS_ADDR 0x1110010C /* 4 */
143 #define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */
144 #define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */
145 #define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */
146 #define AU1000_SSI0_PHYS_ADDR 0x11600000 /* 02 */
147 #define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */
148 #define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */
149 #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
150 #define AU1000_SYS_PHYS_ADDR 0x11900000 /* 012345 */
151 #define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */
152 #define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */
153 #define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */
154 #define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */
155 #define AU1300_UDMA_PHYS_ADDR 0x14001800 /* 5 */
156 #define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */
157 #define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 345 */
158 #define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 345 */
159 #define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
160 #define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
161 #define AU1200_CIM_PHYS_ADDR 0x14004000 /* 45 */
162 #define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */
163 #define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */
164 #define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */
165 #define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */
166 #define AU1300_MAEITE_PHYS_ADDR 0x14010000 /* 5 */
167 #define AU1300_MAEMPE_PHYS_ADDR 0x14014000 /* 5 */
168 #define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */
169 #define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */
170 #define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */
171 #define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */
172 #define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */
173 #define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */
174 #define AU1300_USB_EHCI_PHYS_ADDR 0x14020000 /* 5 */
175 #define AU1300_USB_OHCI0_PHYS_ADDR 0x14020400 /* 5 */
176 #define AU1300_USB_OHCI1_PHYS_ADDR 0x14020800 /* 5 */
177 #define AU1300_USB_CTL_PHYS_ADDR 0x14021000 /* 5 */
178 #define AU1300_USB_OTG_PHYS_ADDR 0x14022000 /* 5 */
179 #define AU1300_MAEBSA_PHYS_ADDR 0x14030000 /* 5 */
180 #define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */
181 #define AU1200_LCD_PHYS_ADDR 0x15000000 /* 45 */
182 #define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */
183 #define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */
184 #define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */
185 #define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */
186 #define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 012345 */
187 #define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 012345 */
188 #define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 012345 */
189
190 /**********************************************************************/
191
192
193 /*
194 * Au1300 GPIO+INT controller (GPIC) register offsets and bits
195 * Registers are 128bits (0x10 bytes), divided into 4 "banks".
196 */
197 #define AU1300_GPIC_PINVAL 0x0000
198 #define AU1300_GPIC_PINVALCLR 0x0010
199 #define AU1300_GPIC_IPEND 0x0020
200 #define AU1300_GPIC_PRIENC 0x0030
201 #define AU1300_GPIC_IEN 0x0040 /* int_mask in manual */
202 #define AU1300_GPIC_IDIS 0x0050 /* int_maskclr in manual */
203 #define AU1300_GPIC_DMASEL 0x0060
204 #define AU1300_GPIC_DEVSEL 0x0080
205 #define AU1300_GPIC_DEVCLR 0x0090
206 #define AU1300_GPIC_RSTVAL 0x00a0
207 /* pin configuration space. one 32bit register for up to 128 IRQs */
208 #define AU1300_GPIC_PINCFG 0x1000
209
210 #define GPIC_GPIO_TO_BIT(gpio) \
211 (1 << ((gpio) & 0x1f))
212
213 #define GPIC_GPIO_BANKOFF(gpio) \
214 (((gpio) >> 5) * 4)
215
216 /* Pin Control bits: who owns the pin, what does it do */
217 #define GPIC_CFG_PC_GPIN 0
218 #define GPIC_CFG_PC_DEV 1
219 #define GPIC_CFG_PC_GPOLOW 2
220 #define GPIC_CFG_PC_GPOHIGH 3
221 #define GPIC_CFG_PC_MASK 3
222
223 /* assign pin to MIPS IRQ line */
224 #define GPIC_CFG_IL_SET(x) (((x) & 3) << 2)
225 #define GPIC_CFG_IL_MASK (3 << 2)
226
227 /* pin interrupt type setup */
228 #define GPIC_CFG_IC_OFF (0 << 4)
229 #define GPIC_CFG_IC_LEVEL_LOW (1 << 4)
230 #define GPIC_CFG_IC_LEVEL_HIGH (2 << 4)
231 #define GPIC_CFG_IC_EDGE_FALL (5 << 4)
232 #define GPIC_CFG_IC_EDGE_RISE (6 << 4)
233 #define GPIC_CFG_IC_EDGE_BOTH (7 << 4)
234 #define GPIC_CFG_IC_MASK (7 << 4)
235
236 /* allow interrupt to wake cpu from 'wait' */
237 #define GPIC_CFG_IDLEWAKE (1 << 7)
238
239 /***********************************************************************/
240
241 /* Au1000 SDRAM memory controller register offsets */
242 #define AU1000_MEM_SDMODE0 0x0000
243 #define AU1000_MEM_SDMODE1 0x0004
244 #define AU1000_MEM_SDMODE2 0x0008
245 #define AU1000_MEM_SDADDR0 0x000C
246 #define AU1000_MEM_SDADDR1 0x0010
247 #define AU1000_MEM_SDADDR2 0x0014
248 #define AU1000_MEM_SDREFCFG 0x0018
249 #define AU1000_MEM_SDPRECMD 0x001C
250 #define AU1000_MEM_SDAUTOREF 0x0020
251 #define AU1000_MEM_SDWRMD0 0x0024
252 #define AU1000_MEM_SDWRMD1 0x0028
253 #define AU1000_MEM_SDWRMD2 0x002C
254 #define AU1000_MEM_SDSLEEP 0x0030
255 #define AU1000_MEM_SDSMCKE 0x0034
256
257 /* MEM_SDMODE register content definitions */
258 #define MEM_SDMODE_F (1 << 22)
259 #define MEM_SDMODE_SR (1 << 21)
260 #define MEM_SDMODE_BS (1 << 20)
261 #define MEM_SDMODE_RS (3 << 18)
262 #define MEM_SDMODE_CS (7 << 15)
263 #define MEM_SDMODE_TRAS (15 << 11)
264 #define MEM_SDMODE_TMRD (3 << 9)
265 #define MEM_SDMODE_TWR (3 << 7)
266 #define MEM_SDMODE_TRP (3 << 5)
267 #define MEM_SDMODE_TRCD (3 << 3)
268 #define MEM_SDMODE_TCL (7 << 0)
269
270 #define MEM_SDMODE_BS_2Bank (0 << 20)
271 #define MEM_SDMODE_BS_4Bank (1 << 20)
272 #define MEM_SDMODE_RS_11Row (0 << 18)
273 #define MEM_SDMODE_RS_12Row (1 << 18)
274 #define MEM_SDMODE_RS_13Row (2 << 18)
275 #define MEM_SDMODE_RS_N(N) ((N) << 18)
276 #define MEM_SDMODE_CS_7Col (0 << 15)
277 #define MEM_SDMODE_CS_8Col (1 << 15)
278 #define MEM_SDMODE_CS_9Col (2 << 15)
279 #define MEM_SDMODE_CS_10Col (3 << 15)
280 #define MEM_SDMODE_CS_11Col (4 << 15)
281 #define MEM_SDMODE_CS_N(N) ((N) << 15)
282 #define MEM_SDMODE_TRAS_N(N) ((N) << 11)
283 #define MEM_SDMODE_TMRD_N(N) ((N) << 9)
284 #define MEM_SDMODE_TWR_N(N) ((N) << 7)
285 #define MEM_SDMODE_TRP_N(N) ((N) << 5)
286 #define MEM_SDMODE_TRCD_N(N) ((N) << 3)
287 #define MEM_SDMODE_TCL_N(N) ((N) << 0)
288
289 /* MEM_SDADDR register contents definitions */
290 #define MEM_SDADDR_E (1 << 20)
291 #define MEM_SDADDR_CSBA (0x03FF << 10)
292 #define MEM_SDADDR_CSMASK (0x03FF << 0)
293 #define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
294 #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
295
296 /* MEM_SDREFCFG register content definitions */
297 #define MEM_SDREFCFG_TRC (15 << 28)
298 #define MEM_SDREFCFG_TRPM (3 << 26)
299 #define MEM_SDREFCFG_E (1 << 25)
300 #define MEM_SDREFCFG_RE (0x1ffffff << 0)
301 #define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
302 #define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
303 #define MEM_SDREFCFG_REF_N(N) (N)
304
305 /* Au1550 SDRAM Register Offsets */
306 #define AU1550_MEM_SDMODE0 0x0800
307 #define AU1550_MEM_SDMODE1 0x0808
308 #define AU1550_MEM_SDMODE2 0x0810
309 #define AU1550_MEM_SDADDR0 0x0820
310 #define AU1550_MEM_SDADDR1 0x0828
311 #define AU1550_MEM_SDADDR2 0x0830
312 #define AU1550_MEM_SDCONFIGA 0x0840
313 #define AU1550_MEM_SDCONFIGB 0x0848
314 #define AU1550_MEM_SDSTAT 0x0850
315 #define AU1550_MEM_SDERRADDR 0x0858
316 #define AU1550_MEM_SDSTRIDE0 0x0860
317 #define AU1550_MEM_SDSTRIDE1 0x0868
318 #define AU1550_MEM_SDSTRIDE2 0x0870
319 #define AU1550_MEM_SDWRMD0 0x0880
320 #define AU1550_MEM_SDWRMD1 0x0888
321 #define AU1550_MEM_SDWRMD2 0x0890
322 #define AU1550_MEM_SDPRECMD 0x08C0
323 #define AU1550_MEM_SDAUTOREF 0x08C8
324 #define AU1550_MEM_SDSREF 0x08D0
325 #define AU1550_MEM_SDSLEEP MEM_SDSREF
326
327 /* Static Bus Controller register offsets */
328 #define AU1000_MEM_STCFG0 0x000
329 #define AU1000_MEM_STTIME0 0x004
330 #define AU1000_MEM_STADDR0 0x008
331 #define AU1000_MEM_STCFG1 0x010
332 #define AU1000_MEM_STTIME1 0x014
333 #define AU1000_MEM_STADDR1 0x018
334 #define AU1000_MEM_STCFG2 0x020
335 #define AU1000_MEM_STTIME2 0x024
336 #define AU1000_MEM_STADDR2 0x028
337 #define AU1000_MEM_STCFG3 0x030
338 #define AU1000_MEM_STTIME3 0x034
339 #define AU1000_MEM_STADDR3 0x038
340 #define AU1000_MEM_STNDCTL 0x100
341 #define AU1000_MEM_STSTAT 0x104
342
343 #define MEM_STNAND_CMD 0x0
344 #define MEM_STNAND_ADDR 0x4
345 #define MEM_STNAND_DATA 0x20
346
347
348 /* Programmable Counters 0 and 1 */
349 #define AU1000_SYS_CNTRCTRL 0x14
350 # define SYS_CNTRL_E1S (1 << 23)
351 # define SYS_CNTRL_T1S (1 << 20)
352 # define SYS_CNTRL_M21 (1 << 19)
353 # define SYS_CNTRL_M11 (1 << 18)
354 # define SYS_CNTRL_M01 (1 << 17)
355 # define SYS_CNTRL_C1S (1 << 16)
356 # define SYS_CNTRL_BP (1 << 14)
357 # define SYS_CNTRL_EN1 (1 << 13)
358 # define SYS_CNTRL_BT1 (1 << 12)
359 # define SYS_CNTRL_EN0 (1 << 11)
360 # define SYS_CNTRL_BT0 (1 << 10)
361 # define SYS_CNTRL_E0 (1 << 8)
362 # define SYS_CNTRL_E0S (1 << 7)
363 # define SYS_CNTRL_32S (1 << 5)
364 # define SYS_CNTRL_T0S (1 << 4)
365 # define SYS_CNTRL_M20 (1 << 3)
366 # define SYS_CNTRL_M10 (1 << 2)
367 # define SYS_CNTRL_M00 (1 << 1)
368 # define SYS_CNTRL_C0S (1 << 0)
369
370 /* Programmable Counter 0 Registers */
371 #define AU1000_SYS_TOYTRIM 0x00
372 #define AU1000_SYS_TOYWRITE 0x04
373 #define AU1000_SYS_TOYMATCH0 0x08
374 #define AU1000_SYS_TOYMATCH1 0x0c
375 #define AU1000_SYS_TOYMATCH2 0x10
376 #define AU1000_SYS_TOYREAD 0x40
377
378 /* Programmable Counter 1 Registers */
379 #define AU1000_SYS_RTCTRIM 0x44
380 #define AU1000_SYS_RTCWRITE 0x48
381 #define AU1000_SYS_RTCMATCH0 0x4c
382 #define AU1000_SYS_RTCMATCH1 0x50
383 #define AU1000_SYS_RTCMATCH2 0x54
384 #define AU1000_SYS_RTCREAD 0x58
385
386
387 /* GPIO */
388 #define AU1000_SYS_PINFUNC 0x2C
389 # define SYS_PF_USB (1 << 15) /* 2nd USB device/host */
390 # define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */
391 # define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */
392 # define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */
393 # define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */
394 # define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */
395 # define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */
396 # define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */
397 # define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */
398 # define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */
399 # define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */
400 # define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */
401 # define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */
402 # define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */
403 # define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */
404 # define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */
405
406 /* Au1100 only */
407 # define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */
408 # define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */
409 # define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */
410 # define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */
411
412 /* Au1550 only. Redefines lots of pins */
413 # define SYS_PF_PSC2_MASK (7 << 17)
414 # define SYS_PF_PSC2_AC97 0
415 # define SYS_PF_PSC2_SPI 0
416 # define SYS_PF_PSC2_I2S (1 << 17)
417 # define SYS_PF_PSC2_SMBUS (3 << 17)
418 # define SYS_PF_PSC2_GPIO (7 << 17)
419 # define SYS_PF_PSC3_MASK (7 << 20)
420 # define SYS_PF_PSC3_AC97 0
421 # define SYS_PF_PSC3_SPI 0
422 # define SYS_PF_PSC3_I2S (1 << 20)
423 # define SYS_PF_PSC3_SMBUS (3 << 20)
424 # define SYS_PF_PSC3_GPIO (7 << 20)
425 # define SYS_PF_PSC1_S1 (1 << 1)
426 # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
427
428 /* Au1200 only */
429 #define SYS_PINFUNC_DMA (1 << 31)
430 #define SYS_PINFUNC_S0A (1 << 30)
431 #define SYS_PINFUNC_S1A (1 << 29)
432 #define SYS_PINFUNC_LP0 (1 << 28)
433 #define SYS_PINFUNC_LP1 (1 << 27)
434 #define SYS_PINFUNC_LD16 (1 << 26)
435 #define SYS_PINFUNC_LD8 (1 << 25)
436 #define SYS_PINFUNC_LD1 (1 << 24)
437 #define SYS_PINFUNC_LD0 (1 << 23)
438 #define SYS_PINFUNC_P1A (3 << 21)
439 #define SYS_PINFUNC_P1B (1 << 20)
440 #define SYS_PINFUNC_FS3 (1 << 19)
441 #define SYS_PINFUNC_P0A (3 << 17)
442 #define SYS_PINFUNC_CS (1 << 16)
443 #define SYS_PINFUNC_CIM (1 << 15)
444 #define SYS_PINFUNC_P1C (1 << 14)
445 #define SYS_PINFUNC_U1T (1 << 12)
446 #define SYS_PINFUNC_U1R (1 << 11)
447 #define SYS_PINFUNC_EX1 (1 << 10)
448 #define SYS_PINFUNC_EX0 (1 << 9)
449 #define SYS_PINFUNC_U0R (1 << 8)
450 #define SYS_PINFUNC_MC (1 << 7)
451 #define SYS_PINFUNC_S0B (1 << 6)
452 #define SYS_PINFUNC_S0C (1 << 5)
453 #define SYS_PINFUNC_P0B (1 << 4)
454 #define SYS_PINFUNC_U0T (1 << 3)
455 #define SYS_PINFUNC_S1B (1 << 2)
456
457 /* Power Management */
458 #define AU1000_SYS_SCRATCH0 0x18
459 #define AU1000_SYS_SCRATCH1 0x1c
460 #define AU1000_SYS_WAKEMSK 0x34
461 #define AU1000_SYS_ENDIAN 0x38
462 #define AU1000_SYS_POWERCTRL 0x3c
463 #define AU1000_SYS_WAKESRC 0x5c
464 #define AU1000_SYS_SLPPWR 0x78
465 #define AU1000_SYS_SLEEP 0x7c
466
467 #define SYS_WAKEMSK_D2 (1 << 9)
468 #define SYS_WAKEMSK_M2 (1 << 8)
469 #define SYS_WAKEMSK_GPIO(x) (1 << (x))
470
471 /* Clock Controller */
472 #define AU1000_SYS_FREQCTRL0 0x20
473 #define AU1000_SYS_FREQCTRL1 0x24
474 #define AU1000_SYS_CLKSRC 0x28
475 #define AU1000_SYS_CPUPLL 0x60
476 #define AU1000_SYS_AUXPLL 0x64
477 #define AU1300_SYS_AUXPLL2 0x68
478
479
480 /**********************************************************************/
481
482
483 /* The PCI chip selects are outside the 32bit space, and since we can't
484 * just program the 36bit addresses into BARs, we have to take a chunk
485 * out of the 32bit space and reserve it for PCI. When these addresses
486 * are ioremap()ed, they'll be fixed up to the real 36bit address before
487 * being passed to the real ioremap function.
488 */
489 #define ALCHEMY_PCI_MEMWIN_START (AU1500_PCI_MEM_PHYS_ADDR >> 4)
490 #define ALCHEMY_PCI_MEMWIN_END (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF)
491
492 /* for PCI IO it's simpler because we get to do the ioremap ourselves and then
493 * adjust the device's resources.
494 */
495 #define ALCHEMY_PCI_IOWIN_START 0x00001000
496 #define ALCHEMY_PCI_IOWIN_END 0x0000FFFF
497
498 #ifdef CONFIG_PCI
499
500 #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
501 #define IOPORT_RESOURCE_END 0xffffffff
502 #define IOMEM_RESOURCE_START 0x10000000
503 #define IOMEM_RESOURCE_END 0xfffffffffULL
504
505 #else
506
507 /* Don't allow any legacy ports probing */
508 #define IOPORT_RESOURCE_START 0x10000000
509 #define IOPORT_RESOURCE_END 0xffffffff
510 #define IOMEM_RESOURCE_START 0x10000000
511 #define IOMEM_RESOURCE_END 0xfffffffffULL
512
513 #endif
514
515 /* PCI controller block register offsets */
516 #define PCI_REG_CMEM 0x0000
517 #define PCI_REG_CONFIG 0x0004
518 #define PCI_REG_B2BMASK_CCH 0x0008
519 #define PCI_REG_B2BBASE0_VID 0x000C
520 #define PCI_REG_B2BBASE1_SID 0x0010
521 #define PCI_REG_MWMASK_DEV 0x0014
522 #define PCI_REG_MWBASE_REV_CCL 0x0018
523 #define PCI_REG_ERR_ADDR 0x001C
524 #define PCI_REG_SPEC_INTACK 0x0020
525 #define PCI_REG_ID 0x0100
526 #define PCI_REG_STATCMD 0x0104
527 #define PCI_REG_CLASSREV 0x0108
528 #define PCI_REG_PARAM 0x010C
529 #define PCI_REG_MBAR 0x0110
530 #define PCI_REG_TIMEOUT 0x0140
531
532 /* PCI controller block register bits */
533 #define PCI_CMEM_E (1 << 28) /* enable cacheable memory */
534 #define PCI_CMEM_CMBASE(x) (((x) & 0x3fff) << 14)
535 #define PCI_CMEM_CMMASK(x) ((x) & 0x3fff)
536 #define PCI_CONFIG_ERD (1 << 27) /* pci error during R/W */
537 #define PCI_CONFIG_ET (1 << 26) /* error in target mode */
538 #define PCI_CONFIG_EF (1 << 25) /* fatal error */
539 #define PCI_CONFIG_EP (1 << 24) /* parity error */
540 #define PCI_CONFIG_EM (1 << 23) /* multiple errors */
541 #define PCI_CONFIG_BM (1 << 22) /* bad master error */
542 #define PCI_CONFIG_PD (1 << 20) /* PCI Disable */
543 #define PCI_CONFIG_BME (1 << 19) /* Byte Mask Enable for reads */
544 #define PCI_CONFIG_NC (1 << 16) /* mark mem access non-coherent */
545 #define PCI_CONFIG_IA (1 << 15) /* INTA# enabled (target mode) */
546 #define PCI_CONFIG_IP (1 << 13) /* int on PCI_PERR# */
547 #define PCI_CONFIG_IS (1 << 12) /* int on PCI_SERR# */
548 #define PCI_CONFIG_IMM (1 << 11) /* int on master abort */
549 #define PCI_CONFIG_ITM (1 << 10) /* int on target abort (as master) */
550 #define PCI_CONFIG_ITT (1 << 9) /* int on target abort (as target) */
551 #define PCI_CONFIG_IPB (1 << 8) /* int on PERR# in bus master acc */
552 #define PCI_CONFIG_SIC_NO (0 << 6) /* no byte mask changes */
553 #define PCI_CONFIG_SIC_BA_ADR (1 << 6) /* on byte/hw acc, invert adr bits */
554 #define PCI_CONFIG_SIC_HWA_DAT (2 << 6) /* on halfword acc, swap data */
555 #define PCI_CONFIG_SIC_ALL (3 << 6) /* swap data bytes on all accesses */
556 #define PCI_CONFIG_ST (1 << 5) /* swap data by target transactions */
557 #define PCI_CONFIG_SM (1 << 4) /* swap data from PCI ctl */
558 #define PCI_CONFIG_AEN (1 << 3) /* enable internal arbiter */
559 #define PCI_CONFIG_R2H (1 << 2) /* REQ2# to hi-prio arbiter */
560 #define PCI_CONFIG_R1H (1 << 1) /* REQ1# to hi-prio arbiter */
561 #define PCI_CONFIG_CH (1 << 0) /* PCI ctl to hi-prio arbiter */
562 #define PCI_B2BMASK_B2BMASK(x) (((x) & 0xffff) << 16)
563 #define PCI_B2BMASK_CCH(x) ((x) & 0xffff) /* 16 upper bits of class code */
564 #define PCI_B2BBASE0_VID_B0(x) (((x) & 0xffff) << 16)
565 #define PCI_B2BBASE0_VID_SV(x) ((x) & 0xffff)
566 #define PCI_B2BBASE1_SID_B1(x) (((x) & 0xffff) << 16)
567 #define PCI_B2BBASE1_SID_SI(x) ((x) & 0xffff)
568 #define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16)
569 #define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff)
570 #define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16)
571 #define PCI_MWBASEREVCCL_REV(x) (((x) & 0xff) << 8)
572 #define PCI_MWBASEREVCCL_CCL(x) ((x) & 0xff)
573 #define PCI_ID_DID(x) (((x) & 0xffff) << 16)
574 #define PCI_ID_VID(x) ((x) & 0xffff)
575 #define PCI_STATCMD_STATUS(x) (((x) & 0xffff) << 16)
576 #define PCI_STATCMD_CMD(x) ((x) & 0xffff)
577 #define PCI_CLASSREV_CLASS(x) (((x) & 0x00ffffff) << 8)
578 #define PCI_CLASSREV_REV(x) ((x) & 0xff)
579 #define PCI_PARAM_BIST(x) (((x) & 0xff) << 24)
580 #define PCI_PARAM_HT(x) (((x) & 0xff) << 16)
581 #define PCI_PARAM_LT(x) (((x) & 0xff) << 8)
582 #define PCI_PARAM_CLS(x) ((x) & 0xff)
583 #define PCI_TIMEOUT_RETRIES(x) (((x) & 0xff) << 8) /* max retries */
584 #define PCI_TIMEOUT_TO(x) ((x) & 0xff) /* target ready timeout */
585
586
587 /**********************************************************************/
588
589
590 #ifndef _LANGUAGE_ASSEMBLY
591
592 #include <linux/delay.h>
593 #include <linux/types.h>
594
595 #include <linux/io.h>
596 #include <linux/irq.h>
597
598 #include <asm/cpu.h>
599
600 void alchemy_set_lpj(void);
601 void board_setup(void);
602
603 /* helpers to access the SYS_* registers */
604 static inline unsigned long alchemy_rdsys(int regofs)
605 {
606 void __iomem *b = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
607
608 return __raw_readl(b + regofs);
609 }
610
611 static inline void alchemy_wrsys(unsigned long v, int regofs)
612 {
613 void __iomem *b = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
614
615 __raw_writel(v, b + regofs);
616 wmb(); /* drain writebuffer */
617 }
618
619 /* helpers to access static memctrl registers */
620 static inline unsigned long alchemy_rdsmem(int regofs)
621 {
622 void __iomem *b = (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
623
624 return __raw_readl(b + regofs);
625 }
626
627 static inline void alchemy_wrsmem(unsigned long v, int regofs)
628 {
629 void __iomem *b = (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
630
631 __raw_writel(v, b + regofs);
632 wmb(); /* drain writebuffer */
633 }
634
635 /* Early Au1000 have a write-only SYS_CPUPLL register. */
636 static inline int au1xxx_cpu_has_pll_wo(void)
637 {
638 switch (read_c0_prid()) {
639 case 0x00030100: /* Au1000 DA */
640 case 0x00030201: /* Au1000 HA */
641 case 0x00030202: /* Au1000 HB */
642 return 1;
643 }
644 return 0;
645 }
646
647 /* does CPU need CONFIG[OD] set to fix tons of errata? */
648 static inline int au1xxx_cpu_needs_config_od(void)
649 {
650 /*
651 * c0_config.od (bit 19) was write only (and read as 0) on the
652 * early revisions of Alchemy SOCs. It disables the bus trans-
653 * action overlapping and needs to be set to fix various errata.
654 */
655 switch (read_c0_prid()) {
656 case 0x00030100: /* Au1000 DA */
657 case 0x00030201: /* Au1000 HA */
658 case 0x00030202: /* Au1000 HB */
659 case 0x01030200: /* Au1500 AB */
660 /*
661 * Au1100/Au1200 errata actually keep silence about this bit,
662 * so we set it just in case for those revisions that require
663 * it to be set according to the (now gone) cpu_table.
664 */
665 case 0x02030200: /* Au1100 AB */
666 case 0x02030201: /* Au1100 BA */
667 case 0x02030202: /* Au1100 BC */
668 case 0x04030201: /* Au1200 AC */
669 return 1;
670 }
671 return 0;
672 }
673
674 #define ALCHEMY_CPU_UNKNOWN -1
675 #define ALCHEMY_CPU_AU1000 0
676 #define ALCHEMY_CPU_AU1500 1
677 #define ALCHEMY_CPU_AU1100 2
678 #define ALCHEMY_CPU_AU1550 3
679 #define ALCHEMY_CPU_AU1200 4
680 #define ALCHEMY_CPU_AU1300 5
681
682 static inline int alchemy_get_cputype(void)
683 {
684 switch (read_c0_prid() & (PRID_OPT_MASK | PRID_COMP_MASK)) {
685 case 0x00030000:
686 return ALCHEMY_CPU_AU1000;
687 break;
688 case 0x01030000:
689 return ALCHEMY_CPU_AU1500;
690 break;
691 case 0x02030000:
692 return ALCHEMY_CPU_AU1100;
693 break;
694 case 0x03030000:
695 return ALCHEMY_CPU_AU1550;
696 break;
697 case 0x04030000:
698 case 0x05030000:
699 return ALCHEMY_CPU_AU1200;
700 break;
701 case 0x800c0000:
702 return ALCHEMY_CPU_AU1300;
703 break;
704 }
705
706 return ALCHEMY_CPU_UNKNOWN;
707 }
708
709 /* return number of uarts on a given cputype */
710 static inline int alchemy_get_uarts(int type)
711 {
712 switch (type) {
713 case ALCHEMY_CPU_AU1000:
714 case ALCHEMY_CPU_AU1300:
715 return 4;
716 case ALCHEMY_CPU_AU1500:
717 case ALCHEMY_CPU_AU1200:
718 return 2;
719 case ALCHEMY_CPU_AU1100:
720 case ALCHEMY_CPU_AU1550:
721 return 3;
722 }
723 return 0;
724 }
725
726 /* enable an UART block if it isn't already */
727 static inline void alchemy_uart_enable(u32 uart_phys)
728 {
729 void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
730
731 /* reset, enable clock, deassert reset */
732 if ((__raw_readl(addr + 0x100) & 3) != 3) {
733 __raw_writel(0, addr + 0x100);
734 wmb(); /* drain writebuffer */
735 __raw_writel(1, addr + 0x100);
736 wmb(); /* drain writebuffer */
737 }
738 __raw_writel(3, addr + 0x100);
739 wmb(); /* drain writebuffer */
740 }
741
742 static inline void alchemy_uart_disable(u32 uart_phys)
743 {
744 void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
745
746 __raw_writel(0, addr + 0x100); /* UART_MOD_CNTRL */
747 wmb(); /* drain writebuffer */
748 }
749
750 static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
751 {
752 void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys);
753 int timeout, i;
754
755 /* check LSR TX_EMPTY bit */
756 timeout = 0xffffff;
757 do {
758 if (__raw_readl(base + 0x1c) & 0x20)
759 break;
760 /* slow down */
761 for (i = 10000; i; i--)
762 asm volatile ("nop");
763 } while (--timeout);
764
765 __raw_writel(c, base + 0x04); /* tx */
766 wmb(); /* drain writebuffer */
767 }
768
769 /* return number of ethernet MACs on a given cputype */
770 static inline int alchemy_get_macs(int type)
771 {
772 switch (type) {
773 case ALCHEMY_CPU_AU1000:
774 case ALCHEMY_CPU_AU1500:
775 case ALCHEMY_CPU_AU1550:
776 return 2;
777 case ALCHEMY_CPU_AU1100:
778 return 1;
779 }
780 return 0;
781 }
782
783 /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
784 void alchemy_sleep_au1000(void);
785 void alchemy_sleep_au1550(void);
786 void alchemy_sleep_au1300(void);
787 void au_sleep(void);
788
789 /* USB: arch/mips/alchemy/common/usb.c */
790 enum alchemy_usb_block {
791 ALCHEMY_USB_OHCI0,
792 ALCHEMY_USB_UDC0,
793 ALCHEMY_USB_EHCI0,
794 ALCHEMY_USB_OTG0,
795 ALCHEMY_USB_OHCI1,
796 };
797 int alchemy_usb_control(int block, int enable);
798
799 /* PCI controller platform data */
800 struct alchemy_pci_platdata {
801 int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin);
802 int (*board_pci_idsel)(unsigned int devsel, int assert);
803 /* bits to set/clear in PCI_CONFIG register */
804 unsigned long pci_cfg_set;
805 unsigned long pci_cfg_clr;
806 };
807
808 /* The IrDA peripheral has an IRFIRSEL pin, but on the DB/PB boards it's
809 * not used to select FIR/SIR mode on the transceiver but as a GPIO.
810 * Instead a CPLD has to be told about the mode. The driver calls the
811 * set_phy_mode() function in addition to driving the IRFIRSEL pin.
812 */
813 #define AU1000_IRDA_PHY_MODE_OFF 0
814 #define AU1000_IRDA_PHY_MODE_SIR 1
815 #define AU1000_IRDA_PHY_MODE_FIR 2
816
817 struct au1k_irda_platform_data {
818 void (*set_phy_mode)(int mode);
819 };
820
821
822 /* Multifunction pins: Each of these pins can either be assigned to the
823 * GPIO controller or a on-chip peripheral.
824 * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to
825 * assign one of these to either the GPIO controller or the device.
826 */
827 enum au1300_multifunc_pins {
828 /* wake-from-str pins 0-3 */
829 AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2,
830 AU1300_PIN_WAKE3,
831 /* external clock sources for PSCs: 4-5 */
832 AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1,
833 /* 8bit MMC interface on SD0: 6-9 */
834 AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6,
835 AU1300_PIN_SD0DAT7,
836 /* aux clk input for freqgen 3: 10 */
837 AU1300_PIN_FG3AUX,
838 /* UART1 pins: 11-18 */
839 AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR,
840 AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR,
841 AU1300_PIN_U1RX, AU1300_PIN_U1TX,
842 /* UART0 pins: 19-24 */
843 AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR,
844 AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR,
845 /* UART2: 25-26 */
846 AU1300_PIN_U2RX, AU1300_PIN_U2TX,
847 /* UART3: 27-28 */
848 AU1300_PIN_U3RX, AU1300_PIN_U3TX,
849 /* LCD controller PWMs, ext pixclock: 29-31 */
850 AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
851 /* SD1 interface: 32-37 */
852 AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2,
853 AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK,
854 /* SD2 interface: 38-43 */
855 AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2,
856 AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
857 /* PSC0/1 clocks: 44-45 */
858 AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK,
859 /* PSCs: 46-49/50-53/54-57/58-61 */
860 AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0,
861 AU1300_PIN_PSC0D1,
862 AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
863 AU1300_PIN_PSC1D1,
864 AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0,
865 AU1300_PIN_PSC2D1,
866 AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
867 AU1300_PIN_PSC3D1,
868 /* PCMCIA interface: 62-70 */
869 AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16,
870 AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
871 AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW,
872 /* camera interface H/V sync inputs: 71-72 */
873 AU1300_PIN_CIMLS, AU1300_PIN_CIMFS,
874 /* PSC2/3 clocks: 73-74 */
875 AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK,
876 };
877
878 /* GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c */
879 extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio);
880 extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio);
881 extern void au1300_set_irq_priority(unsigned int irq, int p);
882 extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio);
883
884 /* Au1300 allows to disconnect certain blocks from internal power supply */
885 enum au1300_vss_block {
886 AU1300_VSS_MPE = 0,
887 AU1300_VSS_BSA,
888 AU1300_VSS_GPE,
889 AU1300_VSS_MGP,
890 };
891
892 extern void au1300_vss_block_control(int block, int enable);
893
894 enum soc_au1000_ints {
895 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
896 AU1000_UART0_INT = AU1000_FIRST_INT,
897 AU1000_UART1_INT,
898 AU1000_UART2_INT,
899 AU1000_UART3_INT,
900 AU1000_SSI0_INT,
901 AU1000_SSI1_INT,
902 AU1000_DMA_INT_BASE,
903
904 AU1000_TOY_INT = AU1000_FIRST_INT + 14,
905 AU1000_TOY_MATCH0_INT,
906 AU1000_TOY_MATCH1_INT,
907 AU1000_TOY_MATCH2_INT,
908 AU1000_RTC_INT,
909 AU1000_RTC_MATCH0_INT,
910 AU1000_RTC_MATCH1_INT,
911 AU1000_RTC_MATCH2_INT,
912 AU1000_IRDA_TX_INT,
913 AU1000_IRDA_RX_INT,
914 AU1000_USB_DEV_REQ_INT,
915 AU1000_USB_DEV_SUS_INT,
916 AU1000_USB_HOST_INT,
917 AU1000_ACSYNC_INT,
918 AU1000_MAC0_DMA_INT,
919 AU1000_MAC1_DMA_INT,
920 AU1000_I2S_UO_INT,
921 AU1000_AC97C_INT,
922 AU1000_GPIO0_INT,
923 AU1000_GPIO1_INT,
924 AU1000_GPIO2_INT,
925 AU1000_GPIO3_INT,
926 AU1000_GPIO4_INT,
927 AU1000_GPIO5_INT,
928 AU1000_GPIO6_INT,
929 AU1000_GPIO7_INT,
930 AU1000_GPIO8_INT,
931 AU1000_GPIO9_INT,
932 AU1000_GPIO10_INT,
933 AU1000_GPIO11_INT,
934 AU1000_GPIO12_INT,
935 AU1000_GPIO13_INT,
936 AU1000_GPIO14_INT,
937 AU1000_GPIO15_INT,
938 AU1000_GPIO16_INT,
939 AU1000_GPIO17_INT,
940 AU1000_GPIO18_INT,
941 AU1000_GPIO19_INT,
942 AU1000_GPIO20_INT,
943 AU1000_GPIO21_INT,
944 AU1000_GPIO22_INT,
945 AU1000_GPIO23_INT,
946 AU1000_GPIO24_INT,
947 AU1000_GPIO25_INT,
948 AU1000_GPIO26_INT,
949 AU1000_GPIO27_INT,
950 AU1000_GPIO28_INT,
951 AU1000_GPIO29_INT,
952 AU1000_GPIO30_INT,
953 AU1000_GPIO31_INT,
954 };
955
956 enum soc_au1100_ints {
957 AU1100_FIRST_INT = AU1000_INTC0_INT_BASE,
958 AU1100_UART0_INT = AU1100_FIRST_INT,
959 AU1100_UART1_INT,
960 AU1100_SD_INT,
961 AU1100_UART3_INT,
962 AU1100_SSI0_INT,
963 AU1100_SSI1_INT,
964 AU1100_DMA_INT_BASE,
965
966 AU1100_TOY_INT = AU1100_FIRST_INT + 14,
967 AU1100_TOY_MATCH0_INT,
968 AU1100_TOY_MATCH1_INT,
969 AU1100_TOY_MATCH2_INT,
970 AU1100_RTC_INT,
971 AU1100_RTC_MATCH0_INT,
972 AU1100_RTC_MATCH1_INT,
973 AU1100_RTC_MATCH2_INT,
974 AU1100_IRDA_TX_INT,
975 AU1100_IRDA_RX_INT,
976 AU1100_USB_DEV_REQ_INT,
977 AU1100_USB_DEV_SUS_INT,
978 AU1100_USB_HOST_INT,
979 AU1100_ACSYNC_INT,
980 AU1100_MAC0_DMA_INT,
981 AU1100_GPIO208_215_INT,
982 AU1100_LCD_INT,
983 AU1100_AC97C_INT,
984 AU1100_GPIO0_INT,
985 AU1100_GPIO1_INT,
986 AU1100_GPIO2_INT,
987 AU1100_GPIO3_INT,
988 AU1100_GPIO4_INT,
989 AU1100_GPIO5_INT,
990 AU1100_GPIO6_INT,
991 AU1100_GPIO7_INT,
992 AU1100_GPIO8_INT,
993 AU1100_GPIO9_INT,
994 AU1100_GPIO10_INT,
995 AU1100_GPIO11_INT,
996 AU1100_GPIO12_INT,
997 AU1100_GPIO13_INT,
998 AU1100_GPIO14_INT,
999 AU1100_GPIO15_INT,
1000 AU1100_GPIO16_INT,
1001 AU1100_GPIO17_INT,
1002 AU1100_GPIO18_INT,
1003 AU1100_GPIO19_INT,
1004 AU1100_GPIO20_INT,
1005 AU1100_GPIO21_INT,
1006 AU1100_GPIO22_INT,
1007 AU1100_GPIO23_INT,
1008 AU1100_GPIO24_INT,
1009 AU1100_GPIO25_INT,
1010 AU1100_GPIO26_INT,
1011 AU1100_GPIO27_INT,
1012 AU1100_GPIO28_INT,
1013 AU1100_GPIO29_INT,
1014 AU1100_GPIO30_INT,
1015 AU1100_GPIO31_INT,
1016 };
1017
1018 enum soc_au1500_ints {
1019 AU1500_FIRST_INT = AU1000_INTC0_INT_BASE,
1020 AU1500_UART0_INT = AU1500_FIRST_INT,
1021 AU1500_PCI_INTA,
1022 AU1500_PCI_INTB,
1023 AU1500_UART3_INT,
1024 AU1500_PCI_INTC,
1025 AU1500_PCI_INTD,
1026 AU1500_DMA_INT_BASE,
1027
1028 AU1500_TOY_INT = AU1500_FIRST_INT + 14,
1029 AU1500_TOY_MATCH0_INT,
1030 AU1500_TOY_MATCH1_INT,
1031 AU1500_TOY_MATCH2_INT,
1032 AU1500_RTC_INT,
1033 AU1500_RTC_MATCH0_INT,
1034 AU1500_RTC_MATCH1_INT,
1035 AU1500_RTC_MATCH2_INT,
1036 AU1500_PCI_ERR_INT,
1037 AU1500_RESERVED_INT,
1038 AU1500_USB_DEV_REQ_INT,
1039 AU1500_USB_DEV_SUS_INT,
1040 AU1500_USB_HOST_INT,
1041 AU1500_ACSYNC_INT,
1042 AU1500_MAC0_DMA_INT,
1043 AU1500_MAC1_DMA_INT,
1044 AU1500_AC97C_INT = AU1500_FIRST_INT + 31,
1045 AU1500_GPIO0_INT,
1046 AU1500_GPIO1_INT,
1047 AU1500_GPIO2_INT,
1048 AU1500_GPIO3_INT,
1049 AU1500_GPIO4_INT,
1050 AU1500_GPIO5_INT,
1051 AU1500_GPIO6_INT,
1052 AU1500_GPIO7_INT,
1053 AU1500_GPIO8_INT,
1054 AU1500_GPIO9_INT,
1055 AU1500_GPIO10_INT,
1056 AU1500_GPIO11_INT,
1057 AU1500_GPIO12_INT,
1058 AU1500_GPIO13_INT,
1059 AU1500_GPIO14_INT,
1060 AU1500_GPIO15_INT,
1061 AU1500_GPIO200_INT,
1062 AU1500_GPIO201_INT,
1063 AU1500_GPIO202_INT,
1064 AU1500_GPIO203_INT,
1065 AU1500_GPIO20_INT,
1066 AU1500_GPIO204_INT,
1067 AU1500_GPIO205_INT,
1068 AU1500_GPIO23_INT,
1069 AU1500_GPIO24_INT,
1070 AU1500_GPIO25_INT,
1071 AU1500_GPIO26_INT,
1072 AU1500_GPIO27_INT,
1073 AU1500_GPIO28_INT,
1074 AU1500_GPIO206_INT,
1075 AU1500_GPIO207_INT,
1076 AU1500_GPIO208_215_INT,
1077 };
1078
1079 enum soc_au1550_ints {
1080 AU1550_FIRST_INT = AU1000_INTC0_INT_BASE,
1081 AU1550_UART0_INT = AU1550_FIRST_INT,
1082 AU1550_PCI_INTA,
1083 AU1550_PCI_INTB,
1084 AU1550_DDMA_INT,
1085 AU1550_CRYPTO_INT,
1086 AU1550_PCI_INTC,
1087 AU1550_PCI_INTD,
1088 AU1550_PCI_RST_INT,
1089 AU1550_UART1_INT,
1090 AU1550_UART3_INT,
1091 AU1550_PSC0_INT,
1092 AU1550_PSC1_INT,
1093 AU1550_PSC2_INT,
1094 AU1550_PSC3_INT,
1095 AU1550_TOY_INT,
1096 AU1550_TOY_MATCH0_INT,
1097 AU1550_TOY_MATCH1_INT,
1098 AU1550_TOY_MATCH2_INT,
1099 AU1550_RTC_INT,
1100 AU1550_RTC_MATCH0_INT,
1101 AU1550_RTC_MATCH1_INT,
1102 AU1550_RTC_MATCH2_INT,
1103
1104 AU1550_NAND_INT = AU1550_FIRST_INT + 23,
1105 AU1550_USB_DEV_REQ_INT,
1106 AU1550_USB_DEV_SUS_INT,
1107 AU1550_USB_HOST_INT,
1108 AU1550_MAC0_DMA_INT,
1109 AU1550_MAC1_DMA_INT,
1110 AU1550_GPIO0_INT = AU1550_FIRST_INT + 32,
1111 AU1550_GPIO1_INT,
1112 AU1550_GPIO2_INT,
1113 AU1550_GPIO3_INT,
1114 AU1550_GPIO4_INT,
1115 AU1550_GPIO5_INT,
1116 AU1550_GPIO6_INT,
1117 AU1550_GPIO7_INT,
1118 AU1550_GPIO8_INT,
1119 AU1550_GPIO9_INT,
1120 AU1550_GPIO10_INT,
1121 AU1550_GPIO11_INT,
1122 AU1550_GPIO12_INT,
1123 AU1550_GPIO13_INT,
1124 AU1550_GPIO14_INT,
1125 AU1550_GPIO15_INT,
1126 AU1550_GPIO200_INT,
1127 AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */
1128 AU1550_GPIO16_INT,
1129 AU1550_GPIO17_INT,
1130 AU1550_GPIO20_INT,
1131 AU1550_GPIO21_INT,
1132 AU1550_GPIO22_INT,
1133 AU1550_GPIO23_INT,
1134 AU1550_GPIO24_INT,
1135 AU1550_GPIO25_INT,
1136 AU1550_GPIO26_INT,
1137 AU1550_GPIO27_INT,
1138 AU1550_GPIO28_INT,
1139 AU1550_GPIO206_INT,
1140 AU1550_GPIO207_INT,
1141 AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */
1142 };
1143
1144 enum soc_au1200_ints {
1145 AU1200_FIRST_INT = AU1000_INTC0_INT_BASE,
1146 AU1200_UART0_INT = AU1200_FIRST_INT,
1147 AU1200_SWT_INT,
1148 AU1200_SD_INT,
1149 AU1200_DDMA_INT,
1150 AU1200_MAE_BE_INT,
1151 AU1200_GPIO200_INT,
1152 AU1200_GPIO201_INT,
1153 AU1200_GPIO202_INT,
1154 AU1200_UART1_INT,
1155 AU1200_MAE_FE_INT,
1156 AU1200_PSC0_INT,
1157 AU1200_PSC1_INT,
1158 AU1200_AES_INT,
1159 AU1200_CAMERA_INT,
1160 AU1200_TOY_INT,
1161 AU1200_TOY_MATCH0_INT,
1162 AU1200_TOY_MATCH1_INT,
1163 AU1200_TOY_MATCH2_INT,
1164 AU1200_RTC_INT,
1165 AU1200_RTC_MATCH0_INT,
1166 AU1200_RTC_MATCH1_INT,
1167 AU1200_RTC_MATCH2_INT,
1168 AU1200_GPIO203_INT,
1169 AU1200_NAND_INT,
1170 AU1200_GPIO204_INT,
1171 AU1200_GPIO205_INT,
1172 AU1200_GPIO206_INT,
1173 AU1200_GPIO207_INT,
1174 AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */
1175 AU1200_USB_INT,
1176 AU1200_LCD_INT,
1177 AU1200_MAE_BOTH_INT,
1178 AU1200_GPIO0_INT,
1179 AU1200_GPIO1_INT,
1180 AU1200_GPIO2_INT,
1181 AU1200_GPIO3_INT,
1182 AU1200_GPIO4_INT,
1183 AU1200_GPIO5_INT,
1184 AU1200_GPIO6_INT,
1185 AU1200_GPIO7_INT,
1186 AU1200_GPIO8_INT,
1187 AU1200_GPIO9_INT,
1188 AU1200_GPIO10_INT,
1189 AU1200_GPIO11_INT,
1190 AU1200_GPIO12_INT,
1191 AU1200_GPIO13_INT,
1192 AU1200_GPIO14_INT,
1193 AU1200_GPIO15_INT,
1194 AU1200_GPIO16_INT,
1195 AU1200_GPIO17_INT,
1196 AU1200_GPIO18_INT,
1197 AU1200_GPIO19_INT,
1198 AU1200_GPIO20_INT,
1199 AU1200_GPIO21_INT,
1200 AU1200_GPIO22_INT,
1201 AU1200_GPIO23_INT,
1202 AU1200_GPIO24_INT,
1203 AU1200_GPIO25_INT,
1204 AU1200_GPIO26_INT,
1205 AU1200_GPIO27_INT,
1206 AU1200_GPIO28_INT,
1207 AU1200_GPIO29_INT,
1208 AU1200_GPIO30_INT,
1209 AU1200_GPIO31_INT,
1210 };
1211
1212 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
1213
1214 #endif
1215
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