1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1550 Descriptor
5 * Based DMA Controller.
6 *
7 * Copyright 2004 Embedded Edge, LLC
8 * dan@embeddededge.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31 /*
32 * Specifics for the Au1xxx Descriptor-Based DMA Controller,
33 * first seen in the AU1550 part.
34 */
35 #ifndef _AU1000_DBDMA_H_
36 #define _AU1000_DBDMA_H_
37
38 #ifndef _LANGUAGE_ASSEMBLY
39
40 typedef volatile struct dbdma_global {
41 u32 ddma_config;
42 u32 ddma_intstat;
43 u32 ddma_throttle;
44 u32 ddma_inten;
45 } dbdma_global_t;
46
47 /* General Configuration. */
48 #define DDMA_CONFIG_AF (1 << 2)
49 #define DDMA_CONFIG_AH (1 << 1)
50 #define DDMA_CONFIG_AL (1 << 0)
51
52 #define DDMA_THROTTLE_EN (1 << 31)
53
54 /* The structure of a DMA Channel. */
55 typedef volatile struct au1xxx_dma_channel {
56 u32 ddma_cfg; /* See below */
57 u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */
58 u32 ddma_statptr; /* word aligned pointer to status word */
59 u32 ddma_dbell; /* A write activates channel operation */
60 u32 ddma_irq; /* If bit 0 set, interrupt pending */
61 u32 ddma_stat; /* See below */
62 u32 ddma_bytecnt; /* Byte count, valid only when chan idle */
63 /* Remainder, up to the 256 byte boundary, is reserved. */
64 } au1x_dma_chan_t;
65
66 #define DDMA_CFG_SED (1 << 9) /* source DMA level/edge detect */
67 #define DDMA_CFG_SP (1 << 8) /* source DMA polarity */
68 #define DDMA_CFG_DED (1 << 7) /* destination DMA level/edge detect */
69 #define DDMA_CFG_DP (1 << 6) /* destination DMA polarity */
70 #define DDMA_CFG_SYNC (1 << 5) /* Sync static bus controller */
71 #define DDMA_CFG_PPR (1 << 4) /* PCI posted read/write control */
72 #define DDMA_CFG_DFN (1 << 3) /* Descriptor fetch non-coherent */
73 #define DDMA_CFG_SBE (1 << 2) /* Source big endian */
74 #define DDMA_CFG_DBE (1 << 1) /* Destination big endian */
75 #define DDMA_CFG_EN (1 << 0) /* Channel enable */
76
77 /*
78 * Always set when descriptor processing done, regardless of
79 * interrupt enable state. Reflected in global intstat, don't
80 * clear this until global intstat is read/used.
81 */
82 #define DDMA_IRQ_IN (1 << 0)
83
84 #define DDMA_STAT_DB (1 << 2) /* Doorbell pushed */
85 #define DDMA_STAT_V (1 << 1) /* Descriptor valid */
86 #define DDMA_STAT_H (1 << 0) /* Channel Halted */
87
88 /*
89 * "Standard" DDMA Descriptor.
90 * Must be 32-byte aligned.
91 */
92 typedef volatile struct au1xxx_ddma_desc {
93 u32 dscr_cmd0; /* See below */
94 u32 dscr_cmd1; /* See below */
95 u32 dscr_source0; /* source phys address */
96 u32 dscr_source1; /* See below */
97 u32 dscr_dest0; /* Destination address */
98 u32 dscr_dest1; /* See below */
99 u32 dscr_stat; /* completion status */
100 u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */
101 /*
102 * First 32 bytes are HW specific!!!
103 * Let's have some SW data following -- make sure it's 32 bytes.
104 */
105 u32 sw_status;
106 u32 sw_context;
107 u32 sw_reserved[6];
108 } au1x_ddma_desc_t;
109
110 #define DSCR_CMD0_V (1 << 31) /* Descriptor valid */
111 #define DSCR_CMD0_MEM (1 << 30) /* mem-mem transfer */
112 #define DSCR_CMD0_SID_MASK (0x1f << 25) /* Source ID */
113 #define DSCR_CMD0_DID_MASK (0x1f << 20) /* Destination ID */
114 #define DSCR_CMD0_SW_MASK (0x3 << 18) /* Source Width */
115 #define DSCR_CMD0_DW_MASK (0x3 << 16) /* Destination Width */
116 #define DSCR_CMD0_ARB (0x1 << 15) /* Set for Hi Pri */
117 #define DSCR_CMD0_DT_MASK (0x3 << 13) /* Descriptor Type */
118 #define DSCR_CMD0_SN (0x1 << 12) /* Source non-coherent */
119 #define DSCR_CMD0_DN (0x1 << 11) /* Destination non-coherent */
120 #define DSCR_CMD0_SM (0x1 << 10) /* Stride mode */
121 #define DSCR_CMD0_IE (0x1 << 8) /* Interrupt Enable */
122 #define DSCR_CMD0_SP (0x1 << 4) /* Status pointer select */
123 #define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */
124 #define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */
125
126 #define SW_STATUS_INUSE (1 << 0)
127
128 /* Command 0 device IDs. */
129 #define AU1550_DSCR_CMD0_UART0_TX 0
130 #define AU1550_DSCR_CMD0_UART0_RX 1
131 #define AU1550_DSCR_CMD0_UART3_TX 2
132 #define AU1550_DSCR_CMD0_UART3_RX 3
133 #define AU1550_DSCR_CMD0_DMA_REQ0 4
134 #define AU1550_DSCR_CMD0_DMA_REQ1 5
135 #define AU1550_DSCR_CMD0_DMA_REQ2 6
136 #define AU1550_DSCR_CMD0_DMA_REQ3 7
137 #define AU1550_DSCR_CMD0_USBDEV_RX0 8
138 #define AU1550_DSCR_CMD0_USBDEV_TX0 9
139 #define AU1550_DSCR_CMD0_USBDEV_TX1 10
140 #define AU1550_DSCR_CMD0_USBDEV_TX2 11
141 #define AU1550_DSCR_CMD0_USBDEV_RX3 12
142 #define AU1550_DSCR_CMD0_USBDEV_RX4 13
143 #define AU1550_DSCR_CMD0_PSC0_TX 14
144 #define AU1550_DSCR_CMD0_PSC0_RX 15
145 #define AU1550_DSCR_CMD0_PSC1_TX 16
146 #define AU1550_DSCR_CMD0_PSC1_RX 17
147 #define AU1550_DSCR_CMD0_PSC2_TX 18
148 #define AU1550_DSCR_CMD0_PSC2_RX 19
149 #define AU1550_DSCR_CMD0_PSC3_TX 20
150 #define AU1550_DSCR_CMD0_PSC3_RX 21
151 #define AU1550_DSCR_CMD0_PCI_WRITE 22
152 #define AU1550_DSCR_CMD0_NAND_FLASH 23
153 #define AU1550_DSCR_CMD0_MAC0_RX 24
154 #define AU1550_DSCR_CMD0_MAC0_TX 25
155 #define AU1550_DSCR_CMD0_MAC1_RX 26
156 #define AU1550_DSCR_CMD0_MAC1_TX 27
157
158 #define AU1200_DSCR_CMD0_UART0_TX 0
159 #define AU1200_DSCR_CMD0_UART0_RX 1
160 #define AU1200_DSCR_CMD0_UART1_TX 2
161 #define AU1200_DSCR_CMD0_UART1_RX 3
162 #define AU1200_DSCR_CMD0_DMA_REQ0 4
163 #define AU1200_DSCR_CMD0_DMA_REQ1 5
164 #define AU1200_DSCR_CMD0_MAE_BE 6
165 #define AU1200_DSCR_CMD0_MAE_FE 7
166 #define AU1200_DSCR_CMD0_SDMS_TX0 8
167 #define AU1200_DSCR_CMD0_SDMS_RX0 9
168 #define AU1200_DSCR_CMD0_SDMS_TX1 10
169 #define AU1200_DSCR_CMD0_SDMS_RX1 11
170 #define AU1200_DSCR_CMD0_AES_TX 13
171 #define AU1200_DSCR_CMD0_AES_RX 12
172 #define AU1200_DSCR_CMD0_PSC0_TX 14
173 #define AU1200_DSCR_CMD0_PSC0_RX 15
174 #define AU1200_DSCR_CMD0_PSC1_TX 16
175 #define AU1200_DSCR_CMD0_PSC1_RX 17
176 #define AU1200_DSCR_CMD0_CIM_RXA 18
177 #define AU1200_DSCR_CMD0_CIM_RXB 19
178 #define AU1200_DSCR_CMD0_CIM_RXC 20
179 #define AU1200_DSCR_CMD0_MAE_BOTH 21
180 #define AU1200_DSCR_CMD0_LCD 22
181 #define AU1200_DSCR_CMD0_NAND_FLASH 23
182 #define AU1200_DSCR_CMD0_PSC0_SYNC 24
183 #define AU1200_DSCR_CMD0_PSC1_SYNC 25
184 #define AU1200_DSCR_CMD0_CIM_SYNC 26
185
186 #define AU1300_DSCR_CMD0_UART0_TX 0
187 #define AU1300_DSCR_CMD0_UART0_RX 1
188 #define AU1300_DSCR_CMD0_UART1_TX 2
189 #define AU1300_DSCR_CMD0_UART1_RX 3
190 #define AU1300_DSCR_CMD0_UART2_TX 4
191 #define AU1300_DSCR_CMD0_UART2_RX 5
192 #define AU1300_DSCR_CMD0_UART3_TX 6
193 #define AU1300_DSCR_CMD0_UART3_RX 7
194 #define AU1300_DSCR_CMD0_SDMS_TX0 8
195 #define AU1300_DSCR_CMD0_SDMS_RX0 9
196 #define AU1300_DSCR_CMD0_SDMS_TX1 10
197 #define AU1300_DSCR_CMD0_SDMS_RX1 11
198 #define AU1300_DSCR_CMD0_AES_TX 12
199 #define AU1300_DSCR_CMD0_AES_RX 13
200 #define AU1300_DSCR_CMD0_PSC0_TX 14
201 #define AU1300_DSCR_CMD0_PSC0_RX 15
202 #define AU1300_DSCR_CMD0_PSC1_TX 16
203 #define AU1300_DSCR_CMD0_PSC1_RX 17
204 #define AU1300_DSCR_CMD0_PSC2_TX 18
205 #define AU1300_DSCR_CMD0_PSC2_RX 19
206 #define AU1300_DSCR_CMD0_PSC3_TX 20
207 #define AU1300_DSCR_CMD0_PSC3_RX 21
208 #define AU1300_DSCR_CMD0_LCD 22
209 #define AU1300_DSCR_CMD0_NAND_FLASH 23
210 #define AU1300_DSCR_CMD0_SDMS_TX2 24
211 #define AU1300_DSCR_CMD0_SDMS_RX2 25
212 #define AU1300_DSCR_CMD0_CIM_SYNC 26
213 #define AU1300_DSCR_CMD0_UDMA 27
214 #define AU1300_DSCR_CMD0_DMA_REQ0 28
215 #define AU1300_DSCR_CMD0_DMA_REQ1 29
216
217 #define DSCR_CMD0_THROTTLE 30
218 #define DSCR_CMD0_ALWAYS 31
219 #define DSCR_NDEV_IDS 32
220 /* This macro is used to find/create custom device types */
221 #define DSCR_DEV2CUSTOM_ID(x, d) (((((x) & 0xFFFF) << 8) | 0x32000000) | \
222 ((d) & 0xFF))
223 #define DSCR_CUSTOM2DEV_ID(x) ((x) & 0xFF)
224
225 #define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25)
226 #define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20)
227
228 /* Source/Destination transfer width. */
229 #define DSCR_CMD0_BYTE 0
230 #define DSCR_CMD0_HALFWORD 1
231 #define DSCR_CMD0_WORD 2
232
233 #define DSCR_CMD0_SW(x) (((x) & 0x3) << 18)
234 #define DSCR_CMD0_DW(x) (((x) & 0x3) << 16)
235
236 /* DDMA Descriptor Type. */
237 #define DSCR_CMD0_STANDARD 0
238 #define DSCR_CMD0_LITERAL 1
239 #define DSCR_CMD0_CMP_BRANCH 2
240
241 #define DSCR_CMD0_DT(x) (((x) & 0x3) << 13)
242
243 /* Status Instruction. */
244 #define DSCR_CMD0_ST_NOCHANGE 0 /* Don't change */
245 #define DSCR_CMD0_ST_CURRENT 1 /* Write current status */
246 #define DSCR_CMD0_ST_CMD0 2 /* Write cmd0 with V cleared */
247 #define DSCR_CMD0_ST_BYTECNT 3 /* Write remaining byte count */
248
249 #define DSCR_CMD0_ST(x) (((x) & 0x3) << 0)
250
251 /* Descriptor Command 1. */
252 #define DSCR_CMD1_SUPTR_MASK (0xf << 28) /* upper 4 bits of src addr */
253 #define DSCR_CMD1_DUPTR_MASK (0xf << 24) /* upper 4 bits of dest addr */
254 #define DSCR_CMD1_FL_MASK (0x3 << 22) /* Flag bits */
255 #define DSCR_CMD1_BC_MASK (0x3fffff) /* Byte count */
256
257 /* Flag description. */
258 #define DSCR_CMD1_FL_MEM_STRIDE0 0
259 #define DSCR_CMD1_FL_MEM_STRIDE1 1
260 #define DSCR_CMD1_FL_MEM_STRIDE2 2
261
262 #define DSCR_CMD1_FL(x) (((x) & 0x3) << 22)
263
264 /* Source1, 1-dimensional stride. */
265 #define DSCR_SRC1_STS_MASK (3 << 30) /* Src xfer size */
266 #define DSCR_SRC1_SAM_MASK (3 << 28) /* Src xfer movement */
267 #define DSCR_SRC1_SB_MASK (0x3fff << 14) /* Block size */
268 #define DSCR_SRC1_SB(x) (((x) & 0x3fff) << 14)
269 #define DSCR_SRC1_SS_MASK (0x3fff << 0) /* Stride */
270 #define DSCR_SRC1_SS(x) (((x) & 0x3fff) << 0)
271
272 /* Dest1, 1-dimensional stride. */
273 #define DSCR_DEST1_DTS_MASK (3 << 30) /* Dest xfer size */
274 #define DSCR_DEST1_DAM_MASK (3 << 28) /* Dest xfer movement */
275 #define DSCR_DEST1_DB_MASK (0x3fff << 14) /* Block size */
276 #define DSCR_DEST1_DB(x) (((x) & 0x3fff) << 14)
277 #define DSCR_DEST1_DS_MASK (0x3fff << 0) /* Stride */
278 #define DSCR_DEST1_DS(x) (((x) & 0x3fff) << 0)
279
280 #define DSCR_xTS_SIZE1 0
281 #define DSCR_xTS_SIZE2 1
282 #define DSCR_xTS_SIZE4 2
283 #define DSCR_xTS_SIZE8 3
284 #define DSCR_SRC1_STS(x) (((x) & 3) << 30)
285 #define DSCR_DEST1_DTS(x) (((x) & 3) << 30)
286
287 #define DSCR_xAM_INCREMENT 0
288 #define DSCR_xAM_DECREMENT 1
289 #define DSCR_xAM_STATIC 2
290 #define DSCR_xAM_BURST 3
291 #define DSCR_SRC1_SAM(x) (((x) & 3) << 28)
292 #define DSCR_DEST1_DAM(x) (((x) & 3) << 28)
293
294 /* The next descriptor pointer. */
295 #define DSCR_NXTPTR_MASK (0x07ffffff)
296 #define DSCR_NXTPTR(x) ((x) >> 5)
297 #define DSCR_GET_NXTPTR(x) ((x) << 5)
298 #define DSCR_NXTPTR_MS (1 << 27)
299
300 /* The number of DBDMA channels. */
301 #define NUM_DBDMA_CHANS 16
302
303 /*
304 * DDMA API definitions
305 * FIXME: may not fit to this header file
306 */
307 typedef struct dbdma_device_table {
308 u32 dev_id;
309 u32 dev_flags;
310 u32 dev_tsize;
311 u32 dev_devwidth;
312 u32 dev_physaddr; /* If FIFO */
313 u32 dev_intlevel;
314 u32 dev_intpolarity;
315 } dbdev_tab_t;
316
317
318 typedef struct dbdma_chan_config {
319 spinlock_t lock;
320
321 u32 chan_flags;
322 u32 chan_index;
323 dbdev_tab_t *chan_src;
324 dbdev_tab_t *chan_dest;
325 au1x_dma_chan_t *chan_ptr;
326 au1x_ddma_desc_t *chan_desc_base;
327 u32 cdb_membase; /* kmalloc base of above */
328 au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
329 void *chan_callparam;
330 void (*chan_callback)(int, void *);
331 } chan_tab_t;
332
333 #define DEV_FLAGS_INUSE (1 << 0)
334 #define DEV_FLAGS_ANYUSE (1 << 1)
335 #define DEV_FLAGS_OUT (1 << 2)
336 #define DEV_FLAGS_IN (1 << 3)
337 #define DEV_FLAGS_BURSTABLE (1 << 4)
338 #define DEV_FLAGS_SYNC (1 << 5)
339 /* end DDMA API definitions */
340
341 /*
342 * External functions for drivers to use.
343 * Use this to allocate a DBDMA channel. The device IDs are one of
344 * the DSCR_CMD0 devices IDs, which is usually redefined to a more
345 * meaningful name. The 'callback' is called during DMA completion
346 * interrupt.
347 */
348 extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
349 void (*callback)(int, void *),
350 void *callparam);
351
352 #define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS
353
354 /* Set the device width of an in/out FIFO. */
355 u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
356
357 /* Allocate a ring of descriptors for DBDMA. */
358 u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
359
360 /* Put buffers on source/destination descriptors. */
361 u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags);
362 u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags);
363
364 /* Get a buffer from the destination descriptor. */
365 u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
366
367 void au1xxx_dbdma_stop(u32 chanid);
368 void au1xxx_dbdma_start(u32 chanid);
369 void au1xxx_dbdma_reset(u32 chanid);
370 u32 au1xxx_get_dma_residue(u32 chanid);
371
372 void au1xxx_dbdma_chan_free(u32 chanid);
373 void au1xxx_dbdma_dump(u32 chanid);
374
375 u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
376
377 u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
378 extern void au1xxx_ddma_del_device(u32 devid);
379 void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
380
381 /*
382 * Flags for the put_source/put_dest functions.
383 */
384 #define DDMA_FLAGS_IE (1 << 0)
385 #define DDMA_FLAGS_NOIE (1 << 1)
386
387 #endif /* _LANGUAGE_ASSEMBLY */
388 #endif /* _AU1000_DBDMA_H_ */
389
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