1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Copyright (C) 2009 Lemote, Inc.
4 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
5 */
6
7 #ifndef __ASM_MACH_LOONGSON2EF_LOONGSON_H
8 #define __ASM_MACH_LOONGSON2EF_LOONGSON_H
9
10 #include <linux/io.h>
11 #include <linux/init.h>
12 #include <linux/irq.h>
13
14 /* loongson internal northbridge initialization */
15 extern void bonito_irq_init(void);
16
17 /* machine-specific reboot/halt operation */
18 extern void mach_prepare_reboot(void);
19 extern void mach_prepare_shutdown(void);
20
21 /* environment arguments from bootloader */
22 extern u32 cpu_clock_freq;
23 extern u32 memsize, highmemsize;
24
25 /* loongson-specific command line, env and memory initialization */
26 extern void __init prom_init_memory(void);
27 extern void __init prom_init_machtype(void);
28 extern void __init prom_init_env(void);
29 #ifdef CONFIG_LOONGSON_UART_BASE
30 extern unsigned long _loongson_uart_base, loongson_uart_base;
31 extern void prom_init_loongson_uart_base(void);
32 #endif
33
34 static inline void prom_init_uart_base(void)
35 {
36 #ifdef CONFIG_LOONGSON_UART_BASE
37 prom_init_loongson_uart_base();
38 #endif
39 }
40
41 /* irq operation functions */
42 extern void bonito_irqdispatch(void);
43 extern void __init bonito_irq_init(void);
44 extern void __init mach_init_irq(void);
45 extern void mach_irq_dispatch(unsigned int pending);
46 extern int mach_i8259_irq(void);
47
48 /* We need this in some places... */
49 #define delay() ({ \
50 int x; \
51 for (x = 0; x < 100000; x++) \
52 __asm__ __volatile__(""); \
53 })
54
55 #define LOONGSON_REG(x) \
56 (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
57
58 #define LOONGSON_IRQ_BASE 32
59
60 #define LOONGSON_FLASH_BASE 0x1c000000
61 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
62 #define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
63
64 #define LOONGSON_LIO0_BASE 0x1e000000
65 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
66 #define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
67
68 #define LOONGSON_BOOT_BASE 0x1fc00000
69 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
70 #define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
71 #define LOONGSON_REG_BASE 0x1fe00000
72 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
73 #define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
74
75 #define LOONGSON_LIO1_BASE 0x1ff00000
76 #define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */
77 #define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
78
79 #define LOONGSON_PCILO0_BASE 0x10000000
80 #define LOONGSON_PCILO1_BASE 0x14000000
81 #define LOONGSON_PCILO2_BASE 0x18000000
82 #define LOONGSON_PCILO_BASE LOONGSON_PCILO0_BASE
83 #define LOONGSON_PCILO_SIZE 0x0c000000 /* 64M * 3 */
84 #define LOONGSON_PCILO_TOP (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
85
86 #define LOONGSON_PCICFG_BASE 0x1fe80000
87 #define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */
88 #define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
89 #define LOONGSON_PCIIO_BASE 0x1fd00000
90
91 #define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */
92 #define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
93
94 /* Loongson Register Bases */
95
96 #define LOONGSON_PCICONFIGBASE 0x00
97 #define LOONGSON_REGBASE 0x100
98
99 /* PCI Configuration Registers */
100
101 #define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
102 #define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00)
103 #define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04)
104 #define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08)
105 #define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c)
106 #define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10)
107 #define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14)
108 #define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18)
109 #define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c)
110 #define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20)
111 #define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30)
112 #define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c)
113
114 #define LOONGSON_PCI_ISR4C LOONGSON_PCI_REG(0x4c)
115
116 #define LOONGSON_PCICMD_PERR_CLR 0x80000000
117 #define LOONGSON_PCICMD_SERR_CLR 0x40000000
118 #define LOONGSON_PCICMD_MABORT_CLR 0x20000000
119 #define LOONGSON_PCICMD_MTABORT_CLR 0x10000000
120 #define LOONGSON_PCICMD_TABORT_CLR 0x08000000
121 #define LOONGSON_PCICMD_MPERR_CLR 0x01000000
122 #define LOONGSON_PCICMD_PERRRESPEN 0x00000040
123 #define LOONGSON_PCICMD_ASTEPEN 0x00000080
124 #define LOONGSON_PCICMD_SERREN 0x00000100
125 #define LOONGSON_PCILTIMER_BUSLATENCY 0x0000ff00
126 #define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT 8
127
128 /* Loongson h/w Configuration */
129
130 #define LOONGSON_GENCFG_OFFSET 0x4
131 #define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
132
133 #define LOONGSON_GENCFG_DEBUGMODE 0x00000001
134 #define LOONGSON_GENCFG_SNOOPEN 0x00000002
135 #define LOONGSON_GENCFG_CPUSELFRESET 0x00000004
136
137 #define LOONGSON_GENCFG_FORCE_IRQA 0x00000008
138 #define LOONGSON_GENCFG_IRQA_ISOUT 0x00000010
139 #define LOONGSON_GENCFG_IRQA_FROM_INT1 0x00000020
140 #define LOONGSON_GENCFG_BYTESWAP 0x00000040
141
142 #define LOONGSON_GENCFG_UNCACHED 0x00000080
143 #define LOONGSON_GENCFG_PREFETCHEN 0x00000100
144 #define LOONGSON_GENCFG_WBEHINDEN 0x00000200
145 #define LOONGSON_GENCFG_CACHEALG 0x00000c00
146 #define LOONGSON_GENCFG_CACHEALG_SHIFT 10
147 #define LOONGSON_GENCFG_PCIQUEUE 0x00001000
148 #define LOONGSON_GENCFG_CACHESTOP 0x00002000
149 #define LOONGSON_GENCFG_MSTRBYTESWAP 0x00004000
150 #define LOONGSON_GENCFG_BUSERREN 0x00008000
151 #define LOONGSON_GENCFG_NORETRYTIMEOUT 0x00010000
152 #define LOONGSON_GENCFG_SHORTCOPYTIMEOUT 0x00020000
153
154 /* PCI address map control */
155
156 #define LOONGSON_PCIMAP LOONGSON_REG(LOONGSON_REGBASE + 0x10)
157 #define LOONGSON_PCIMEMBASECFG LOONGSON_REG(LOONGSON_REGBASE + 0x14)
158 #define LOONGSON_PCIMAP_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x18)
159
160 /* GPIO Regs - r/w */
161
162 #define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
163 #define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20)
164
165 /* ICU Configuration Regs - r/w */
166
167 #define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24)
168 #define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28)
169 #define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
170
171 /* ICU Enable Regs - IntEn & IntISR are r/o. */
172
173 #define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30)
174 #define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34)
175 #define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38)
176 #define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
177
178 /* ICU */
179 #define LOONGSON_ICU_MBOXES 0x0000000f
180 #define LOONGSON_ICU_MBOXES_SHIFT 0
181 #define LOONGSON_ICU_DMARDY 0x00000010
182 #define LOONGSON_ICU_DMAEMPTY 0x00000020
183 #define LOONGSON_ICU_COPYRDY 0x00000040
184 #define LOONGSON_ICU_COPYEMPTY 0x00000080
185 #define LOONGSON_ICU_COPYERR 0x00000100
186 #define LOONGSON_ICU_PCIIRQ 0x00000200
187 #define LOONGSON_ICU_MASTERERR 0x00000400
188 #define LOONGSON_ICU_SYSTEMERR 0x00000800
189 #define LOONGSON_ICU_DRAMPERR 0x00001000
190 #define LOONGSON_ICU_RETRYERR 0x00002000
191 #define LOONGSON_ICU_GPIOS 0x01ff0000
192 #define LOONGSON_ICU_GPIOS_SHIFT 16
193 #define LOONGSON_ICU_GPINS 0x7e000000
194 #define LOONGSON_ICU_GPINS_SHIFT 25
195 #define LOONGSON_ICU_MBOX(N) (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
196 #define LOONGSON_ICU_GPIO(N) (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
197 #define LOONGSON_ICU_GPIN(N) (1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
198
199 /* PCI prefetch window base & mask */
200
201 #define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40)
202 #define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44)
203 #define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48)
204 #define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
205
206 /* PCI_Hit*_Sel_* */
207
208 #define LOONGSON_PCI_HIT0_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x50)
209 #define LOONGSON_PCI_HIT0_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x54)
210 #define LOONGSON_PCI_HIT1_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x58)
211 #define LOONGSON_PCI_HIT1_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
212 #define LOONGSON_PCI_HIT2_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x60)
213 #define LOONGSON_PCI_HIT2_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x64)
214
215 /* PXArb Config & Status */
216
217 #define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68)
218 #define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
219
220 /* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */
221 #define LOONGSON_CHIPCFG (void __iomem *)TO_UNCAC(0x1fc00180)
222
223 /* pcimap */
224
225 #define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f
226 #define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0
227 #define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0
228 #define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT 6
229 #define LOONGSON_PCIMAP_PCIMAP_LO2 0x0003f000
230 #define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT 12
231 #define LOONGSON_PCIMAP_PCIMAP_2 0x00040000
232 #define LOONGSON_PCIMAP_WIN(WIN, ADDR) \
233 ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
234
235 #ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
236 #include <linux/cpufreq.h>
237 extern struct cpufreq_frequency_table loongson2_clockmod_table[];
238 extern int loongson2_cpu_set_rate(unsigned long rate_khz);
239 #endif
240
241 /*
242 * address windows configuration module
243 *
244 * loongson2e do not have this module
245 */
246 #ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
247
248 /* address window config module base address */
249 #define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul
250 #define LOONGSON_ADDRWINCFG_SIZE 0x180
251
252 extern unsigned long _loongson_addrwincfg_base;
253 #define LOONGSON_ADDRWINCFG(offset) \
254 (*(volatile u64 *)(_loongson_addrwincfg_base + (offset)))
255
256 #define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00)
257 #define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08)
258 #define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10)
259 #define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18)
260
261 #define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20)
262 #define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28)
263 #define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30)
264 #define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38)
265
266 #define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40)
267 #define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48)
268 #define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50)
269 #define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58)
270
271 #define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60)
272 #define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68)
273 #define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70)
274 #define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78)
275
276 #define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80)
277 #define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88)
278 #define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90)
279 #define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98)
280
281 #define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0)
282 #define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8)
283 #define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0)
284 #define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8)
285
286 #define ADDRWIN_WIN0 0
287 #define ADDRWIN_WIN1 1
288 #define ADDRWIN_WIN2 2
289 #define ADDRWIN_WIN3 3
290
291 #define ADDRWIN_MAP_DST_DDR 0
292 #define ADDRWIN_MAP_DST_PCI 1
293 #define ADDRWIN_MAP_DST_LIO 1
294
295 /*
296 * s: CPU, PCIDMA
297 * d: DDR, PCI, LIO
298 * win: 0, 1, 2, 3
299 * src: map source
300 * dst: map destination
301 * size: ~mask + 1
302 */
303 #define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
304 s##_WIN##w##_BASE = (src); \
305 s##_WIN##w##_MMAP = (dst) | ADDRWIN_MAP_DST_##d; \
306 s##_WIN##w##_MASK = ~(size-1); \
307 } while (0)
308
309 #define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
310 LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
311 #define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
312 LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
313 #define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
314 LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
315
316 #endif /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
317
318 #endif /* __ASM_MACH_LOONGSON2EF_LOONGSON_H */
319
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