1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com> 4 * 5 * IRQ mappings for Loongson 1 6 */ 7 8 #ifndef __ASM_MACH_LOONGSON32_IRQ_H 9 #define __ASM_MACH_LOONGSON32_IRQ_H 10 11 /* 12 * CPU core Interrupt Numbers 13 */ 14 #define MIPS_CPU_IRQ_BASE 0 15 #define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) 16 17 #define SOFTINT0_IRQ MIPS_CPU_IRQ(0) 18 #define SOFTINT1_IRQ MIPS_CPU_IRQ(1) 19 #define INT0_IRQ MIPS_CPU_IRQ(2) 20 #define INT1_IRQ MIPS_CPU_IRQ(3) 21 #define INT2_IRQ MIPS_CPU_IRQ(4) 22 #define INT3_IRQ MIPS_CPU_IRQ(5) 23 #define INT4_IRQ MIPS_CPU_IRQ(6) 24 #define TIMER_IRQ MIPS_CPU_IRQ(7) /* cpu timer */ 25 26 #define MIPS_CPU_IRQS (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE) 27 28 /* 29 * INT0~3 Interrupt Numbers 30 */ 31 #define LS1X_IRQ_BASE MIPS_CPU_IRQS 32 #define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x)) 33 34 #define LS1X_UART0_IRQ LS1X_IRQ(0, 2) 35 #if defined(CONFIG_LOONGSON1_LS1B) 36 #define LS1X_UART1_IRQ LS1X_IRQ(0, 3) 37 #define LS1X_UART2_IRQ LS1X_IRQ(0, 4) 38 #define LS1X_UART3_IRQ LS1X_IRQ(0, 5) 39 #elif defined(CONFIG_LOONGSON1_LS1C) 40 #define LS1X_UART1_IRQ LS1X_IRQ(0, 4) 41 #define LS1X_UART2_IRQ LS1X_IRQ(0, 5) 42 #endif 43 #define LS1X_CAN0_IRQ LS1X_IRQ(0, 6) 44 #define LS1X_CAN1_IRQ LS1X_IRQ(0, 7) 45 #define LS1X_SPI0_IRQ LS1X_IRQ(0, 8) 46 #define LS1X_SPI1_IRQ LS1X_IRQ(0, 9) 47 #define LS1X_AC97_IRQ LS1X_IRQ(0, 10) 48 #define LS1X_DMA0_IRQ LS1X_IRQ(0, 13) 49 #define LS1X_DMA1_IRQ LS1X_IRQ(0, 14) 50 #define LS1X_DMA2_IRQ LS1X_IRQ(0, 15) 51 #if defined(CONFIG_LOONGSON1_LS1C) 52 #define LS1X_NAND_IRQ LS1X_IRQ(0, 16) 53 #endif 54 #define LS1X_PWM0_IRQ LS1X_IRQ(0, 17) 55 #define LS1X_PWM1_IRQ LS1X_IRQ(0, 18) 56 #define LS1X_PWM2_IRQ LS1X_IRQ(0, 19) 57 #define LS1X_PWM3_IRQ LS1X_IRQ(0, 20) 58 #define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21) 59 #define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22) 60 #define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23) 61 #if defined(CONFIG_LOONGSON1_LS1B) 62 #define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24) 63 #define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25) 64 #define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26) 65 #define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27) 66 #define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28) 67 #define LS1X_UART4_IRQ LS1X_IRQ(0, 29) 68 #define LS1X_UART5_IRQ LS1X_IRQ(0, 30) 69 #elif defined(CONFIG_LOONGSON1_LS1C) 70 #define LS1X_UART3_IRQ LS1X_IRQ(0, 29) 71 #define LS1X_ADC_IRQ LS1X_IRQ(0, 30) 72 #define LS1X_SDIO_IRQ LS1X_IRQ(0, 31) 73 #endif 74 75 #define LS1X_EHCI_IRQ LS1X_IRQ(1, 0) 76 #define LS1X_OHCI_IRQ LS1X_IRQ(1, 1) 77 #if defined(CONFIG_LOONGSON1_LS1B) 78 #define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2) 79 #define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3) 80 #elif defined(CONFIG_LOONGSON1_LS1C) 81 #define LS1X_OTG_IRQ LS1X_IRQ(1, 2) 82 #define LS1X_GMAC0_IRQ LS1X_IRQ(1, 3) 83 #define LS1X_CAM_IRQ LS1X_IRQ(1, 4) 84 #define LS1X_UART4_IRQ LS1X_IRQ(1, 5) 85 #define LS1X_UART5_IRQ LS1X_IRQ(1, 6) 86 #define LS1X_UART6_IRQ LS1X_IRQ(1, 7) 87 #define LS1X_UART7_IRQ LS1X_IRQ(1, 8) 88 #define LS1X_UART8_IRQ LS1X_IRQ(1, 9) 89 #define LS1X_UART9_IRQ LS1X_IRQ(1, 13) 90 #define LS1X_UART10_IRQ LS1X_IRQ(1, 14) 91 #define LS1X_UART11_IRQ LS1X_IRQ(1, 15) 92 #define LS1X_I2C0_IRQ LS1X_IRQ(1, 17) 93 #define LS1X_I2C1_IRQ LS1X_IRQ(1, 18) 94 #define LS1X_I2C2_IRQ LS1X_IRQ(1, 19) 95 #endif 96 97 #if defined(CONFIG_LOONGSON1_LS1B) 98 #define INTN 4 99 #elif defined(CONFIG_LOONGSON1_LS1C) 100 #define INTN 5 101 #endif 102 103 #define LS1X_IRQS (LS1X_IRQ(INTN, 31) + 1 - LS1X_IRQ_BASE) 104 105 #define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS) 106 107 #endif /* __ASM_MACH_LOONGSON32_IRQ_H */ 108
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