1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 *
4 * Parts of this file are based on Ralink's 2.6.21 BSP
5 *
6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Copyright (C) 2013 John Crispin <john@phrozen.org>
9 */
10
11 #ifndef _MT7620_REGS_H_
12 #define _MT7620_REGS_H_
13
14 #define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x)))
15 #define MT7620_SYSC_BASE IOMEM(0x10000000)
16
17 #define SYSC_REG_CHIP_NAME0 0x00
18 #define SYSC_REG_CHIP_NAME1 0x04
19 #define SYSC_REG_EFUSE_CFG 0x08
20 #define SYSC_REG_CHIP_REV 0x0c
21 #define SYSC_REG_SYSTEM_CONFIG0 0x10
22 #define SYSC_REG_SYSTEM_CONFIG1 0x14
23
24 #define MT7620_CHIP_NAME0 0x3637544d
25 #define MT7620_CHIP_NAME1 0x20203032
26 #define MT7628_CHIP_NAME1 0x20203832
27
28 #define CHIP_REV_PKG_MASK 0x1
29 #define CHIP_REV_PKG_SHIFT 16
30 #define CHIP_REV_VER_MASK 0xf
31 #define CHIP_REV_VER_SHIFT 8
32 #define CHIP_REV_ECO_MASK 0xf
33
34 #define SYSCFG0_DRAM_TYPE_MASK 0x3
35 #define SYSCFG0_DRAM_TYPE_SHIFT 4
36 #define SYSCFG0_DRAM_TYPE_SDRAM 0
37 #define SYSCFG0_DRAM_TYPE_DDR1 1
38 #define SYSCFG0_DRAM_TYPE_DDR2 2
39 #define SYSCFG0_DRAM_TYPE_UNKNOWN 3
40
41 #define SYSCFG0_DRAM_TYPE_DDR2_MT7628 0
42 #define SYSCFG0_DRAM_TYPE_DDR1_MT7628 1
43
44 #define MT7620_DRAM_BASE 0x0
45 #define MT7620_SDRAM_SIZE_MIN 2
46 #define MT7620_SDRAM_SIZE_MAX 64
47 #define MT7620_DDR1_SIZE_MIN 32
48 #define MT7620_DDR1_SIZE_MAX 128
49 #define MT7620_DDR2_SIZE_MIN 32
50 #define MT7620_DDR2_SIZE_MAX 256
51
52 extern enum ralink_soc_type ralink_soc;
53
54 static inline int is_mt76x8(void)
55 {
56 return ralink_soc == MT762X_SOC_MT7628AN ||
57 ralink_soc == MT762X_SOC_MT7688;
58 }
59
60 static inline int mt7620_get_eco(void)
61 {
62 return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
63 }
64
65 #endif
66
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