1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved. 7 * Carsten Langgaard <carstenl@mips.com> 8 * Steven J. Hill <sjhill@mips.com> 9 */ 10 #ifndef _MIPS_MALTAINT_H 11 #define _MIPS_MALTAINT_H 12 13 /* 14 * Interrupts 0..15 are used for Malta ISA compatible interrupts 15 */ 16 #define MALTA_INT_BASE 0 17 18 /* CPU interrupt offsets */ 19 #define MIPSCPU_INT_SW0 0 20 #define MIPSCPU_INT_SW1 1 21 #define MIPSCPU_INT_MB0 2 22 #define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0 23 #define MIPSCPU_INT_GIC MIPSCPU_INT_MB0 /* GIC chained interrupt */ 24 #define MIPSCPU_INT_MB1 3 25 #define MIPSCPU_INT_SMI MIPSCPU_INT_MB1 26 #define MIPSCPU_INT_MB2 4 27 #define MIPSCPU_INT_MB3 5 28 #define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3 29 #define MIPSCPU_INT_MB4 6 30 #define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4 31 32 /* 33 * Interrupts 96..127 are used for Soc-it Classic interrupts 34 */ 35 #define MSC01C_INT_BASE 96 36 37 /* SOC-it Classic interrupt offsets */ 38 #define MSC01C_INT_TMR 0 39 #define MSC01C_INT_PCI 1 40 41 /* 42 * Interrupts 96..127 are used for Soc-it EIC interrupts 43 */ 44 #define MSC01E_INT_BASE 96 45 46 /* SOC-it EIC interrupt offsets */ 47 #define MSC01E_INT_SW0 1 48 #define MSC01E_INT_SW1 2 49 #define MSC01E_INT_MB0 3 50 #define MSC01E_INT_I8259A MSC01E_INT_MB0 51 #define MSC01E_INT_MB1 4 52 #define MSC01E_INT_SMI MSC01E_INT_MB1 53 #define MSC01E_INT_MB2 5 54 #define MSC01E_INT_MB3 6 55 #define MSC01E_INT_COREHI MSC01E_INT_MB3 56 #define MSC01E_INT_MB4 7 57 #define MSC01E_INT_CORELO MSC01E_INT_MB4 58 #define MSC01E_INT_TMR 8 59 #define MSC01E_INT_PCI 9 60 #define MSC01E_INT_PERFCTR 10 61 #define MSC01E_INT_CPUCTR 11 62 63 #endif /* !(_MIPS_MALTAINT_H) */ 64
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