1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2015 Imagination Technologies, Inc. 7 * written by Ralf Baechle <ralf@linux-mips.org> 8 */ 9 #ifndef __ASM_MIPS_BOARDS_SEAD3_ADDR_H 10 #define __ASM_MIPS_BOARDS_SEAD3_ADDR_H 11 12 /* 13 * Target #0 Register Decode 14 */ 15 #define SEAD3_SD_SPDCNF 0xbb000040 16 #define SEAD3_SD_SPADDR 0xbb000048 17 #define SEAD3_SD_DATA 0xbb000050 18 19 /* 20 * Target #1 Register Decode 21 */ 22 #define SEAD3_CFG 0xbb100110 23 #define SEAD3_GIC_BASE_ADDRESS 0xbb1c0000 24 #define SEAD3_SHARED_SECTION 0xbb1c0000 25 #define SEAD3_VPE_LOCAL_SECTION 0xbb1c8000 26 #define SEAD3_VPE_OTHER_SECTION 0xbb1cc000 27 #define SEAD3_USER_MODE_VISIBLE_SECTION 0xbb1d0000 28 29 /* 30 * Target #3 Register Decode 31 */ 32 #define SEAD3_USB_HS_BASE 0xbb200000 33 #define SEAD3_USB_HS_IDENTIFICATION_REGS 0xbb200000 34 #define SEAD3_USB_HS_CAPABILITY_REGS 0xbb200100 35 #define SEAD3_USB_HS_OPERATIONAL_REGS 0xbb200140 36 #define SEAD3_RESERVED 0xbe800000 37 38 /* 39 * Target #3 Register Decode 40 */ 41 #define SEAD3_SRAM 0xbe000000 42 #define SEAD3_OPTIONAL_SRAM 0xbe400000 43 #define SEAD3_FPGA 0xbf000000 44 45 #define SEAD3_PI_PIC32_USB_STATUS 0xbf000060 46 #define SEAD3_PI_PIC32_USB_STATUS_IO_RDY (1 << 0) 47 #define SEAD3_PI_PIC32_USB_STATUS_SPL_INT (1 << 1) 48 #define SEAD3_PI_PIC32_USB_STATUS_GPIOA_INT (1 << 2) 49 #define SEAD3_PI_PIC32_USB_STATUS_GPIOB_INT (1 << 3) 50 51 #define SEAD3_PI_SOFT_ENDIAN 0xbf000070 52 53 #define SEAD3_CPLD_P_SWITCH 0xbf000200 54 #define SEAD3_CPLD_F_SWITCH 0xbf000208 55 #define SEAD3_CPLD_P_LED 0xbf000210 56 #define SEAD3_CPLD_F_LED 0xbf000218 57 #define SEAD3_NEWSC_LIVE 0xbf000220 58 #define SEAD3_NEWSC_REG 0xbf000228 59 #define SEAD3_NEWSC_CTRL 0xbf000230 60 61 #define SEAD3_LCD_CONTROL 0xbf000400 62 #define SEAD3_LCD_DATA 0xbf000408 63 #define SEAD3_CPLD_LCD_STATUS 0xbf000410 64 #define SEAD3_CPLD_LCD_DATA 0xbf000418 65 66 #define SEAD3_CPLD_PI_DEVRST 0xbf000480 67 #define SEAD3_CPLD_PI_DEVRST_IC32_RST (1 << 0) 68 #define SEAD3_RESERVED_0 0xbf000500 69 70 #define SEAD3_PIC32_REGISTERS 0xbf000600 71 #define SEAD3_RESERVED_1 0xbf000700 72 #define SEAD3_UART_CH_0 0xbf000800 73 #define SEAD3_UART_CH_1 0xbf000900 74 #define SEAD3_RESERVED_2 0xbf000a00 75 #define SEAD3_ETHERNET 0xbf010000 76 #define SEAD3_RESERVED_3 0xbf020000 77 #define SEAD3_USER_EXPANSION 0xbf400000 78 #define SEAD3_RESERVED_4 0xbf800000 79 #define SEAD3_BOOT_FLASH_EXTENSION 0xbfa00000 80 #define SEAD3_BOOT_FLASH 0xbfc00000 81 #define SEAD3_REVISION_REGISTER 0xbfc00010 82 83 #endif /* __ASM_MIPS_BOARDS_SEAD3_ADDR_H */ 84
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