1 /***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2012 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28 #ifndef __CVMX_GPIO_DEFS_H__
29 #define __CVMX_GPIO_DEFS_H__
30
31 #define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8)
32 #define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull))
33 #define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8)
34 #define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8)
35 #define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
36 #define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull))
37 #define CVMX_GPIO_MULTI_CAST (CVMX_ADD_IO_SEG(0x00010700000008B0ull))
38 #define CVMX_GPIO_PIN_ENA (CVMX_ADD_IO_SEG(0x00010700000008B8ull))
39 #define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull))
40 #define CVMX_GPIO_TIM_CTL (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
41 #define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull))
42 #define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull))
43 #define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16)
44
45 union cvmx_gpio_bit_cfgx {
46 uint64_t u64;
47 struct cvmx_gpio_bit_cfgx_s {
48 #ifdef __BIG_ENDIAN_BITFIELD
49 uint64_t reserved_21_63:42;
50 uint64_t output_sel:5;
51 uint64_t synce_sel:2;
52 uint64_t clk_gen:1;
53 uint64_t clk_sel:2;
54 uint64_t fil_sel:4;
55 uint64_t fil_cnt:4;
56 uint64_t int_type:1;
57 uint64_t int_en:1;
58 uint64_t rx_xor:1;
59 uint64_t tx_oe:1;
60 #else
61 uint64_t tx_oe:1;
62 uint64_t rx_xor:1;
63 uint64_t int_en:1;
64 uint64_t int_type:1;
65 uint64_t fil_cnt:4;
66 uint64_t fil_sel:4;
67 uint64_t clk_sel:2;
68 uint64_t clk_gen:1;
69 uint64_t synce_sel:2;
70 uint64_t output_sel:5;
71 uint64_t reserved_21_63:42;
72 #endif
73 } s;
74 struct cvmx_gpio_bit_cfgx_cn30xx {
75 #ifdef __BIG_ENDIAN_BITFIELD
76 uint64_t reserved_12_63:52;
77 uint64_t fil_sel:4;
78 uint64_t fil_cnt:4;
79 uint64_t int_type:1;
80 uint64_t int_en:1;
81 uint64_t rx_xor:1;
82 uint64_t tx_oe:1;
83 #else
84 uint64_t tx_oe:1;
85 uint64_t rx_xor:1;
86 uint64_t int_en:1;
87 uint64_t int_type:1;
88 uint64_t fil_cnt:4;
89 uint64_t fil_sel:4;
90 uint64_t reserved_12_63:52;
91 #endif
92 } cn30xx;
93 struct cvmx_gpio_bit_cfgx_cn52xx {
94 #ifdef __BIG_ENDIAN_BITFIELD
95 uint64_t reserved_15_63:49;
96 uint64_t clk_gen:1;
97 uint64_t clk_sel:2;
98 uint64_t fil_sel:4;
99 uint64_t fil_cnt:4;
100 uint64_t int_type:1;
101 uint64_t int_en:1;
102 uint64_t rx_xor:1;
103 uint64_t tx_oe:1;
104 #else
105 uint64_t tx_oe:1;
106 uint64_t rx_xor:1;
107 uint64_t int_en:1;
108 uint64_t int_type:1;
109 uint64_t fil_cnt:4;
110 uint64_t fil_sel:4;
111 uint64_t clk_sel:2;
112 uint64_t clk_gen:1;
113 uint64_t reserved_15_63:49;
114 #endif
115 } cn52xx;
116 };
117
118 union cvmx_gpio_boot_ena {
119 uint64_t u64;
120 struct cvmx_gpio_boot_ena_s {
121 #ifdef __BIG_ENDIAN_BITFIELD
122 uint64_t reserved_12_63:52;
123 uint64_t boot_ena:4;
124 uint64_t reserved_0_7:8;
125 #else
126 uint64_t reserved_0_7:8;
127 uint64_t boot_ena:4;
128 uint64_t reserved_12_63:52;
129 #endif
130 } s;
131 };
132
133 union cvmx_gpio_clk_genx {
134 uint64_t u64;
135 struct cvmx_gpio_clk_genx_s {
136 #ifdef __BIG_ENDIAN_BITFIELD
137 uint64_t reserved_32_63:32;
138 uint64_t n:32;
139 #else
140 uint64_t n:32;
141 uint64_t reserved_32_63:32;
142 #endif
143 } s;
144 };
145
146 union cvmx_gpio_clk_qlmx {
147 uint64_t u64;
148 struct cvmx_gpio_clk_qlmx_s {
149 #ifdef __BIG_ENDIAN_BITFIELD
150 uint64_t reserved_11_63:53;
151 uint64_t qlm_sel:3;
152 uint64_t reserved_3_7:5;
153 uint64_t div:1;
154 uint64_t lane_sel:2;
155 #else
156 uint64_t lane_sel:2;
157 uint64_t div:1;
158 uint64_t reserved_3_7:5;
159 uint64_t qlm_sel:3;
160 uint64_t reserved_11_63:53;
161 #endif
162 } s;
163 struct cvmx_gpio_clk_qlmx_cn61xx {
164 #ifdef __BIG_ENDIAN_BITFIELD
165 uint64_t reserved_10_63:54;
166 uint64_t qlm_sel:2;
167 uint64_t reserved_3_7:5;
168 uint64_t div:1;
169 uint64_t lane_sel:2;
170 #else
171 uint64_t lane_sel:2;
172 uint64_t div:1;
173 uint64_t reserved_3_7:5;
174 uint64_t qlm_sel:2;
175 uint64_t reserved_10_63:54;
176 #endif
177 } cn61xx;
178 struct cvmx_gpio_clk_qlmx_cn63xx {
179 #ifdef __BIG_ENDIAN_BITFIELD
180 uint64_t reserved_3_63:61;
181 uint64_t div:1;
182 uint64_t lane_sel:2;
183 #else
184 uint64_t lane_sel:2;
185 uint64_t div:1;
186 uint64_t reserved_3_63:61;
187 #endif
188 } cn63xx;
189 };
190
191 union cvmx_gpio_dbg_ena {
192 uint64_t u64;
193 struct cvmx_gpio_dbg_ena_s {
194 #ifdef __BIG_ENDIAN_BITFIELD
195 uint64_t reserved_21_63:43;
196 uint64_t dbg_ena:21;
197 #else
198 uint64_t dbg_ena:21;
199 uint64_t reserved_21_63:43;
200 #endif
201 } s;
202 };
203
204 union cvmx_gpio_int_clr {
205 uint64_t u64;
206 struct cvmx_gpio_int_clr_s {
207 #ifdef __BIG_ENDIAN_BITFIELD
208 uint64_t reserved_16_63:48;
209 uint64_t type:16;
210 #else
211 uint64_t type:16;
212 uint64_t reserved_16_63:48;
213 #endif
214 } s;
215 };
216
217 union cvmx_gpio_multi_cast {
218 uint64_t u64;
219 struct cvmx_gpio_multi_cast_s {
220 #ifdef __BIG_ENDIAN_BITFIELD
221 uint64_t reserved_1_63:63;
222 uint64_t en:1;
223 #else
224 uint64_t en:1;
225 uint64_t reserved_1_63:63;
226 #endif
227 } s;
228 };
229
230 union cvmx_gpio_pin_ena {
231 uint64_t u64;
232 struct cvmx_gpio_pin_ena_s {
233 #ifdef __BIG_ENDIAN_BITFIELD
234 uint64_t reserved_20_63:44;
235 uint64_t ena19:1;
236 uint64_t ena18:1;
237 uint64_t reserved_0_17:18;
238 #else
239 uint64_t reserved_0_17:18;
240 uint64_t ena18:1;
241 uint64_t ena19:1;
242 uint64_t reserved_20_63:44;
243 #endif
244 } s;
245 };
246
247 union cvmx_gpio_rx_dat {
248 uint64_t u64;
249 struct cvmx_gpio_rx_dat_s {
250 #ifdef __BIG_ENDIAN_BITFIELD
251 uint64_t reserved_24_63:40;
252 uint64_t dat:24;
253 #else
254 uint64_t dat:24;
255 uint64_t reserved_24_63:40;
256 #endif
257 } s;
258 struct cvmx_gpio_rx_dat_cn38xx {
259 #ifdef __BIG_ENDIAN_BITFIELD
260 uint64_t reserved_16_63:48;
261 uint64_t dat:16;
262 #else
263 uint64_t dat:16;
264 uint64_t reserved_16_63:48;
265 #endif
266 } cn38xx;
267 struct cvmx_gpio_rx_dat_cn61xx {
268 #ifdef __BIG_ENDIAN_BITFIELD
269 uint64_t reserved_20_63:44;
270 uint64_t dat:20;
271 #else
272 uint64_t dat:20;
273 uint64_t reserved_20_63:44;
274 #endif
275 } cn61xx;
276 };
277
278 union cvmx_gpio_tim_ctl {
279 uint64_t u64;
280 struct cvmx_gpio_tim_ctl_s {
281 #ifdef __BIG_ENDIAN_BITFIELD
282 uint64_t reserved_4_63:60;
283 uint64_t sel:4;
284 #else
285 uint64_t sel:4;
286 uint64_t reserved_4_63:60;
287 #endif
288 } s;
289 };
290
291 union cvmx_gpio_tx_clr {
292 uint64_t u64;
293 struct cvmx_gpio_tx_clr_s {
294 #ifdef __BIG_ENDIAN_BITFIELD
295 uint64_t reserved_24_63:40;
296 uint64_t clr:24;
297 #else
298 uint64_t clr:24;
299 uint64_t reserved_24_63:40;
300 #endif
301 } s;
302 struct cvmx_gpio_tx_clr_cn38xx {
303 #ifdef __BIG_ENDIAN_BITFIELD
304 uint64_t reserved_16_63:48;
305 uint64_t clr:16;
306 #else
307 uint64_t clr:16;
308 uint64_t reserved_16_63:48;
309 #endif
310 } cn38xx;
311 struct cvmx_gpio_tx_clr_cn61xx {
312 #ifdef __BIG_ENDIAN_BITFIELD
313 uint64_t reserved_20_63:44;
314 uint64_t clr:20;
315 #else
316 uint64_t clr:20;
317 uint64_t reserved_20_63:44;
318 #endif
319 } cn61xx;
320 };
321
322 union cvmx_gpio_tx_set {
323 uint64_t u64;
324 struct cvmx_gpio_tx_set_s {
325 #ifdef __BIG_ENDIAN_BITFIELD
326 uint64_t reserved_24_63:40;
327 uint64_t set:24;
328 #else
329 uint64_t set:24;
330 uint64_t reserved_24_63:40;
331 #endif
332 } s;
333 struct cvmx_gpio_tx_set_cn38xx {
334 #ifdef __BIG_ENDIAN_BITFIELD
335 uint64_t reserved_16_63:48;
336 uint64_t set:16;
337 #else
338 uint64_t set:16;
339 uint64_t reserved_16_63:48;
340 #endif
341 } cn38xx;
342 struct cvmx_gpio_tx_set_cn61xx {
343 #ifdef __BIG_ENDIAN_BITFIELD
344 uint64_t reserved_20_63:44;
345 uint64_t set:20;
346 #else
347 uint64_t set:20;
348 uint64_t reserved_20_63:44;
349 #endif
350 } cn61xx;
351 };
352
353 union cvmx_gpio_xbit_cfgx {
354 uint64_t u64;
355 struct cvmx_gpio_xbit_cfgx_s {
356 #ifdef __BIG_ENDIAN_BITFIELD
357 uint64_t reserved_17_63:47;
358 uint64_t synce_sel:2;
359 uint64_t clk_gen:1;
360 uint64_t clk_sel:2;
361 uint64_t fil_sel:4;
362 uint64_t fil_cnt:4;
363 uint64_t int_type:1;
364 uint64_t int_en:1;
365 uint64_t rx_xor:1;
366 uint64_t tx_oe:1;
367 #else
368 uint64_t tx_oe:1;
369 uint64_t rx_xor:1;
370 uint64_t int_en:1;
371 uint64_t int_type:1;
372 uint64_t fil_cnt:4;
373 uint64_t fil_sel:4;
374 uint64_t clk_sel:2;
375 uint64_t clk_gen:1;
376 uint64_t synce_sel:2;
377 uint64_t reserved_17_63:47;
378 #endif
379 } s;
380 struct cvmx_gpio_xbit_cfgx_cn30xx {
381 #ifdef __BIG_ENDIAN_BITFIELD
382 uint64_t reserved_12_63:52;
383 uint64_t fil_sel:4;
384 uint64_t fil_cnt:4;
385 uint64_t reserved_2_3:2;
386 uint64_t rx_xor:1;
387 uint64_t tx_oe:1;
388 #else
389 uint64_t tx_oe:1;
390 uint64_t rx_xor:1;
391 uint64_t reserved_2_3:2;
392 uint64_t fil_cnt:4;
393 uint64_t fil_sel:4;
394 uint64_t reserved_12_63:52;
395 #endif
396 } cn30xx;
397 };
398
399 #endif
400
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