1 /***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2012 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28 #ifndef __CVMX_PESCX_DEFS_H__
29 #define __CVMX_PESCX_DEFS_H__
30
31 #define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull)
32 #define CVMX_PESCX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull)
33 #define CVMX_PESCX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull)
34 #define CVMX_PESCX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull)
35 #define CVMX_PESCX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull)
36 #define CVMX_PESCX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull)
37 #define CVMX_PESCX_CTL_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull)
38 #define CVMX_PESCX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull)
39 #define CVMX_PESCX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull)
40 #define CVMX_PESCX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull)
41 #define CVMX_PESCX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull)
42 #define CVMX_PESCX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull)
43 #define CVMX_PESCX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull)
44 #define CVMX_PESCX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
45 #define CVMX_PESCX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
46 #define CVMX_PESCX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull)
47
48 union cvmx_pescx_bist_status {
49 uint64_t u64;
50 struct cvmx_pescx_bist_status_s {
51 #ifdef __BIG_ENDIAN_BITFIELD
52 uint64_t reserved_13_63:51;
53 uint64_t rqdata5:1;
54 uint64_t ctlp_or:1;
55 uint64_t ntlp_or:1;
56 uint64_t ptlp_or:1;
57 uint64_t retry:1;
58 uint64_t rqdata0:1;
59 uint64_t rqdata1:1;
60 uint64_t rqdata2:1;
61 uint64_t rqdata3:1;
62 uint64_t rqdata4:1;
63 uint64_t rqhdr1:1;
64 uint64_t rqhdr0:1;
65 uint64_t sot:1;
66 #else
67 uint64_t sot:1;
68 uint64_t rqhdr0:1;
69 uint64_t rqhdr1:1;
70 uint64_t rqdata4:1;
71 uint64_t rqdata3:1;
72 uint64_t rqdata2:1;
73 uint64_t rqdata1:1;
74 uint64_t rqdata0:1;
75 uint64_t retry:1;
76 uint64_t ptlp_or:1;
77 uint64_t ntlp_or:1;
78 uint64_t ctlp_or:1;
79 uint64_t rqdata5:1;
80 uint64_t reserved_13_63:51;
81 #endif
82 } s;
83 struct cvmx_pescx_bist_status_cn52xxp1 {
84 #ifdef __BIG_ENDIAN_BITFIELD
85 uint64_t reserved_12_63:52;
86 uint64_t ctlp_or:1;
87 uint64_t ntlp_or:1;
88 uint64_t ptlp_or:1;
89 uint64_t retry:1;
90 uint64_t rqdata0:1;
91 uint64_t rqdata1:1;
92 uint64_t rqdata2:1;
93 uint64_t rqdata3:1;
94 uint64_t rqdata4:1;
95 uint64_t rqhdr1:1;
96 uint64_t rqhdr0:1;
97 uint64_t sot:1;
98 #else
99 uint64_t sot:1;
100 uint64_t rqhdr0:1;
101 uint64_t rqhdr1:1;
102 uint64_t rqdata4:1;
103 uint64_t rqdata3:1;
104 uint64_t rqdata2:1;
105 uint64_t rqdata1:1;
106 uint64_t rqdata0:1;
107 uint64_t retry:1;
108 uint64_t ptlp_or:1;
109 uint64_t ntlp_or:1;
110 uint64_t ctlp_or:1;
111 uint64_t reserved_12_63:52;
112 #endif
113 } cn52xxp1;
114 };
115
116 union cvmx_pescx_bist_status2 {
117 uint64_t u64;
118 struct cvmx_pescx_bist_status2_s {
119 #ifdef __BIG_ENDIAN_BITFIELD
120 uint64_t reserved_14_63:50;
121 uint64_t cto_p2e:1;
122 uint64_t e2p_cpl:1;
123 uint64_t e2p_n:1;
124 uint64_t e2p_p:1;
125 uint64_t e2p_rsl:1;
126 uint64_t dbg_p2e:1;
127 uint64_t peai_p2e:1;
128 uint64_t rsl_p2e:1;
129 uint64_t pef_tpf1:1;
130 uint64_t pef_tpf0:1;
131 uint64_t pef_tnf:1;
132 uint64_t pef_tcf1:1;
133 uint64_t pef_tc0:1;
134 uint64_t ppf:1;
135 #else
136 uint64_t ppf:1;
137 uint64_t pef_tc0:1;
138 uint64_t pef_tcf1:1;
139 uint64_t pef_tnf:1;
140 uint64_t pef_tpf0:1;
141 uint64_t pef_tpf1:1;
142 uint64_t rsl_p2e:1;
143 uint64_t peai_p2e:1;
144 uint64_t dbg_p2e:1;
145 uint64_t e2p_rsl:1;
146 uint64_t e2p_p:1;
147 uint64_t e2p_n:1;
148 uint64_t e2p_cpl:1;
149 uint64_t cto_p2e:1;
150 uint64_t reserved_14_63:50;
151 #endif
152 } s;
153 };
154
155 union cvmx_pescx_cfg_rd {
156 uint64_t u64;
157 struct cvmx_pescx_cfg_rd_s {
158 #ifdef __BIG_ENDIAN_BITFIELD
159 uint64_t data:32;
160 uint64_t addr:32;
161 #else
162 uint64_t addr:32;
163 uint64_t data:32;
164 #endif
165 } s;
166 };
167
168 union cvmx_pescx_cfg_wr {
169 uint64_t u64;
170 struct cvmx_pescx_cfg_wr_s {
171 #ifdef __BIG_ENDIAN_BITFIELD
172 uint64_t data:32;
173 uint64_t addr:32;
174 #else
175 uint64_t addr:32;
176 uint64_t data:32;
177 #endif
178 } s;
179 };
180
181 union cvmx_pescx_cpl_lut_valid {
182 uint64_t u64;
183 struct cvmx_pescx_cpl_lut_valid_s {
184 #ifdef __BIG_ENDIAN_BITFIELD
185 uint64_t reserved_32_63:32;
186 uint64_t tag:32;
187 #else
188 uint64_t tag:32;
189 uint64_t reserved_32_63:32;
190 #endif
191 } s;
192 };
193
194 union cvmx_pescx_ctl_status {
195 uint64_t u64;
196 struct cvmx_pescx_ctl_status_s {
197 #ifdef __BIG_ENDIAN_BITFIELD
198 uint64_t reserved_28_63:36;
199 uint64_t dnum:5;
200 uint64_t pbus:8;
201 uint64_t qlm_cfg:2;
202 uint64_t lane_swp:1;
203 uint64_t pm_xtoff:1;
204 uint64_t pm_xpme:1;
205 uint64_t ob_p_cmd:1;
206 uint64_t reserved_7_8:2;
207 uint64_t nf_ecrc:1;
208 uint64_t dly_one:1;
209 uint64_t lnk_enb:1;
210 uint64_t ro_ctlp:1;
211 uint64_t reserved_2_2:1;
212 uint64_t inv_ecrc:1;
213 uint64_t inv_lcrc:1;
214 #else
215 uint64_t inv_lcrc:1;
216 uint64_t inv_ecrc:1;
217 uint64_t reserved_2_2:1;
218 uint64_t ro_ctlp:1;
219 uint64_t lnk_enb:1;
220 uint64_t dly_one:1;
221 uint64_t nf_ecrc:1;
222 uint64_t reserved_7_8:2;
223 uint64_t ob_p_cmd:1;
224 uint64_t pm_xpme:1;
225 uint64_t pm_xtoff:1;
226 uint64_t lane_swp:1;
227 uint64_t qlm_cfg:2;
228 uint64_t pbus:8;
229 uint64_t dnum:5;
230 uint64_t reserved_28_63:36;
231 #endif
232 } s;
233 struct cvmx_pescx_ctl_status_cn56xx {
234 #ifdef __BIG_ENDIAN_BITFIELD
235 uint64_t reserved_28_63:36;
236 uint64_t dnum:5;
237 uint64_t pbus:8;
238 uint64_t qlm_cfg:2;
239 uint64_t reserved_12_12:1;
240 uint64_t pm_xtoff:1;
241 uint64_t pm_xpme:1;
242 uint64_t ob_p_cmd:1;
243 uint64_t reserved_7_8:2;
244 uint64_t nf_ecrc:1;
245 uint64_t dly_one:1;
246 uint64_t lnk_enb:1;
247 uint64_t ro_ctlp:1;
248 uint64_t reserved_2_2:1;
249 uint64_t inv_ecrc:1;
250 uint64_t inv_lcrc:1;
251 #else
252 uint64_t inv_lcrc:1;
253 uint64_t inv_ecrc:1;
254 uint64_t reserved_2_2:1;
255 uint64_t ro_ctlp:1;
256 uint64_t lnk_enb:1;
257 uint64_t dly_one:1;
258 uint64_t nf_ecrc:1;
259 uint64_t reserved_7_8:2;
260 uint64_t ob_p_cmd:1;
261 uint64_t pm_xpme:1;
262 uint64_t pm_xtoff:1;
263 uint64_t reserved_12_12:1;
264 uint64_t qlm_cfg:2;
265 uint64_t pbus:8;
266 uint64_t dnum:5;
267 uint64_t reserved_28_63:36;
268 #endif
269 } cn56xx;
270 };
271
272 union cvmx_pescx_ctl_status2 {
273 uint64_t u64;
274 struct cvmx_pescx_ctl_status2_s {
275 #ifdef __BIG_ENDIAN_BITFIELD
276 uint64_t reserved_2_63:62;
277 uint64_t pclk_run:1;
278 uint64_t pcierst:1;
279 #else
280 uint64_t pcierst:1;
281 uint64_t pclk_run:1;
282 uint64_t reserved_2_63:62;
283 #endif
284 } s;
285 struct cvmx_pescx_ctl_status2_cn52xxp1 {
286 #ifdef __BIG_ENDIAN_BITFIELD
287 uint64_t reserved_1_63:63;
288 uint64_t pcierst:1;
289 #else
290 uint64_t pcierst:1;
291 uint64_t reserved_1_63:63;
292 #endif
293 } cn52xxp1;
294 };
295
296 union cvmx_pescx_dbg_info {
297 uint64_t u64;
298 struct cvmx_pescx_dbg_info_s {
299 #ifdef __BIG_ENDIAN_BITFIELD
300 uint64_t reserved_31_63:33;
301 uint64_t ecrc_e:1;
302 uint64_t rawwpp:1;
303 uint64_t racpp:1;
304 uint64_t ramtlp:1;
305 uint64_t rarwdns:1;
306 uint64_t caar:1;
307 uint64_t racca:1;
308 uint64_t racur:1;
309 uint64_t rauc:1;
310 uint64_t rqo:1;
311 uint64_t fcuv:1;
312 uint64_t rpe:1;
313 uint64_t fcpvwt:1;
314 uint64_t dpeoosd:1;
315 uint64_t rtwdle:1;
316 uint64_t rdwdle:1;
317 uint64_t mre:1;
318 uint64_t rte:1;
319 uint64_t acto:1;
320 uint64_t rvdm:1;
321 uint64_t rumep:1;
322 uint64_t rptamrc:1;
323 uint64_t rpmerc:1;
324 uint64_t rfemrc:1;
325 uint64_t rnfemrc:1;
326 uint64_t rcemrc:1;
327 uint64_t rpoison:1;
328 uint64_t recrce:1;
329 uint64_t rtlplle:1;
330 uint64_t rtlpmal:1;
331 uint64_t spoison:1;
332 #else
333 uint64_t spoison:1;
334 uint64_t rtlpmal:1;
335 uint64_t rtlplle:1;
336 uint64_t recrce:1;
337 uint64_t rpoison:1;
338 uint64_t rcemrc:1;
339 uint64_t rnfemrc:1;
340 uint64_t rfemrc:1;
341 uint64_t rpmerc:1;
342 uint64_t rptamrc:1;
343 uint64_t rumep:1;
344 uint64_t rvdm:1;
345 uint64_t acto:1;
346 uint64_t rte:1;
347 uint64_t mre:1;
348 uint64_t rdwdle:1;
349 uint64_t rtwdle:1;
350 uint64_t dpeoosd:1;
351 uint64_t fcpvwt:1;
352 uint64_t rpe:1;
353 uint64_t fcuv:1;
354 uint64_t rqo:1;
355 uint64_t rauc:1;
356 uint64_t racur:1;
357 uint64_t racca:1;
358 uint64_t caar:1;
359 uint64_t rarwdns:1;
360 uint64_t ramtlp:1;
361 uint64_t racpp:1;
362 uint64_t rawwpp:1;
363 uint64_t ecrc_e:1;
364 uint64_t reserved_31_63:33;
365 #endif
366 } s;
367 };
368
369 union cvmx_pescx_dbg_info_en {
370 uint64_t u64;
371 struct cvmx_pescx_dbg_info_en_s {
372 #ifdef __BIG_ENDIAN_BITFIELD
373 uint64_t reserved_31_63:33;
374 uint64_t ecrc_e:1;
375 uint64_t rawwpp:1;
376 uint64_t racpp:1;
377 uint64_t ramtlp:1;
378 uint64_t rarwdns:1;
379 uint64_t caar:1;
380 uint64_t racca:1;
381 uint64_t racur:1;
382 uint64_t rauc:1;
383 uint64_t rqo:1;
384 uint64_t fcuv:1;
385 uint64_t rpe:1;
386 uint64_t fcpvwt:1;
387 uint64_t dpeoosd:1;
388 uint64_t rtwdle:1;
389 uint64_t rdwdle:1;
390 uint64_t mre:1;
391 uint64_t rte:1;
392 uint64_t acto:1;
393 uint64_t rvdm:1;
394 uint64_t rumep:1;
395 uint64_t rptamrc:1;
396 uint64_t rpmerc:1;
397 uint64_t rfemrc:1;
398 uint64_t rnfemrc:1;
399 uint64_t rcemrc:1;
400 uint64_t rpoison:1;
401 uint64_t recrce:1;
402 uint64_t rtlplle:1;
403 uint64_t rtlpmal:1;
404 uint64_t spoison:1;
405 #else
406 uint64_t spoison:1;
407 uint64_t rtlpmal:1;
408 uint64_t rtlplle:1;
409 uint64_t recrce:1;
410 uint64_t rpoison:1;
411 uint64_t rcemrc:1;
412 uint64_t rnfemrc:1;
413 uint64_t rfemrc:1;
414 uint64_t rpmerc:1;
415 uint64_t rptamrc:1;
416 uint64_t rumep:1;
417 uint64_t rvdm:1;
418 uint64_t acto:1;
419 uint64_t rte:1;
420 uint64_t mre:1;
421 uint64_t rdwdle:1;
422 uint64_t rtwdle:1;
423 uint64_t dpeoosd:1;
424 uint64_t fcpvwt:1;
425 uint64_t rpe:1;
426 uint64_t fcuv:1;
427 uint64_t rqo:1;
428 uint64_t rauc:1;
429 uint64_t racur:1;
430 uint64_t racca:1;
431 uint64_t caar:1;
432 uint64_t rarwdns:1;
433 uint64_t ramtlp:1;
434 uint64_t racpp:1;
435 uint64_t rawwpp:1;
436 uint64_t ecrc_e:1;
437 uint64_t reserved_31_63:33;
438 #endif
439 } s;
440 };
441
442 union cvmx_pescx_diag_status {
443 uint64_t u64;
444 struct cvmx_pescx_diag_status_s {
445 #ifdef __BIG_ENDIAN_BITFIELD
446 uint64_t reserved_4_63:60;
447 uint64_t pm_dst:1;
448 uint64_t pm_stat:1;
449 uint64_t pm_en:1;
450 uint64_t aux_en:1;
451 #else
452 uint64_t aux_en:1;
453 uint64_t pm_en:1;
454 uint64_t pm_stat:1;
455 uint64_t pm_dst:1;
456 uint64_t reserved_4_63:60;
457 #endif
458 } s;
459 };
460
461 union cvmx_pescx_p2n_bar0_start {
462 uint64_t u64;
463 struct cvmx_pescx_p2n_bar0_start_s {
464 #ifdef __BIG_ENDIAN_BITFIELD
465 uint64_t addr:50;
466 uint64_t reserved_0_13:14;
467 #else
468 uint64_t reserved_0_13:14;
469 uint64_t addr:50;
470 #endif
471 } s;
472 };
473
474 union cvmx_pescx_p2n_bar1_start {
475 uint64_t u64;
476 struct cvmx_pescx_p2n_bar1_start_s {
477 #ifdef __BIG_ENDIAN_BITFIELD
478 uint64_t addr:38;
479 uint64_t reserved_0_25:26;
480 #else
481 uint64_t reserved_0_25:26;
482 uint64_t addr:38;
483 #endif
484 } s;
485 };
486
487 union cvmx_pescx_p2n_bar2_start {
488 uint64_t u64;
489 struct cvmx_pescx_p2n_bar2_start_s {
490 #ifdef __BIG_ENDIAN_BITFIELD
491 uint64_t addr:25;
492 uint64_t reserved_0_38:39;
493 #else
494 uint64_t reserved_0_38:39;
495 uint64_t addr:25;
496 #endif
497 } s;
498 };
499
500 union cvmx_pescx_p2p_barx_end {
501 uint64_t u64;
502 struct cvmx_pescx_p2p_barx_end_s {
503 #ifdef __BIG_ENDIAN_BITFIELD
504 uint64_t addr:52;
505 uint64_t reserved_0_11:12;
506 #else
507 uint64_t reserved_0_11:12;
508 uint64_t addr:52;
509 #endif
510 } s;
511 };
512
513 union cvmx_pescx_p2p_barx_start {
514 uint64_t u64;
515 struct cvmx_pescx_p2p_barx_start_s {
516 #ifdef __BIG_ENDIAN_BITFIELD
517 uint64_t addr:52;
518 uint64_t reserved_0_11:12;
519 #else
520 uint64_t reserved_0_11:12;
521 uint64_t addr:52;
522 #endif
523 } s;
524 };
525
526 union cvmx_pescx_tlp_credits {
527 uint64_t u64;
528 struct cvmx_pescx_tlp_credits_s {
529 #ifdef __BIG_ENDIAN_BITFIELD
530 uint64_t reserved_0_63:64;
531 #else
532 uint64_t reserved_0_63:64;
533 #endif
534 } s;
535 struct cvmx_pescx_tlp_credits_cn52xx {
536 #ifdef __BIG_ENDIAN_BITFIELD
537 uint64_t reserved_56_63:8;
538 uint64_t peai_ppf:8;
539 uint64_t pesc_cpl:8;
540 uint64_t pesc_np:8;
541 uint64_t pesc_p:8;
542 uint64_t npei_cpl:8;
543 uint64_t npei_np:8;
544 uint64_t npei_p:8;
545 #else
546 uint64_t npei_p:8;
547 uint64_t npei_np:8;
548 uint64_t npei_cpl:8;
549 uint64_t pesc_p:8;
550 uint64_t pesc_np:8;
551 uint64_t pesc_cpl:8;
552 uint64_t peai_ppf:8;
553 uint64_t reserved_56_63:8;
554 #endif
555 } cn52xx;
556 struct cvmx_pescx_tlp_credits_cn52xxp1 {
557 #ifdef __BIG_ENDIAN_BITFIELD
558 uint64_t reserved_38_63:26;
559 uint64_t peai_ppf:8;
560 uint64_t pesc_cpl:5;
561 uint64_t pesc_np:5;
562 uint64_t pesc_p:5;
563 uint64_t npei_cpl:5;
564 uint64_t npei_np:5;
565 uint64_t npei_p:5;
566 #else
567 uint64_t npei_p:5;
568 uint64_t npei_np:5;
569 uint64_t npei_cpl:5;
570 uint64_t pesc_p:5;
571 uint64_t pesc_np:5;
572 uint64_t pesc_cpl:5;
573 uint64_t peai_ppf:8;
574 uint64_t reserved_38_63:26;
575 #endif
576 } cn52xxp1;
577 };
578
579 #endif
580
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