1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* ********************************************************************* 3 * SB1250 Board Support Package 4 * 5 * Interrupt Mapper definitions File: sb1250_int.h 6 * 7 * This module contains constants for manipulating the SB1250's 8 * interrupt mapper and definitions for the interrupt sources. 9 * 10 * SB1250 specification level: User's manual 1/02/02 11 * 12 ********************************************************************* 13 * 14 * Copyright 2000, 2001, 2002, 2003 15 * Broadcom Corporation. All rights reserved. 16 * 17 ********************************************************************* */ 18 19 20 #ifndef _SB1250_INT_H 21 #define _SB1250_INT_H 22 23 #include <asm/sibyte/sb1250_defs.h> 24 25 /* ********************************************************************* 26 * Interrupt Mapper Constants 27 ********************************************************************* */ 28 29 /* 30 * Interrupt sources (Table 4-8, UM 0.2) 31 * 32 * First, the interrupt numbers. 33 */ 34 35 #define K_INT_SOURCES 64 36 37 #define K_INT_WATCHDOG_TIMER_0 0 38 #define K_INT_WATCHDOG_TIMER_1 1 39 #define K_INT_TIMER_0 2 40 #define K_INT_TIMER_1 3 41 #define K_INT_TIMER_2 4 42 #define K_INT_TIMER_3 5 43 #define K_INT_SMB_0 6 44 #define K_INT_SMB_1 7 45 #define K_INT_UART_0 8 46 #define K_INT_UART_1 9 47 #define K_INT_SER_0 10 48 #define K_INT_SER_1 11 49 #define K_INT_PCMCIA 12 50 #define K_INT_ADDR_TRAP 13 51 #define K_INT_PERF_CNT 14 52 #define K_INT_TRACE_FREEZE 15 53 #define K_INT_BAD_ECC 16 54 #define K_INT_COR_ECC 17 55 #define K_INT_IO_BUS 18 56 #define K_INT_MAC_0 19 57 #define K_INT_MAC_1 20 58 #define K_INT_MAC_2 21 59 #define K_INT_DM_CH_0 22 60 #define K_INT_DM_CH_1 23 61 #define K_INT_DM_CH_2 24 62 #define K_INT_DM_CH_3 25 63 #define K_INT_MBOX_0 26 64 #define K_INT_MBOX_1 27 65 #define K_INT_MBOX_2 28 66 #define K_INT_MBOX_3 29 67 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 68 #define K_INT_CYCLE_CP0_INT 30 69 #define K_INT_CYCLE_CP1_INT 31 70 #endif /* 1250 PASS2 || 112x PASS1 */ 71 #define K_INT_GPIO_0 32 72 #define K_INT_GPIO_1 33 73 #define K_INT_GPIO_2 34 74 #define K_INT_GPIO_3 35 75 #define K_INT_GPIO_4 36 76 #define K_INT_GPIO_5 37 77 #define K_INT_GPIO_6 38 78 #define K_INT_GPIO_7 39 79 #define K_INT_GPIO_8 40 80 #define K_INT_GPIO_9 41 81 #define K_INT_GPIO_10 42 82 #define K_INT_GPIO_11 43 83 #define K_INT_GPIO_12 44 84 #define K_INT_GPIO_13 45 85 #define K_INT_GPIO_14 46 86 #define K_INT_GPIO_15 47 87 #define K_INT_LDT_FATAL 48 88 #define K_INT_LDT_NONFATAL 49 89 #define K_INT_LDT_SMI 50 90 #define K_INT_LDT_NMI 51 91 #define K_INT_LDT_INIT 52 92 #define K_INT_LDT_STARTUP 53 93 #define K_INT_LDT_EXT 54 94 #define K_INT_PCI_ERROR 55 95 #define K_INT_PCI_INTA 56 96 #define K_INT_PCI_INTB 57 97 #define K_INT_PCI_INTC 58 98 #define K_INT_PCI_INTD 59 99 #define K_INT_SPARE_2 60 100 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 101 #define K_INT_MAC_0_CH1 61 102 #define K_INT_MAC_1_CH1 62 103 #define K_INT_MAC_2_CH1 63 104 #endif /* 1250 PASS2 || 112x PASS1 */ 105 106 /* 107 * Mask values for each interrupt 108 */ 109 110 #define M_INT_WATCHDOG_TIMER_0 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0) 111 #define M_INT_WATCHDOG_TIMER_1 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1) 112 #define M_INT_TIMER_0 _SB_MAKEMASK1(K_INT_TIMER_0) 113 #define M_INT_TIMER_1 _SB_MAKEMASK1(K_INT_TIMER_1) 114 #define M_INT_TIMER_2 _SB_MAKEMASK1(K_INT_TIMER_2) 115 #define M_INT_TIMER_3 _SB_MAKEMASK1(K_INT_TIMER_3) 116 #define M_INT_SMB_0 _SB_MAKEMASK1(K_INT_SMB_0) 117 #define M_INT_SMB_1 _SB_MAKEMASK1(K_INT_SMB_1) 118 #define M_INT_UART_0 _SB_MAKEMASK1(K_INT_UART_0) 119 #define M_INT_UART_1 _SB_MAKEMASK1(K_INT_UART_1) 120 #define M_INT_SER_0 _SB_MAKEMASK1(K_INT_SER_0) 121 #define M_INT_SER_1 _SB_MAKEMASK1(K_INT_SER_1) 122 #define M_INT_PCMCIA _SB_MAKEMASK1(K_INT_PCMCIA) 123 #define M_INT_ADDR_TRAP _SB_MAKEMASK1(K_INT_ADDR_TRAP) 124 #define M_INT_PERF_CNT _SB_MAKEMASK1(K_INT_PERF_CNT) 125 #define M_INT_TRACE_FREEZE _SB_MAKEMASK1(K_INT_TRACE_FREEZE) 126 #define M_INT_BAD_ECC _SB_MAKEMASK1(K_INT_BAD_ECC) 127 #define M_INT_COR_ECC _SB_MAKEMASK1(K_INT_COR_ECC) 128 #define M_INT_IO_BUS _SB_MAKEMASK1(K_INT_IO_BUS) 129 #define M_INT_MAC_0 _SB_MAKEMASK1(K_INT_MAC_0) 130 #define M_INT_MAC_1 _SB_MAKEMASK1(K_INT_MAC_1) 131 #define M_INT_MAC_2 _SB_MAKEMASK1(K_INT_MAC_2) 132 #define M_INT_DM_CH_0 _SB_MAKEMASK1(K_INT_DM_CH_0) 133 #define M_INT_DM_CH_1 _SB_MAKEMASK1(K_INT_DM_CH_1) 134 #define M_INT_DM_CH_2 _SB_MAKEMASK1(K_INT_DM_CH_2) 135 #define M_INT_DM_CH_3 _SB_MAKEMASK1(K_INT_DM_CH_3) 136 #define M_INT_MBOX_0 _SB_MAKEMASK1(K_INT_MBOX_0) 137 #define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1) 138 #define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2) 139 #define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3) 140 #define M_INT_MBOX_ALL _SB_MAKEMASK(4, K_INT_MBOX_0) 141 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 142 #define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT) 143 #define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT) 144 #endif /* 1250 PASS2 || 112x PASS1 */ 145 #define M_INT_GPIO_0 _SB_MAKEMASK1(K_INT_GPIO_0) 146 #define M_INT_GPIO_1 _SB_MAKEMASK1(K_INT_GPIO_1) 147 #define M_INT_GPIO_2 _SB_MAKEMASK1(K_INT_GPIO_2) 148 #define M_INT_GPIO_3 _SB_MAKEMASK1(K_INT_GPIO_3) 149 #define M_INT_GPIO_4 _SB_MAKEMASK1(K_INT_GPIO_4) 150 #define M_INT_GPIO_5 _SB_MAKEMASK1(K_INT_GPIO_5) 151 #define M_INT_GPIO_6 _SB_MAKEMASK1(K_INT_GPIO_6) 152 #define M_INT_GPIO_7 _SB_MAKEMASK1(K_INT_GPIO_7) 153 #define M_INT_GPIO_8 _SB_MAKEMASK1(K_INT_GPIO_8) 154 #define M_INT_GPIO_9 _SB_MAKEMASK1(K_INT_GPIO_9) 155 #define M_INT_GPIO_10 _SB_MAKEMASK1(K_INT_GPIO_10) 156 #define M_INT_GPIO_11 _SB_MAKEMASK1(K_INT_GPIO_11) 157 #define M_INT_GPIO_12 _SB_MAKEMASK1(K_INT_GPIO_12) 158 #define M_INT_GPIO_13 _SB_MAKEMASK1(K_INT_GPIO_13) 159 #define M_INT_GPIO_14 _SB_MAKEMASK1(K_INT_GPIO_14) 160 #define M_INT_GPIO_15 _SB_MAKEMASK1(K_INT_GPIO_15) 161 #define M_INT_LDT_FATAL _SB_MAKEMASK1(K_INT_LDT_FATAL) 162 #define M_INT_LDT_NONFATAL _SB_MAKEMASK1(K_INT_LDT_NONFATAL) 163 #define M_INT_LDT_SMI _SB_MAKEMASK1(K_INT_LDT_SMI) 164 #define M_INT_LDT_NMI _SB_MAKEMASK1(K_INT_LDT_NMI) 165 #define M_INT_LDT_INIT _SB_MAKEMASK1(K_INT_LDT_INIT) 166 #define M_INT_LDT_STARTUP _SB_MAKEMASK1(K_INT_LDT_STARTUP) 167 #define M_INT_LDT_EXT _SB_MAKEMASK1(K_INT_LDT_EXT) 168 #define M_INT_PCI_ERROR _SB_MAKEMASK1(K_INT_PCI_ERROR) 169 #define M_INT_PCI_INTA _SB_MAKEMASK1(K_INT_PCI_INTA) 170 #define M_INT_PCI_INTB _SB_MAKEMASK1(K_INT_PCI_INTB) 171 #define M_INT_PCI_INTC _SB_MAKEMASK1(K_INT_PCI_INTC) 172 #define M_INT_PCI_INTD _SB_MAKEMASK1(K_INT_PCI_INTD) 173 #define M_INT_SPARE_2 _SB_MAKEMASK1(K_INT_SPARE_2) 174 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 175 #define M_INT_MAC_0_CH1 _SB_MAKEMASK1(K_INT_MAC_0_CH1) 176 #define M_INT_MAC_1_CH1 _SB_MAKEMASK1(K_INT_MAC_1_CH1) 177 #define M_INT_MAC_2_CH1 _SB_MAKEMASK1(K_INT_MAC_2_CH1) 178 #endif /* 1250 PASS2 || 112x PASS1 */ 179 180 /* 181 * Interrupt mappings 182 */ 183 184 #define K_INT_MAP_I0 0 /* interrupt pins on processor */ 185 #define K_INT_MAP_I1 1 186 #define K_INT_MAP_I2 2 187 #define K_INT_MAP_I3 3 188 #define K_INT_MAP_I4 4 189 #define K_INT_MAP_I5 5 190 #define K_INT_MAP_NMI 6 /* nonmaskable */ 191 #define K_INT_MAP_DINT 7 /* debug interrupt */ 192 193 /* 194 * LDT Interrupt Set Register (table 4-5) 195 */ 196 197 #define S_INT_LDT_INTMSG 0 198 #define M_INT_LDT_INTMSG _SB_MAKEMASK(3, S_INT_LDT_INTMSG) 199 #define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x, S_INT_LDT_INTMSG) 200 #define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x, S_INT_LDT_INTMSG, M_INT_LDT_INTMSG) 201 202 #define K_INT_LDT_INTMSG_FIXED 0 203 #define K_INT_LDT_INTMSG_ARBITRATED 1 204 #define K_INT_LDT_INTMSG_SMI 2 205 #define K_INT_LDT_INTMSG_NMI 3 206 #define K_INT_LDT_INTMSG_INIT 4 207 #define K_INT_LDT_INTMSG_STARTUP 5 208 #define K_INT_LDT_INTMSG_EXTINT 6 209 #define K_INT_LDT_INTMSG_RESERVED 7 210 211 #define M_INT_LDT_EDGETRIGGER 0 212 #define M_INT_LDT_LEVELTRIGGER _SB_MAKEMASK1(3) 213 214 #define M_INT_LDT_PHYSICALDEST 0 215 #define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4) 216 217 #define S_INT_LDT_INTDEST 5 218 #define M_INT_LDT_INTDEST _SB_MAKEMASK(10, S_INT_LDT_INTDEST) 219 #define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x, S_INT_LDT_INTDEST) 220 #define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x, S_INT_LDT_INTDEST, M_INT_LDT_INTDEST) 221 222 #define S_INT_LDT_VECTOR 13 223 #define M_INT_LDT_VECTOR _SB_MAKEMASK(8, S_INT_LDT_VECTOR) 224 #define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x, S_INT_LDT_VECTOR) 225 #define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x, S_INT_LDT_VECTOR, M_INT_LDT_VECTOR) 226 227 /* 228 * Vector format (Table 4-6) 229 */ 230 231 #define M_LDTVECT_RAISEINT 0x00 232 #define M_LDTVECT_RAISEMBOX 0x40 233 234 235 #endif /* 1250/112x */ 236
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