1 /*
2 * Author: MontaVista Software, Inc.
3 * source@mvista.com
4 *
5 * Copyright 2001-2006 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
15 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
17 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
18 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
19 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
20 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
21 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27 #ifndef __ASM_TXX9_TX4927_H
28 #define __ASM_TXX9_TX4927_H
29
30 #include <linux/types.h>
31 #include <linux/io.h>
32 #include <asm/txx9irq.h>
33 #include <asm/txx9/tx4927pcic.h>
34
35 #ifdef CONFIG_64BIT
36 #define TX4927_REG_BASE 0xffffffffff1f0000UL
37 #else
38 #define TX4927_REG_BASE 0xff1f0000UL
39 #endif
40 #define TX4927_REG_SIZE 0x00010000
41
42 #define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000)
43 #define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000)
44 #define TX4927_DMA_REG (TX4927_REG_BASE + 0xb000)
45 #define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000)
46 #define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000)
47 #define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600)
48 #define TX4927_NR_TMR 3
49 #define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100)
50 #define TX4927_NR_SIO 2
51 #define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100)
52 #define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500)
53 #define TX4927_ACLC_REG (TX4927_REG_BASE + 0xf700)
54
55 #define TX4927_IR_ECCERR 0
56 #define TX4927_IR_WTOERR 1
57 #define TX4927_NUM_IR_INT 6
58 #define TX4927_IR_INT(n) (2 + (n))
59 #define TX4927_NUM_IR_SIO 2
60 #define TX4927_IR_SIO(n) (8 + (n))
61 #define TX4927_NUM_IR_DMA 4
62 #define TX4927_IR_DMA(n) (10 + (n))
63 #define TX4927_IR_PIO 14
64 #define TX4927_IR_PDMAC 15
65 #define TX4927_IR_PCIC 16
66 #define TX4927_NUM_IR_TMR 3
67 #define TX4927_IR_TMR(n) (17 + (n))
68 #define TX4927_IR_PCIERR 22
69 #define TX4927_IR_PCIPME 23
70 #define TX4927_IR_ACLC 24
71 #define TX4927_IR_ACLCPME 25
72 #define TX4927_NUM_IR 32
73
74 #define TX4927_IRC_INT 2 /* IP[2] in Status register */
75
76 #define TX4927_NUM_PIO 16
77
78 struct tx4927_sdramc_reg {
79 u64 cr[4];
80 u64 unused0[4];
81 u64 tr;
82 u64 unused1[2];
83 u64 cmd;
84 };
85
86 struct tx4927_ebusc_reg {
87 u64 cr[8];
88 };
89
90 struct tx4927_ccfg_reg {
91 u64 ccfg;
92 u64 crir;
93 u64 pcfg;
94 u64 toea;
95 u64 clkctr;
96 u64 unused0;
97 u64 garbc;
98 u64 unused1;
99 u64 unused2;
100 u64 ramp;
101 };
102
103 /*
104 * CCFG
105 */
106 /* CCFG : Chip Configuration */
107 #define TX4927_CCFG_WDRST 0x0000020000000000ULL
108 #define TX4927_CCFG_WDREXEN 0x0000010000000000ULL
109 #define TX4927_CCFG_BCFG_MASK 0x000000ff00000000ULL
110 #define TX4927_CCFG_TINTDIS 0x01000000
111 #define TX4927_CCFG_PCI66 0x00800000
112 #define TX4927_CCFG_PCIMODE 0x00400000
113 #define TX4927_CCFG_DIVMODE_MASK 0x000e0000
114 #define TX4927_CCFG_DIVMODE_8 (0x0 << 17)
115 #define TX4927_CCFG_DIVMODE_12 (0x1 << 17)
116 #define TX4927_CCFG_DIVMODE_16 (0x2 << 17)
117 #define TX4927_CCFG_DIVMODE_10 (0x3 << 17)
118 #define TX4927_CCFG_DIVMODE_2 (0x4 << 17)
119 #define TX4927_CCFG_DIVMODE_3 (0x5 << 17)
120 #define TX4927_CCFG_DIVMODE_4 (0x6 << 17)
121 #define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
122 #define TX4927_CCFG_BEOW 0x00010000
123 #define TX4927_CCFG_WR 0x00008000
124 #define TX4927_CCFG_TOE 0x00004000
125 #define TX4927_CCFG_PCIARB 0x00002000
126 #define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
127 #define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
128 #define TX4927_CCFG_PCIDIVMODE_3 0x00000800
129 #define TX4927_CCFG_PCIDIVMODE_5 0x00001000
130 #define TX4927_CCFG_PCIDIVMODE_6 0x00001800
131 #define TX4927_CCFG_SYSSP_MASK 0x000000c0
132 #define TX4927_CCFG_ENDIAN 0x00000004
133 #define TX4927_CCFG_HALT 0x00000002
134 #define TX4927_CCFG_ACEHOLD 0x00000001
135 #define TX4927_CCFG_W1CBITS (TX4927_CCFG_WDRST | TX4927_CCFG_BEOW)
136
137 /* PCFG : Pin Configuration */
138 #define TX4927_PCFG_SDCLKDLY_MASK 0x30000000
139 #define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)
140 #define TX4927_PCFG_SYSCLKEN 0x08000000
141 #define TX4927_PCFG_SDCLKEN_ALL 0x07800000
142 #define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
143 #define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
144 #define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
145 #define TX4927_PCFG_SEL2 0x00000200
146 #define TX4927_PCFG_SEL1 0x00000100
147 #define TX4927_PCFG_DMASEL_ALL 0x000000ff
148 #define TX4927_PCFG_DMASEL0_MASK 0x00000003
149 #define TX4927_PCFG_DMASEL1_MASK 0x0000000c
150 #define TX4927_PCFG_DMASEL2_MASK 0x00000030
151 #define TX4927_PCFG_DMASEL3_MASK 0x000000c0
152 #define TX4927_PCFG_DMASEL0_DRQ0 0x00000000
153 #define TX4927_PCFG_DMASEL0_SIO1 0x00000001
154 #define TX4927_PCFG_DMASEL0_ACL0 0x00000002
155 #define TX4927_PCFG_DMASEL0_ACL2 0x00000003
156 #define TX4927_PCFG_DMASEL1_DRQ1 0x00000000
157 #define TX4927_PCFG_DMASEL1_SIO1 0x00000004
158 #define TX4927_PCFG_DMASEL1_ACL1 0x00000008
159 #define TX4927_PCFG_DMASEL1_ACL3 0x0000000c
160 #define TX4927_PCFG_DMASEL2_DRQ2 0x00000000 /* SEL2=0 */
161 #define TX4927_PCFG_DMASEL2_SIO0 0x00000010 /* SEL2=0 */
162 #define TX4927_PCFG_DMASEL2_ACL1 0x00000000 /* SEL2=1 */
163 #define TX4927_PCFG_DMASEL2_ACL2 0x00000020 /* SEL2=1 */
164 #define TX4927_PCFG_DMASEL2_ACL0 0x00000030 /* SEL2=1 */
165 #define TX4927_PCFG_DMASEL3_DRQ3 0x00000000
166 #define TX4927_PCFG_DMASEL3_SIO0 0x00000040
167 #define TX4927_PCFG_DMASEL3_ACL3 0x00000080
168 #define TX4927_PCFG_DMASEL3_ACL1 0x000000c0
169
170 /* CLKCTR : Clock Control */
171 #define TX4927_CLKCTR_ACLCKD 0x02000000
172 #define TX4927_CLKCTR_PIOCKD 0x01000000
173 #define TX4927_CLKCTR_DMACKD 0x00800000
174 #define TX4927_CLKCTR_PCICKD 0x00400000
175 #define TX4927_CLKCTR_TM0CKD 0x00100000
176 #define TX4927_CLKCTR_TM1CKD 0x00080000
177 #define TX4927_CLKCTR_TM2CKD 0x00040000
178 #define TX4927_CLKCTR_SIO0CKD 0x00020000
179 #define TX4927_CLKCTR_SIO1CKD 0x00010000
180 #define TX4927_CLKCTR_ACLRST 0x00000200
181 #define TX4927_CLKCTR_PIORST 0x00000100
182 #define TX4927_CLKCTR_DMARST 0x00000080
183 #define TX4927_CLKCTR_PCIRST 0x00000040
184 #define TX4927_CLKCTR_TM0RST 0x00000010
185 #define TX4927_CLKCTR_TM1RST 0x00000008
186 #define TX4927_CLKCTR_TM2RST 0x00000004
187 #define TX4927_CLKCTR_SIO0RST 0x00000002
188 #define TX4927_CLKCTR_SIO1RST 0x00000001
189
190 #define tx4927_sdramcptr \
191 ((struct tx4927_sdramc_reg __iomem *)TX4927_SDRAMC_REG)
192 #define tx4927_pcicptr \
193 ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG)
194 #define tx4927_ccfgptr \
195 ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
196 #define tx4927_ebuscptr \
197 ((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG)
198 #define tx4927_pioptr ((struct txx9_pio_reg __iomem *)TX4927_PIO_REG)
199
200 #define TX4927_REV_PCODE() \
201 ((__u32)__raw_readq(&tx4927_ccfgptr->crir) >> 16)
202
203 #define TX4927_SDRAMC_CR(ch) __raw_readq(&tx4927_sdramcptr->cr[(ch)])
204 #define TX4927_SDRAMC_BA(ch) ((TX4927_SDRAMC_CR(ch) >> 49) << 21)
205 #define TX4927_SDRAMC_SIZE(ch) \
206 ((((TX4927_SDRAMC_CR(ch) >> 33) & 0x7fff) + 1) << 21)
207
208 #define TX4927_EBUSC_CR(ch) __raw_readq(&tx4927_ebuscptr->cr[(ch)])
209 #define TX4927_EBUSC_BA(ch) ((TX4927_EBUSC_CR(ch) >> 48) << 20)
210 #define TX4927_EBUSC_SIZE(ch) \
211 (0x00100000 << ((unsigned long)(TX4927_EBUSC_CR(ch) >> 8) & 0xf))
212 #define TX4927_EBUSC_WIDTH(ch) \
213 (64 >> ((__u32)(TX4927_EBUSC_CR(ch) >> 20) & 0x3))
214
215 /* utilities */
216 static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
217 {
218 #ifdef CONFIG_32BIT
219 unsigned long flags;
220 local_irq_save(flags);
221 #endif
222 ____raw_writeq(____raw_readq(adr) & ~bits, adr);
223 #ifdef CONFIG_32BIT
224 local_irq_restore(flags);
225 #endif
226 }
227 static inline void txx9_set64(__u64 __iomem *adr, __u64 bits)
228 {
229 #ifdef CONFIG_32BIT
230 unsigned long flags;
231 local_irq_save(flags);
232 #endif
233 ____raw_writeq(____raw_readq(adr) | bits, adr);
234 #ifdef CONFIG_32BIT
235 local_irq_restore(flags);
236 #endif
237 }
238
239 /* These functions are not interrupt safe. */
240 static inline void tx4927_ccfg_clear(__u64 bits)
241 {
242 ____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg)
243 & ~(TX4927_CCFG_W1CBITS | bits),
244 &tx4927_ccfgptr->ccfg);
245 }
246 static inline void tx4927_ccfg_set(__u64 bits)
247 {
248 ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
249 & ~TX4927_CCFG_W1CBITS) | bits,
250 &tx4927_ccfgptr->ccfg);
251 }
252 static inline void tx4927_ccfg_change(__u64 change, __u64 new)
253 {
254 ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
255 & ~(TX4927_CCFG_W1CBITS | change)) |
256 new,
257 &tx4927_ccfgptr->ccfg);
258 }
259
260 unsigned int tx4927_get_mem_size(void);
261 void tx4927_wdt_init(void);
262 void tx4927_setup(void);
263 void tx4927_time_init(unsigned int tmrnr);
264 void tx4927_sio_init(unsigned int sclk, unsigned int cts_mask);
265 int tx4927_report_pciclk(void);
266 int tx4927_pciclk66_setup(void);
267 void tx4927_setup_pcierr_irq(void);
268 void tx4927_irq_init(void);
269 void tx4927_mtd_init(int ch);
270 void tx4927_dmac_init(int memcpy_chan);
271 void tx4927_aclc_init(unsigned int dma_chan_out, unsigned int dma_chan_in);
272
273 #endif /* __ASM_TXX9_TX4927_H */
274
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