1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * Copyright (C) 2011-2012 John Crispin <john@phrozen.org>
5 * Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
6 */
7
8 #include <linux/ioport.h>
9 #include <linux/export.h>
10 #include <linux/clkdev.h>
11 #include <linux/spinlock.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14
15 #include <lantiq_soc.h>
16
17 #include "../clk.h"
18 #include "../prom.h"
19
20 /* clock control register for legacy */
21 #define CGU_IFCCR 0x0018
22 #define CGU_IFCCR_VR9 0x0024
23 /* system clock register for legacy */
24 #define CGU_SYS 0x0010
25 /* pci control register */
26 #define CGU_PCICR 0x0034
27 #define CGU_PCICR_VR9 0x0038
28 /* ephy configuration register */
29 #define CGU_EPHY 0x10
30
31 /* Legacy PMU register for ar9, ase, danube */
32 /* power control register */
33 #define PMU_PWDCR 0x1C
34 /* power status register */
35 #define PMU_PWDSR 0x20
36 /* power control register */
37 #define PMU_PWDCR1 0x24
38 /* power status register */
39 #define PMU_PWDSR1 0x28
40 /* power control register */
41 #define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR))
42 /* power status register */
43 #define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR))
44
45
46 /* PMU register for ar10 and grx390 */
47
48 /* First register set */
49 #define PMU_CLK_SR 0x20 /* status */
50 #define PMU_CLK_CR_A 0x24 /* Enable */
51 #define PMU_CLK_CR_B 0x28 /* Disable */
52 /* Second register set */
53 #define PMU_CLK_SR1 0x30 /* status */
54 #define PMU_CLK_CR1_A 0x34 /* Enable */
55 #define PMU_CLK_CR1_B 0x38 /* Disable */
56 /* Third register set */
57 #define PMU_ANA_SR 0x40 /* status */
58 #define PMU_ANA_CR_A 0x44 /* Enable */
59 #define PMU_ANA_CR_B 0x48 /* Disable */
60
61 /* Status */
62 static u32 pmu_clk_sr[] = {
63 PMU_CLK_SR,
64 PMU_CLK_SR1,
65 PMU_ANA_SR,
66 };
67
68 /* Enable */
69 static u32 pmu_clk_cr_a[] = {
70 PMU_CLK_CR_A,
71 PMU_CLK_CR1_A,
72 PMU_ANA_CR_A,
73 };
74
75 /* Disable */
76 static u32 pmu_clk_cr_b[] = {
77 PMU_CLK_CR_B,
78 PMU_CLK_CR1_B,
79 PMU_ANA_CR_B,
80 };
81
82 #define PWDCR_EN_XRX(x) (pmu_clk_cr_a[(x)])
83 #define PWDCR_DIS_XRX(x) (pmu_clk_cr_b[(x)])
84 #define PWDSR_XRX(x) (pmu_clk_sr[(x)])
85
86 /* clock gates that we can en/disable */
87 #define PMU_USB0_P BIT(0)
88 #define PMU_ASE_SDIO BIT(2) /* ASE special */
89 #define PMU_PCI BIT(4)
90 #define PMU_DMA BIT(5)
91 #define PMU_USB0 BIT(6)
92 #define PMU_ASC0 BIT(7)
93 #define PMU_EPHY BIT(7) /* ase */
94 #define PMU_USIF BIT(7) /* from vr9 until grx390 */
95 #define PMU_SPI BIT(8)
96 #define PMU_DFE BIT(9)
97 #define PMU_EBU BIT(10)
98 #define PMU_STP BIT(11)
99 #define PMU_GPT BIT(12)
100 #define PMU_AHBS BIT(13) /* vr9 */
101 #define PMU_FPI BIT(14)
102 #define PMU_AHBM BIT(15)
103 #define PMU_SDIO BIT(16) /* danube, ar9, vr9 */
104 #define PMU_ASC1 BIT(17)
105 #define PMU_PPE_QSB BIT(18)
106 #define PMU_PPE_SLL01 BIT(19)
107 #define PMU_DEU BIT(20)
108 #define PMU_PPE_TC BIT(21)
109 #define PMU_PPE_EMA BIT(22)
110 #define PMU_PPE_DPLUM BIT(23)
111 #define PMU_PPE_DP BIT(23)
112 #define PMU_PPE_DPLUS BIT(24)
113 #define PMU_USB1_P BIT(26)
114 #define PMU_GPHY3 BIT(26) /* grx390 */
115 #define PMU_USB1 BIT(27)
116 #define PMU_SWITCH BIT(28)
117 #define PMU_PPE_TOP BIT(29)
118 #define PMU_GPHY0 BIT(29) /* ar10, xrx390 */
119 #define PMU_GPHY BIT(30)
120 #define PMU_GPHY1 BIT(30) /* ar10, xrx390 */
121 #define PMU_PCIE_CLK BIT(31)
122 #define PMU_GPHY2 BIT(31) /* ar10, xrx390 */
123
124 #define PMU1_PCIE_PHY BIT(0) /* vr9-specific,moved in ar10/grx390 */
125 #define PMU1_PCIE_CTL BIT(1)
126 #define PMU1_PCIE_PDI BIT(4)
127 #define PMU1_PCIE_MSI BIT(5)
128 #define PMU1_CKE BIT(6)
129 #define PMU1_PCIE1_CTL BIT(17)
130 #define PMU1_PCIE1_PDI BIT(20)
131 #define PMU1_PCIE1_MSI BIT(21)
132 #define PMU1_PCIE2_CTL BIT(25)
133 #define PMU1_PCIE2_PDI BIT(26)
134 #define PMU1_PCIE2_MSI BIT(27)
135
136 #define PMU_ANALOG_USB0_P BIT(0)
137 #define PMU_ANALOG_USB1_P BIT(1)
138 #define PMU_ANALOG_PCIE0_P BIT(8)
139 #define PMU_ANALOG_PCIE1_P BIT(9)
140 #define PMU_ANALOG_PCIE2_P BIT(10)
141 #define PMU_ANALOG_DSL_AFE BIT(16)
142 #define PMU_ANALOG_DCDC_2V5 BIT(17)
143 #define PMU_ANALOG_DCDC_1VX BIT(18)
144 #define PMU_ANALOG_DCDC_1V0 BIT(19)
145
146 #define pmu_w32(x, y) ltq_w32((x), pmu_membase + (y))
147 #define pmu_r32(x) ltq_r32(pmu_membase + (x))
148
149 static void __iomem *pmu_membase;
150 void __iomem *ltq_cgu_membase;
151 void __iomem *ltq_ebu_membase;
152
153 static u32 ifccr = CGU_IFCCR;
154 static u32 pcicr = CGU_PCICR;
155
156 static DEFINE_SPINLOCK(g_pmu_lock);
157
158 /* legacy function kept alive to ease clkdev transition */
159 void ltq_pmu_enable(unsigned int module)
160 {
161 int retry = 1000000;
162
163 spin_lock(&g_pmu_lock);
164 pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR);
165 do {} while (--retry && (pmu_r32(PMU_PWDSR) & module));
166 spin_unlock(&g_pmu_lock);
167
168 if (!retry)
169 panic("activating PMU module failed!");
170 }
171 EXPORT_SYMBOL(ltq_pmu_enable);
172
173 /* legacy function kept alive to ease clkdev transition */
174 void ltq_pmu_disable(unsigned int module)
175 {
176 int retry = 1000000;
177
178 spin_lock(&g_pmu_lock);
179 pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR);
180 do {} while (--retry && (!(pmu_r32(PMU_PWDSR) & module)));
181 spin_unlock(&g_pmu_lock);
182
183 if (!retry)
184 pr_warn("deactivating PMU module failed!");
185 }
186 EXPORT_SYMBOL(ltq_pmu_disable);
187
188 /* enable a hw clock */
189 static int cgu_enable(struct clk *clk)
190 {
191 ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr);
192 return 0;
193 }
194
195 /* disable a hw clock */
196 static void cgu_disable(struct clk *clk)
197 {
198 ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr);
199 }
200
201 /* enable a clock gate */
202 static int pmu_enable(struct clk *clk)
203 {
204 int retry = 1000000;
205
206 if (of_machine_is_compatible("lantiq,ar10")
207 || of_machine_is_compatible("lantiq,grx390")) {
208 pmu_w32(clk->bits, PWDCR_EN_XRX(clk->module));
209 do {} while (--retry &&
210 (!(pmu_r32(PWDSR_XRX(clk->module)) & clk->bits)));
211
212 } else {
213 spin_lock(&g_pmu_lock);
214 pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits,
215 PWDCR(clk->module));
216 do {} while (--retry &&
217 (pmu_r32(PWDSR(clk->module)) & clk->bits));
218 spin_unlock(&g_pmu_lock);
219 }
220
221 if (!retry)
222 panic("activating PMU module failed!");
223
224 return 0;
225 }
226
227 /* disable a clock gate */
228 static void pmu_disable(struct clk *clk)
229 {
230 int retry = 1000000;
231
232 if (of_machine_is_compatible("lantiq,ar10")
233 || of_machine_is_compatible("lantiq,grx390")) {
234 pmu_w32(clk->bits, PWDCR_DIS_XRX(clk->module));
235 do {} while (--retry &&
236 (pmu_r32(PWDSR_XRX(clk->module)) & clk->bits));
237 } else {
238 spin_lock(&g_pmu_lock);
239 pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits,
240 PWDCR(clk->module));
241 do {} while (--retry &&
242 (!(pmu_r32(PWDSR(clk->module)) & clk->bits)));
243 spin_unlock(&g_pmu_lock);
244 }
245
246 if (!retry)
247 pr_warn("deactivating PMU module failed!");
248 }
249
250 static void usb_set_clock(void)
251 {
252 unsigned int val = ltq_cgu_r32(ifccr);
253
254 if (of_machine_is_compatible("lantiq,ar10") ||
255 of_machine_is_compatible("lantiq,grx390")) {
256 val &= ~0x03; /* XTAL divided by 3 */
257 } else if (of_machine_is_compatible("lantiq,ar9") ||
258 of_machine_is_compatible("lantiq,vr9")) {
259 /* TODO: this depends on the XTAL frequency */
260 val |= 0x03; /* XTAL divided by 3 */
261 } else if (of_machine_is_compatible("lantiq,ase")) {
262 val |= 0x20; /* from XTAL */
263 } else if (of_machine_is_compatible("lantiq,danube")) {
264 val |= 0x30; /* 12 MHz, generated from 36 MHz */
265 }
266 ltq_cgu_w32(val, ifccr);
267 }
268
269 /* the pci enable helper */
270 static int pci_enable(struct clk *clk)
271 {
272 unsigned int val = ltq_cgu_r32(ifccr);
273 /* set bus clock speed */
274 if (of_machine_is_compatible("lantiq,ar9") ||
275 of_machine_is_compatible("lantiq,vr9")) {
276 val &= ~0x1f00000;
277 if (clk->rate == CLOCK_33M)
278 val |= 0xe00000;
279 else
280 val |= 0x700000; /* 62.5M */
281 } else {
282 val &= ~0xf00000;
283 if (clk->rate == CLOCK_33M)
284 val |= 0x800000;
285 else
286 val |= 0x400000; /* 62.5M */
287 }
288 ltq_cgu_w32(val, ifccr);
289 pmu_enable(clk);
290 return 0;
291 }
292
293 /* enable the external clock as a source */
294 static int pci_ext_enable(struct clk *clk)
295 {
296 ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr);
297 ltq_cgu_w32((1 << 30), pcicr);
298 return 0;
299 }
300
301 /* disable the external clock as a source */
302 static void pci_ext_disable(struct clk *clk)
303 {
304 ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr);
305 ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
306 }
307
308 /* enable a clockout source */
309 static int clkout_enable(struct clk *clk)
310 {
311 int i;
312
313 /* get the correct rate */
314 for (i = 0; i < 4; i++) {
315 if (clk->rates[i] == clk->rate) {
316 int shift = 14 - (2 * clk->module);
317 int enable = 7 - clk->module;
318 unsigned int val = ltq_cgu_r32(ifccr);
319
320 val &= ~(3 << shift);
321 val |= i << shift;
322 val |= enable;
323 ltq_cgu_w32(val, ifccr);
324 return 0;
325 }
326 }
327 return -1;
328 }
329
330 /* manage the clock gates via PMU */
331 static void clkdev_add_pmu(const char *dev, const char *con, bool deactivate,
332 unsigned int module, unsigned int bits)
333 {
334 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
335
336 if (!clk)
337 return;
338 clk->cl.dev_id = dev;
339 clk->cl.con_id = con;
340 clk->cl.clk = clk;
341 clk->enable = pmu_enable;
342 clk->disable = pmu_disable;
343 clk->module = module;
344 clk->bits = bits;
345 if (deactivate) {
346 /*
347 * Disable it during the initialization. Module should enable
348 * when used
349 */
350 pmu_disable(clk);
351 }
352 clkdev_add(&clk->cl);
353 }
354
355 /* manage the clock generator */
356 static void clkdev_add_cgu(const char *dev, const char *con,
357 unsigned int bits)
358 {
359 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
360
361 if (!clk)
362 return;
363 clk->cl.dev_id = dev;
364 clk->cl.con_id = con;
365 clk->cl.clk = clk;
366 clk->enable = cgu_enable;
367 clk->disable = cgu_disable;
368 clk->bits = bits;
369 clkdev_add(&clk->cl);
370 }
371
372 /* pci needs its own enable function as the setup is a bit more complex */
373 static unsigned long valid_pci_rates[] = {CLOCK_33M, CLOCK_62_5M, 0};
374
375 static void clkdev_add_pci(void)
376 {
377 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
378 struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL);
379
380 /* main pci clock */
381 if (clk) {
382 clk->cl.dev_id = "17000000.pci";
383 clk->cl.con_id = NULL;
384 clk->cl.clk = clk;
385 clk->rate = CLOCK_33M;
386 clk->rates = valid_pci_rates;
387 clk->enable = pci_enable;
388 clk->disable = pmu_disable;
389 clk->module = 0;
390 clk->bits = PMU_PCI;
391 clkdev_add(&clk->cl);
392 }
393
394 /* use internal/external bus clock */
395 if (clk_ext) {
396 clk_ext->cl.dev_id = "17000000.pci";
397 clk_ext->cl.con_id = "external";
398 clk_ext->cl.clk = clk_ext;
399 clk_ext->enable = pci_ext_enable;
400 clk_ext->disable = pci_ext_disable;
401 clkdev_add(&clk_ext->cl);
402 }
403 }
404
405 /* xway socs can generate clocks on gpio pins */
406 static unsigned long valid_clkout_rates[4][5] = {
407 {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0},
408 {CLOCK_40M, CLOCK_12M, CLOCK_24M, CLOCK_48M, 0},
409 {CLOCK_25M, CLOCK_40M, CLOCK_30M, CLOCK_60M, 0},
410 {CLOCK_12M, CLOCK_50M, CLOCK_32_768K, CLOCK_25M, 0},
411 };
412
413 static void clkdev_add_clkout(void)
414 {
415 int i;
416
417 for (i = 0; i < 4; i++) {
418 struct clk *clk;
419 char *name;
420
421 name = kzalloc(sizeof("clkout0"), GFP_KERNEL);
422 if (!name)
423 continue;
424 sprintf(name, "clkout%d", i);
425
426 clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
427 if (!clk) {
428 kfree(name);
429 continue;
430 }
431 clk->cl.dev_id = "1f103000.cgu";
432 clk->cl.con_id = name;
433 clk->cl.clk = clk;
434 clk->rate = 0;
435 clk->rates = valid_clkout_rates[i];
436 clk->enable = clkout_enable;
437 clk->module = i;
438 clkdev_add(&clk->cl);
439 }
440 }
441
442 /* bring up all register ranges that we need for basic system control */
443 void __init ltq_soc_init(void)
444 {
445 struct resource res_pmu, res_cgu, res_ebu;
446 struct device_node *np_pmu =
447 of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway");
448 struct device_node *np_cgu =
449 of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway");
450 struct device_node *np_ebu =
451 of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway");
452
453 /* check if all the core register ranges are available */
454 if (!np_pmu || !np_cgu || !np_ebu)
455 panic("Failed to load core nodes from devicetree");
456
457 if (of_address_to_resource(np_pmu, 0, &res_pmu) ||
458 of_address_to_resource(np_cgu, 0, &res_cgu) ||
459 of_address_to_resource(np_ebu, 0, &res_ebu))
460 panic("Failed to get core resources");
461
462 of_node_put(np_pmu);
463 of_node_put(np_cgu);
464 of_node_put(np_ebu);
465
466 if (!request_mem_region(res_pmu.start, resource_size(&res_pmu),
467 res_pmu.name) ||
468 !request_mem_region(res_cgu.start, resource_size(&res_cgu),
469 res_cgu.name) ||
470 !request_mem_region(res_ebu.start, resource_size(&res_ebu),
471 res_ebu.name))
472 pr_err("Failed to request core resources");
473
474 pmu_membase = ioremap(res_pmu.start, resource_size(&res_pmu));
475 ltq_cgu_membase = ioremap(res_cgu.start,
476 resource_size(&res_cgu));
477 ltq_ebu_membase = ioremap(res_ebu.start,
478 resource_size(&res_ebu));
479 if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
480 panic("Failed to remap core resources");
481
482 /* make sure to unprotect the memory region where flash is located */
483 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
484
485 /* add our generic xway clocks */
486 clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI);
487 clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT);
488 clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP);
489 clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
490 clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA);
491 clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI);
492 clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU);
493 clkdev_add_clkout();
494
495 /* add the soc dependent clocks */
496 if (of_machine_is_compatible("lantiq,vr9")) {
497 ifccr = CGU_IFCCR_VR9;
498 pcicr = CGU_PCICR_VR9;
499 } else {
500 clkdev_add_pmu("1e180000.etop", NULL, 1, 0, PMU_PPE);
501 }
502
503 if (!of_machine_is_compatible("lantiq,ase"))
504 clkdev_add_pci();
505
506 if (of_machine_is_compatible("lantiq,grx390") ||
507 of_machine_is_compatible("lantiq,ar10")) {
508 clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY0);
509 clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY1);
510 clkdev_add_pmu("1e108000.switch", "gphy2", 0, 0, PMU_GPHY2);
511 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB0_P);
512 clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB1_P);
513 /* rc 0 */
514 clkdev_add_pmu("1f106800.phy", "phy", 1, 2, PMU_ANALOG_PCIE0_P);
515 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
516 clkdev_add_pmu("1f106800.phy", "pdi", 1, 1, PMU1_PCIE_PDI);
517 clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
518 /* rc 1 */
519 clkdev_add_pmu("1f700400.phy", "phy", 1, 2, PMU_ANALOG_PCIE1_P);
520 clkdev_add_pmu("19000000.pcie", "msi", 1, 1, PMU1_PCIE1_MSI);
521 clkdev_add_pmu("1f700400.phy", "pdi", 1, 1, PMU1_PCIE1_PDI);
522 clkdev_add_pmu("19000000.pcie", "ctl", 1, 1, PMU1_PCIE1_CTL);
523 }
524
525 if (of_machine_is_compatible("lantiq,ase")) {
526 if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
527 clkdev_add_static(CLOCK_266M, CLOCK_133M,
528 CLOCK_133M, CLOCK_266M);
529 else
530 clkdev_add_static(CLOCK_133M, CLOCK_133M,
531 CLOCK_133M, CLOCK_133M);
532 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
533 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
534 clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);
535 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
536 clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
537 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_ASE_SDIO);
538 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
539 } else if (of_machine_is_compatible("lantiq,grx390")) {
540 clkdev_add_static(ltq_grx390_cpu_hz(), ltq_grx390_fpi_hz(),
541 ltq_grx390_fpi_hz(), ltq_grx390_pp32_hz());
542 clkdev_add_pmu("1e108000.switch", "gphy3", 0, 0, PMU_GPHY3);
543 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
544 clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
545 /* rc 2 */
546 clkdev_add_pmu("1f106a00.pcie", "phy", 1, 2, PMU_ANALOG_PCIE2_P);
547 clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI);
548 clkdev_add_pmu("1f106a00.pcie", "pdi", 1, 1, PMU1_PCIE2_PDI);
549 clkdev_add_pmu("1a800000.pcie", "ctl", 1, 1, PMU1_PCIE2_CTL);
550 clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP);
551 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
552 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
553 } else if (of_machine_is_compatible("lantiq,ar10")) {
554 clkdev_add_static(ltq_ar10_cpu_hz(), ltq_ar10_fpi_hz(),
555 ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz());
556 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
557 clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
558 clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH |
559 PMU_PPE_DP | PMU_PPE_TC);
560 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
561 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
562 clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE);
563 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
564 } else if (of_machine_is_compatible("lantiq,vr9")) {
565 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
566 ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
567 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
568 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
569 clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);
570 clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM);
571 clkdev_add_pmu("1f106800.phy", "phy", 1, 1, PMU1_PCIE_PHY);
572 clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
573 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
574 clkdev_add_pmu("1f106800.phy", "pdi", 1, 1, PMU1_PCIE_PDI);
575 clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
576 clkdev_add_pmu(NULL, "ahb", 1, 0, PMU_AHBM | PMU_AHBS);
577
578 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
579 clkdev_add_pmu("1e10b308.eth", NULL, 0, 0,
580 PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
581 PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
582 PMU_PPE_QSB | PMU_PPE_TOP);
583 clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY);
584 clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY);
585 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
586 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
587 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
588 } else if (of_machine_is_compatible("lantiq,ar9")) {
589 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
590 ltq_ar9_fpi_hz(), CLOCK_250M);
591 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
592 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
593 clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);
594 clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM);
595 clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
596 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
597 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
598 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
599 clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
600 } else {
601 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
602 ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
603 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
604 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
605 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
606 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
607 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
608 clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
609 }
610 usb_set_clock();
611 }
612
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