1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007, 2008, 2009, 2010, 2011 Cavium Networks
7 */
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/interrupt.h>
12 #include <linux/time.h>
13 #include <linux/delay.h>
14 #include <linux/moduleparam.h>
15
16 #include <asm/octeon/octeon.h>
17 #include <asm/octeon/cvmx-npei-defs.h>
18 #include <asm/octeon/cvmx-pciercx-defs.h>
19 #include <asm/octeon/cvmx-pescx-defs.h>
20 #include <asm/octeon/cvmx-pexp-defs.h>
21 #include <asm/octeon/cvmx-pemx-defs.h>
22 #include <asm/octeon/cvmx-dpi-defs.h>
23 #include <asm/octeon/cvmx-sli-defs.h>
24 #include <asm/octeon/cvmx-sriox-defs.h>
25 #include <asm/octeon/cvmx-helper-errata.h>
26 #include <asm/octeon/pci-octeon.h>
27
28 #define MRRS_CN5XXX 0 /* 128 byte Max Read Request Size */
29 #define MPS_CN5XXX 0 /* 128 byte Max Packet Size (Limit of most PCs) */
30 #define MRRS_CN6XXX 3 /* 1024 byte Max Read Request Size */
31 #define MPS_CN6XXX 0 /* 128 byte Max Packet Size (Limit of most PCs) */
32
33 /* Module parameter to disable PCI probing */
34 static int pcie_disable;
35 module_param(pcie_disable, int, S_IRUGO);
36
37 static int enable_pcie_14459_war;
38 static int enable_pcie_bus_num_war[2];
39
40 union cvmx_pcie_address {
41 uint64_t u64;
42 struct {
43 uint64_t upper:2; /* Normally 2 for XKPHYS */
44 uint64_t reserved_49_61:13; /* Must be zero */
45 uint64_t io:1; /* 1 for IO space access */
46 uint64_t did:5; /* PCIe DID = 3 */
47 uint64_t subdid:3; /* PCIe SubDID = 1 */
48 uint64_t reserved_36_39:4; /* Must be zero */
49 uint64_t es:2; /* Endian swap = 1 */
50 uint64_t port:2; /* PCIe port 0,1 */
51 uint64_t reserved_29_31:3; /* Must be zero */
52 /*
53 * Selects the type of the configuration request (0 = type 0,
54 * 1 = type 1).
55 */
56 uint64_t ty:1;
57 /* Target bus number sent in the ID in the request. */
58 uint64_t bus:8;
59 /*
60 * Target device number sent in the ID in the
61 * request. Note that Dev must be zero for type 0
62 * configuration requests.
63 */
64 uint64_t dev:5;
65 /* Target function number sent in the ID in the request. */
66 uint64_t func:3;
67 /*
68 * Selects a register in the configuration space of
69 * the target.
70 */
71 uint64_t reg:12;
72 } config;
73 struct {
74 uint64_t upper:2; /* Normally 2 for XKPHYS */
75 uint64_t reserved_49_61:13; /* Must be zero */
76 uint64_t io:1; /* 1 for IO space access */
77 uint64_t did:5; /* PCIe DID = 3 */
78 uint64_t subdid:3; /* PCIe SubDID = 2 */
79 uint64_t reserved_36_39:4; /* Must be zero */
80 uint64_t es:2; /* Endian swap = 1 */
81 uint64_t port:2; /* PCIe port 0,1 */
82 uint64_t address:32; /* PCIe IO address */
83 } io;
84 struct {
85 uint64_t upper:2; /* Normally 2 for XKPHYS */
86 uint64_t reserved_49_61:13; /* Must be zero */
87 uint64_t io:1; /* 1 for IO space access */
88 uint64_t did:5; /* PCIe DID = 3 */
89 uint64_t subdid:3; /* PCIe SubDID = 3-6 */
90 uint64_t reserved_36_39:4; /* Must be zero */
91 uint64_t address:36; /* PCIe Mem address */
92 } mem;
93 };
94
95 static int cvmx_pcie_rc_initialize(int pcie_port);
96
97 /**
98 * Return the Core virtual base address for PCIe IO access. IOs are
99 * read/written as an offset from this address.
100 *
101 * @pcie_port: PCIe port the IO is for
102 *
103 * Returns 64bit Octeon IO base address for read/write
104 */
105 static inline uint64_t cvmx_pcie_get_io_base_address(int pcie_port)
106 {
107 union cvmx_pcie_address pcie_addr;
108 pcie_addr.u64 = 0;
109 pcie_addr.io.upper = 0;
110 pcie_addr.io.io = 1;
111 pcie_addr.io.did = 3;
112 pcie_addr.io.subdid = 2;
113 pcie_addr.io.es = 1;
114 pcie_addr.io.port = pcie_port;
115 return pcie_addr.u64;
116 }
117
118 /**
119 * Size of the IO address region returned at address
120 * cvmx_pcie_get_io_base_address()
121 *
122 * @pcie_port: PCIe port the IO is for
123 *
124 * Returns Size of the IO window
125 */
126 static inline uint64_t cvmx_pcie_get_io_size(int pcie_port)
127 {
128 return 1ull << 32;
129 }
130
131 /**
132 * Return the Core virtual base address for PCIe MEM access. Memory is
133 * read/written as an offset from this address.
134 *
135 * @pcie_port: PCIe port the IO is for
136 *
137 * Returns 64bit Octeon IO base address for read/write
138 */
139 static inline uint64_t cvmx_pcie_get_mem_base_address(int pcie_port)
140 {
141 union cvmx_pcie_address pcie_addr;
142 pcie_addr.u64 = 0;
143 pcie_addr.mem.upper = 0;
144 pcie_addr.mem.io = 1;
145 pcie_addr.mem.did = 3;
146 pcie_addr.mem.subdid = 3 + pcie_port;
147 return pcie_addr.u64;
148 }
149
150 /**
151 * Size of the Mem address region returned at address
152 * cvmx_pcie_get_mem_base_address()
153 *
154 * @pcie_port: PCIe port the IO is for
155 *
156 * Returns Size of the Mem window
157 */
158 static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port)
159 {
160 return 1ull << 36;
161 }
162
163 /**
164 * Read a PCIe config space register indirectly. This is used for
165 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
166 *
167 * @pcie_port: PCIe port to read from
168 * @cfg_offset: Address to read
169 *
170 * Returns Value read
171 */
172 static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
173 {
174 if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
175 union cvmx_pescx_cfg_rd pescx_cfg_rd;
176 pescx_cfg_rd.u64 = 0;
177 pescx_cfg_rd.s.addr = cfg_offset;
178 cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
179 pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
180 return pescx_cfg_rd.s.data;
181 } else {
182 union cvmx_pemx_cfg_rd pemx_cfg_rd;
183 pemx_cfg_rd.u64 = 0;
184 pemx_cfg_rd.s.addr = cfg_offset;
185 cvmx_write_csr(CVMX_PEMX_CFG_RD(pcie_port), pemx_cfg_rd.u64);
186 pemx_cfg_rd.u64 = cvmx_read_csr(CVMX_PEMX_CFG_RD(pcie_port));
187 return pemx_cfg_rd.s.data;
188 }
189 }
190
191 /**
192 * Write a PCIe config space register indirectly. This is used for
193 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
194 *
195 * @pcie_port: PCIe port to write to
196 * @cfg_offset: Address to write
197 * @val: Value to write
198 */
199 static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
200 uint32_t val)
201 {
202 if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
203 union cvmx_pescx_cfg_wr pescx_cfg_wr;
204 pescx_cfg_wr.u64 = 0;
205 pescx_cfg_wr.s.addr = cfg_offset;
206 pescx_cfg_wr.s.data = val;
207 cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
208 } else {
209 union cvmx_pemx_cfg_wr pemx_cfg_wr;
210 pemx_cfg_wr.u64 = 0;
211 pemx_cfg_wr.s.addr = cfg_offset;
212 pemx_cfg_wr.s.data = val;
213 cvmx_write_csr(CVMX_PEMX_CFG_WR(pcie_port), pemx_cfg_wr.u64);
214 }
215 }
216
217 /**
218 * Build a PCIe config space request address for a device
219 *
220 * @pcie_port: PCIe port to access
221 * @bus: Sub bus
222 * @dev: Device ID
223 * @fn: Device sub function
224 * @reg: Register to access
225 *
226 * Returns 64bit Octeon IO address
227 */
228 static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus,
229 int dev, int fn, int reg)
230 {
231 union cvmx_pcie_address pcie_addr;
232 union cvmx_pciercx_cfg006 pciercx_cfg006;
233 union cvmx_pciercx_cfg032 pciercx_cfg032;
234
235 pciercx_cfg006.u32 =
236 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port));
237 if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0))
238 return 0;
239
240 pciercx_cfg032.u32 =
241 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
242 if ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1))
243 return 0;
244
245 pcie_addr.u64 = 0;
246 pcie_addr.config.upper = 2;
247 pcie_addr.config.io = 1;
248 pcie_addr.config.did = 3;
249 pcie_addr.config.subdid = 1;
250 pcie_addr.config.es = 1;
251 pcie_addr.config.port = pcie_port;
252 pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum);
253 pcie_addr.config.bus = bus;
254 pcie_addr.config.dev = dev;
255 pcie_addr.config.func = fn;
256 pcie_addr.config.reg = reg;
257 return pcie_addr.u64;
258 }
259
260 /**
261 * Read 8bits from a Device's config space
262 *
263 * @pcie_port: PCIe port the device is on
264 * @bus: Sub bus
265 * @dev: Device ID
266 * @fn: Device sub function
267 * @reg: Register to access
268 *
269 * Returns Result of the read
270 */
271 static uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev,
272 int fn, int reg)
273 {
274 uint64_t address =
275 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
276 if (address)
277 return cvmx_read64_uint8(address);
278 else
279 return 0xff;
280 }
281
282 /**
283 * Read 16bits from a Device's config space
284 *
285 * @pcie_port: PCIe port the device is on
286 * @bus: Sub bus
287 * @dev: Device ID
288 * @fn: Device sub function
289 * @reg: Register to access
290 *
291 * Returns Result of the read
292 */
293 static uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev,
294 int fn, int reg)
295 {
296 uint64_t address =
297 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
298 if (address)
299 return le16_to_cpu(cvmx_read64_uint16(address));
300 else
301 return 0xffff;
302 }
303
304 /**
305 * Read 32bits from a Device's config space
306 *
307 * @pcie_port: PCIe port the device is on
308 * @bus: Sub bus
309 * @dev: Device ID
310 * @fn: Device sub function
311 * @reg: Register to access
312 *
313 * Returns Result of the read
314 */
315 static uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev,
316 int fn, int reg)
317 {
318 uint64_t address =
319 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
320 if (address)
321 return le32_to_cpu(cvmx_read64_uint32(address));
322 else
323 return 0xffffffff;
324 }
325
326 /**
327 * Write 8bits to a Device's config space
328 *
329 * @pcie_port: PCIe port the device is on
330 * @bus: Sub bus
331 * @dev: Device ID
332 * @fn: Device sub function
333 * @reg: Register to access
334 * @val: Value to write
335 */
336 static void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn,
337 int reg, uint8_t val)
338 {
339 uint64_t address =
340 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
341 if (address)
342 cvmx_write64_uint8(address, val);
343 }
344
345 /**
346 * Write 16bits to a Device's config space
347 *
348 * @pcie_port: PCIe port the device is on
349 * @bus: Sub bus
350 * @dev: Device ID
351 * @fn: Device sub function
352 * @reg: Register to access
353 * @val: Value to write
354 */
355 static void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn,
356 int reg, uint16_t val)
357 {
358 uint64_t address =
359 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
360 if (address)
361 cvmx_write64_uint16(address, cpu_to_le16(val));
362 }
363
364 /**
365 * Write 32bits to a Device's config space
366 *
367 * @pcie_port: PCIe port the device is on
368 * @bus: Sub bus
369 * @dev: Device ID
370 * @fn: Device sub function
371 * @reg: Register to access
372 * @val: Value to write
373 */
374 static void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn,
375 int reg, uint32_t val)
376 {
377 uint64_t address =
378 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
379 if (address)
380 cvmx_write64_uint32(address, cpu_to_le32(val));
381 }
382
383 /**
384 * Initialize the RC config space CSRs
385 *
386 * @pcie_port: PCIe port to initialize
387 */
388 static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
389 {
390 union cvmx_pciercx_cfg030 pciercx_cfg030;
391 union cvmx_pciercx_cfg070 pciercx_cfg070;
392 union cvmx_pciercx_cfg001 pciercx_cfg001;
393 union cvmx_pciercx_cfg032 pciercx_cfg032;
394 union cvmx_pciercx_cfg006 pciercx_cfg006;
395 union cvmx_pciercx_cfg008 pciercx_cfg008;
396 union cvmx_pciercx_cfg009 pciercx_cfg009;
397 union cvmx_pciercx_cfg010 pciercx_cfg010;
398 union cvmx_pciercx_cfg011 pciercx_cfg011;
399 union cvmx_pciercx_cfg035 pciercx_cfg035;
400 union cvmx_pciercx_cfg075 pciercx_cfg075;
401 union cvmx_pciercx_cfg034 pciercx_cfg034;
402
403 /* Max Payload Size (PCIE*_CFG030[MPS]) */
404 /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
405 /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
406 /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
407
408 pciercx_cfg030.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
409 if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) {
410 pciercx_cfg030.s.mps = MPS_CN5XXX;
411 pciercx_cfg030.s.mrrs = MRRS_CN5XXX;
412 } else {
413 pciercx_cfg030.s.mps = MPS_CN6XXX;
414 pciercx_cfg030.s.mrrs = MRRS_CN6XXX;
415 }
416 /*
417 * Enable relaxed order processing. This will allow devices to
418 * affect read response ordering.
419 */
420 pciercx_cfg030.s.ro_en = 1;
421 /* Enable no snoop processing. Not used by Octeon */
422 pciercx_cfg030.s.ns_en = 1;
423 /* Correctable error reporting enable. */
424 pciercx_cfg030.s.ce_en = 1;
425 /* Non-fatal error reporting enable. */
426 pciercx_cfg030.s.nfe_en = 1;
427 /* Fatal error reporting enable. */
428 pciercx_cfg030.s.fe_en = 1;
429 /* Unsupported request reporting enable. */
430 pciercx_cfg030.s.ur_en = 1;
431 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port), pciercx_cfg030.u32);
432
433
434 if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
435 union cvmx_npei_ctl_status2 npei_ctl_status2;
436 /*
437 * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
438 * PCIE*_CFG030[MPS]. Max Read Request Size
439 * (NPEI_CTL_STATUS2[MRRS]) must not exceed
440 * PCIE*_CFG030[MRRS]
441 */
442 npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
443 /* Max payload size = 128 bytes for best Octeon DMA performance */
444 npei_ctl_status2.s.mps = MPS_CN5XXX;
445 /* Max read request size = 128 bytes for best Octeon DMA performance */
446 npei_ctl_status2.s.mrrs = MRRS_CN5XXX;
447 if (pcie_port)
448 npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */
449 else
450 npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */
451
452 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
453 } else {
454 /*
455 * Max Payload Size (DPI_SLI_PRTX_CFG[MPS]) must match
456 * PCIE*_CFG030[MPS]. Max Read Request Size
457 * (DPI_SLI_PRTX_CFG[MRRS]) must not exceed
458 * PCIE*_CFG030[MRRS].
459 */
460 union cvmx_dpi_sli_prtx_cfg prt_cfg;
461 union cvmx_sli_s2m_portx_ctl sli_s2m_portx_ctl;
462 prt_cfg.u64 = cvmx_read_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port));
463 prt_cfg.s.mps = MPS_CN6XXX;
464 prt_cfg.s.mrrs = MRRS_CN6XXX;
465 /* Max outstanding load request. */
466 prt_cfg.s.molr = 32;
467 cvmx_write_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64);
468
469 sli_s2m_portx_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port));
470 sli_s2m_portx_ctl.s.mrrs = MRRS_CN6XXX;
471 cvmx_write_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port), sli_s2m_portx_ctl.u64);
472 }
473
474 /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
475 pciercx_cfg070.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
476 pciercx_cfg070.s.ge = 1; /* ECRC generation enable. */
477 pciercx_cfg070.s.ce = 1; /* ECRC check enable. */
478 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port), pciercx_cfg070.u32);
479
480 /*
481 * Access Enables (PCIE*_CFG001[MSAE,ME])
482 * ME and MSAE should always be set.
483 * Interrupt Disable (PCIE*_CFG001[I_DIS])
484 * System Error Message Enable (PCIE*_CFG001[SEE])
485 */
486 pciercx_cfg001.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
487 pciercx_cfg001.s.msae = 1; /* Memory space enable. */
488 pciercx_cfg001.s.me = 1; /* Bus master enable. */
489 pciercx_cfg001.s.i_dis = 1; /* INTx assertion disable. */
490 pciercx_cfg001.s.see = 1; /* SERR# enable */
491 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port), pciercx_cfg001.u32);
492
493 /* Advanced Error Recovery Message Enables */
494 /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
495 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG066(pcie_port), 0);
496 /* Use CVMX_PCIERCX_CFG067 hardware default */
497 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0);
498
499
500 /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
501 pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
502 pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
503 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port), pciercx_cfg032.u32);
504
505 /*
506 * Link Width Mode (PCIERCn_CFG452[LME]) - Set during
507 * cvmx_pcie_rc_initialize_link()
508 *
509 * Primary Bus Number (PCIERCn_CFG006[PBNUM])
510 *
511 * We set the primary bus number to 1 so IDT bridges are
512 * happy. They don't like zero.
513 */
514 pciercx_cfg006.u32 = 0;
515 pciercx_cfg006.s.pbnum = 1;
516 pciercx_cfg006.s.sbnum = 1;
517 pciercx_cfg006.s.subbnum = 1;
518 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port), pciercx_cfg006.u32);
519
520
521 /*
522 * Memory-mapped I/O BAR (PCIERCn_CFG008)
523 * Most applications should disable the memory-mapped I/O BAR by
524 * setting PCIERCn_CFG008[ML_ADDR] < PCIERCn_CFG008[MB_ADDR]
525 */
526 pciercx_cfg008.u32 = 0;
527 pciercx_cfg008.s.mb_addr = 0x100;
528 pciercx_cfg008.s.ml_addr = 0;
529 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port), pciercx_cfg008.u32);
530
531
532 /*
533 * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011)
534 * Most applications should disable the prefetchable BAR by setting
535 * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] <
536 * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE]
537 */
538 pciercx_cfg009.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
539 pciercx_cfg010.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
540 pciercx_cfg011.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
541 pciercx_cfg009.s.lmem_base = 0x100;
542 pciercx_cfg009.s.lmem_limit = 0;
543 pciercx_cfg010.s.umem_base = 0x100;
544 pciercx_cfg011.s.umem_limit = 0;
545 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port), pciercx_cfg009.u32);
546 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32);
547 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port), pciercx_cfg011.u32);
548
549 /*
550 * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE])
551 * PME Interrupt Enables (PCIERCn_CFG035[PMEIE])
552 */
553 pciercx_cfg035.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
554 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */
555 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */
556 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */
557 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */
558 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32);
559
560 /*
561 * Advanced Error Recovery Interrupt Enables
562 * (PCIERCn_CFG075[CERE,NFERE,FERE])
563 */
564 pciercx_cfg075.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
565 pciercx_cfg075.s.cere = 1; /* Correctable error reporting enable. */
566 pciercx_cfg075.s.nfere = 1; /* Non-fatal error reporting enable. */
567 pciercx_cfg075.s.fere = 1; /* Fatal error reporting enable. */
568 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port), pciercx_cfg075.u32);
569
570 /*
571 * HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
572 * PCIERCn_CFG034[DLLS_EN,CCINT_EN])
573 */
574 pciercx_cfg034.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
575 pciercx_cfg034.s.hpint_en = 1; /* Hot-plug interrupt enable. */
576 pciercx_cfg034.s.dlls_en = 1; /* Data Link Layer state changed enable */
577 pciercx_cfg034.s.ccint_en = 1; /* Command completed interrupt enable. */
578 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port), pciercx_cfg034.u32);
579 }
580
581 /**
582 * Initialize a host mode PCIe gen 1 link. This function takes a PCIe
583 * port from reset to a link up state. Software can then begin
584 * configuring the rest of the link.
585 *
586 * @pcie_port: PCIe port to initialize
587 *
588 * Returns Zero on success
589 */
590 static int __cvmx_pcie_rc_initialize_link_gen1(int pcie_port)
591 {
592 uint64_t start_cycle;
593 union cvmx_pescx_ctl_status pescx_ctl_status;
594 union cvmx_pciercx_cfg452 pciercx_cfg452;
595 union cvmx_pciercx_cfg032 pciercx_cfg032;
596 union cvmx_pciercx_cfg448 pciercx_cfg448;
597
598 /* Set the lane width */
599 pciercx_cfg452.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
600 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
601 if (pescx_ctl_status.s.qlm_cfg == 0)
602 /* We're in 8 lane (56XX) or 4 lane (54XX) mode */
603 pciercx_cfg452.s.lme = 0xf;
604 else
605 /* We're in 4 lane (56XX) or 2 lane (52XX) mode */
606 pciercx_cfg452.s.lme = 0x7;
607 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port), pciercx_cfg452.u32);
608
609 /*
610 * CN52XX pass 1.x has an errata where length mismatches on UR
611 * responses can cause bus errors on 64bit memory
612 * reads. Turning off length error checking fixes this.
613 */
614 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
615 union cvmx_pciercx_cfg455 pciercx_cfg455;
616 pciercx_cfg455.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG455(pcie_port));
617 pciercx_cfg455.s.m_cpl_len_err = 1;
618 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port), pciercx_cfg455.u32);
619 }
620
621 /* Lane swap needs to be manually enabled for CN52XX */
622 if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) {
623 pescx_ctl_status.s.lane_swp = 1;
624 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
625 }
626
627 /* Bring up the link */
628 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
629 pescx_ctl_status.s.lnk_enb = 1;
630 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
631
632 /*
633 * CN52XX pass 1.0: Due to a bug in 2nd order CDR, it needs to
634 * be disabled.
635 */
636 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0))
637 __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0);
638
639 /* Wait for the link to come up */
640 start_cycle = cvmx_get_cycle();
641 do {
642 if (cvmx_get_cycle() - start_cycle > 2 * octeon_get_clock_rate()) {
643 cvmx_dprintf("PCIe: Port %d link timeout\n", pcie_port);
644 return -1;
645 }
646 __delay(10000);
647 pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
648 } while (pciercx_cfg032.s.dlla == 0);
649
650 /* Clear all pending errors */
651 cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
652
653 /*
654 * Update the Replay Time Limit. Empirically, some PCIe
655 * devices take a little longer to respond than expected under
656 * load. As a workaround for this we configure the Replay Time
657 * Limit to the value expected for a 512 byte MPS instead of
658 * our actual 256 byte MPS. The numbers below are directly
659 * from the PCIe spec table 3-4.
660 */
661 pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
662 switch (pciercx_cfg032.s.nlw) {
663 case 1: /* 1 lane */
664 pciercx_cfg448.s.rtl = 1677;
665 break;
666 case 2: /* 2 lanes */
667 pciercx_cfg448.s.rtl = 867;
668 break;
669 case 4: /* 4 lanes */
670 pciercx_cfg448.s.rtl = 462;
671 break;
672 case 8: /* 8 lanes */
673 pciercx_cfg448.s.rtl = 258;
674 break;
675 }
676 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);
677
678 return 0;
679 }
680
681 static void __cvmx_increment_ba(union cvmx_sli_mem_access_subidx *pmas)
682 {
683 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
684 pmas->cn68xx.ba++;
685 else
686 pmas->s.ba++;
687 }
688
689 /**
690 * Initialize a PCIe gen 1 port for use in host(RC) mode. It doesn't
691 * enumerate the bus.
692 *
693 * @pcie_port: PCIe port to initialize
694 *
695 * Returns Zero on success
696 */
697 static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
698 {
699 int i;
700 int base;
701 u64 addr_swizzle;
702 union cvmx_ciu_soft_prst ciu_soft_prst;
703 union cvmx_pescx_bist_status pescx_bist_status;
704 union cvmx_pescx_bist_status2 pescx_bist_status2;
705 union cvmx_npei_ctl_status npei_ctl_status;
706 union cvmx_npei_mem_access_ctl npei_mem_access_ctl;
707 union cvmx_npei_mem_access_subidx mem_access_subid;
708 union cvmx_npei_dbg_data npei_dbg_data;
709 union cvmx_pescx_ctl_status2 pescx_ctl_status2;
710 union cvmx_pciercx_cfg032 pciercx_cfg032;
711 union cvmx_npei_bar1_indexx bar1_index;
712
713 retry:
714 /*
715 * Make sure we aren't trying to setup a target mode interface
716 * in host mode.
717 */
718 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
719 if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) {
720 cvmx_dprintf("PCIe: Port %d in endpoint mode\n", pcie_port);
721 return -1;
722 }
723
724 /*
725 * Make sure a CN52XX isn't trying to bring up port 1 when it
726 * is disabled.
727 */
728 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
729 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
730 if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) {
731 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called on port1, but port1 is disabled\n");
732 return -1;
733 }
734 }
735
736 /*
737 * PCIe switch arbitration mode. '' == fixed priority NPEI,
738 * PCIe0, then PCIe1. '1' == round robin.
739 */
740 npei_ctl_status.s.arb = 1;
741 /* Allow up to 0x20 config retries */
742 npei_ctl_status.s.cfg_rtry = 0x20;
743 /*
744 * CN52XX pass1.x has an errata where P0_NTAGS and P1_NTAGS
745 * don't reset.
746 */
747 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
748 npei_ctl_status.s.p0_ntags = 0x20;
749 npei_ctl_status.s.p1_ntags = 0x20;
750 }
751 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS, npei_ctl_status.u64);
752
753 /* Bring the PCIe out of reset */
754 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) {
755 /*
756 * The EBH5200 board swapped the PCIe reset lines on
757 * the board. As a workaround for this bug, we bring
758 * both PCIe ports out of reset at the same time
759 * instead of on separate calls. So for port 0, we
760 * bring both out of reset and do nothing on port 1
761 */
762 if (pcie_port == 0) {
763 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
764 /*
765 * After a chip reset the PCIe will also be in
766 * reset. If it isn't, most likely someone is
767 * trying to init it again without a proper
768 * PCIe reset.
769 */
770 if (ciu_soft_prst.s.soft_prst == 0) {
771 /* Reset the ports */
772 ciu_soft_prst.s.soft_prst = 1;
773 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
774 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
775 ciu_soft_prst.s.soft_prst = 1;
776 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
777 /* Wait until pcie resets the ports. */
778 udelay(2000);
779 }
780 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
781 ciu_soft_prst.s.soft_prst = 0;
782 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
783 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
784 ciu_soft_prst.s.soft_prst = 0;
785 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
786 }
787 } else {
788 /*
789 * The normal case: The PCIe ports are completely
790 * separate and can be brought out of reset
791 * independently.
792 */
793 if (pcie_port)
794 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
795 else
796 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
797 /*
798 * After a chip reset the PCIe will also be in
799 * reset. If it isn't, most likely someone is trying
800 * to init it again without a proper PCIe reset.
801 */
802 if (ciu_soft_prst.s.soft_prst == 0) {
803 /* Reset the port */
804 ciu_soft_prst.s.soft_prst = 1;
805 if (pcie_port)
806 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
807 else
808 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
809 /* Wait until pcie resets the ports. */
810 udelay(2000);
811 }
812 if (pcie_port) {
813 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
814 ciu_soft_prst.s.soft_prst = 0;
815 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
816 } else {
817 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
818 ciu_soft_prst.s.soft_prst = 0;
819 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
820 }
821 }
822
823 /*
824 * Wait for PCIe reset to complete. Due to errata PCIE-700, we
825 * don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a
826 * fixed number of cycles.
827 */
828 __delay(400000);
829
830 /*
831 * PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of
832 * CN56XX and CN52XX, so we only probe it on newer chips
833 */
834 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
835 /* Clear PCLK_RUN so we can check if the clock is running */
836 pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
837 pescx_ctl_status2.s.pclk_run = 1;
838 cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port), pescx_ctl_status2.u64);
839 /* Now that we cleared PCLK_RUN, wait for it to be set
840 * again telling us the clock is running
841 */
842 if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port),
843 union cvmx_pescx_ctl_status2, pclk_run, ==, 1, 10000)) {
844 cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n", pcie_port);
845 return -1;
846 }
847 }
848
849 /*
850 * Check and make sure PCIe came out of reset. If it doesn't
851 * the board probably hasn't wired the clocks up and the
852 * interface should be skipped.
853 */
854 pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
855 if (pescx_ctl_status2.s.pcierst) {
856 cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);
857 return -1;
858 }
859
860 /*
861 * Check BIST2 status. If any bits are set skip this
862 * interface. This is an attempt to catch PCIE-813 on pass 1
863 * parts.
864 */
865 pescx_bist_status2.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
866 if (pescx_bist_status2.u64) {
867 cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this port isn't hooked up, skipping.\n",
868 pcie_port);
869 return -1;
870 }
871
872 /* Check BIST status */
873 pescx_bist_status.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
874 if (pescx_bist_status.u64)
875 cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n",
876 pcie_port, CAST64(pescx_bist_status.u64));
877
878 /* Initialize the config space CSRs */
879 __cvmx_pcie_rc_initialize_config_space(pcie_port);
880
881 /* Bring the link up */
882 if (__cvmx_pcie_rc_initialize_link_gen1(pcie_port)) {
883 cvmx_dprintf("PCIe: Failed to initialize port %d, probably the slot is empty\n",
884 pcie_port);
885 return -1;
886 }
887
888 /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
889 npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
890 npei_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */
891 npei_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */
892 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
893
894 /* Setup Mem access SubDIDs */
895 mem_access_subid.u64 = 0;
896 mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
897 mem_access_subid.s.nmerge = 1; /* Due to an errata on pass 1 chips, no merging is allowed. */
898 mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */
899 mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
900 mem_access_subid.s.nsr = 0; /* Enable Snooping for Reads. Octeon doesn't care, but devices might want this more conservative setting */
901 mem_access_subid.s.nsw = 0; /* Enable Snoop for Writes. */
902 mem_access_subid.s.ror = 0; /* Disable Relaxed Ordering for Reads. */
903 mem_access_subid.s.row = 0; /* Disable Relaxed Ordering for Writes. */
904 mem_access_subid.s.ba = 0; /* PCIe Address Bits <63:34>. */
905
906 /*
907 * Setup mem access 12-15 for port 0, 16-19 for port 1,
908 * supplying 36 bits of address space.
909 */
910 for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
911 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
912 mem_access_subid.s.ba += 1; /* Set each SUBID to extend the addressable range */
913 }
914
915 /*
916 * Disable the peer to peer forwarding register. This must be
917 * setup by the OS after it enumerates the bus and assigns
918 * addresses to the PCIe busses.
919 */
920 for (i = 0; i < 4; i++) {
921 cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i, pcie_port), -1);
922 cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i, pcie_port), -1);
923 }
924
925 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
926 cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
927
928 /* BAR1 follows BAR2 with a gap so it has the same address as for gen2. */
929 cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
930
931 bar1_index.u32 = 0;
932 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
933 bar1_index.s.ca = 1; /* Not Cached */
934 bar1_index.s.end_swp = 1; /* Endian Swap mode */
935 bar1_index.s.addr_v = 1; /* Valid entry */
936
937 base = pcie_port ? 16 : 0;
938
939 /* Big endian swizzle for 32-bit PEXP_NCB register. */
940 #ifdef __MIPSEB__
941 addr_swizzle = 4;
942 #else
943 addr_swizzle = 0;
944 #endif
945 for (i = 0; i < 16; i++) {
946 cvmx_write64_uint32((CVMX_PEXP_NPEI_BAR1_INDEXX(base) ^ addr_swizzle),
947 bar1_index.u32);
948 base++;
949 /* 256MB / 16 >> 22 == 4 */
950 bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
951 }
952
953 /*
954 * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take
955 * precedence where they overlap. It also overlaps with the
956 * device addresses, so make sure the peer to peer forwarding
957 * is set right.
958 */
959 cvmx_write_csr(CVMX_PESCX_P2N_BAR2_START(pcie_port), 0);
960
961 /*
962 * Setup BAR2 attributes
963 *
964 * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
965 * - PTLP_RO,CTLP_RO should normally be set (except for debug).
966 * - WAIT_COM=0 will likely work for all applications.
967 *
968 * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]).
969 */
970 if (pcie_port) {
971 union cvmx_npei_ctl_port1 npei_ctl_port;
972 npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT1);
973 npei_ctl_port.s.bar2_enb = 1;
974 npei_ctl_port.s.bar2_esx = 1;
975 npei_ctl_port.s.bar2_cax = 0;
976 npei_ctl_port.s.ptlp_ro = 1;
977 npei_ctl_port.s.ctlp_ro = 1;
978 npei_ctl_port.s.wait_com = 0;
979 npei_ctl_port.s.waitl_com = 0;
980 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT1, npei_ctl_port.u64);
981 } else {
982 union cvmx_npei_ctl_port0 npei_ctl_port;
983 npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT0);
984 npei_ctl_port.s.bar2_enb = 1;
985 npei_ctl_port.s.bar2_esx = 1;
986 npei_ctl_port.s.bar2_cax = 0;
987 npei_ctl_port.s.ptlp_ro = 1;
988 npei_ctl_port.s.ctlp_ro = 1;
989 npei_ctl_port.s.wait_com = 0;
990 npei_ctl_port.s.waitl_com = 0;
991 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64);
992 }
993
994 /*
995 * Both pass 1 and pass 2 of CN52XX and CN56XX have an errata
996 * that causes TLP ordering to not be preserved after multiple
997 * PCIe port resets. This code detects this fault and corrects
998 * it by aligning the TLP counters properly. Another link
999 * reset is then performed. See PCIE-13340
1000 */
1001 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
1002 OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) ||
1003 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) ||
1004 OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
1005 union cvmx_npei_dbg_data dbg_data;
1006 int old_in_fif_p_count;
1007 int in_fif_p_count;
1008 int out_p_count;
1009 int in_p_offset = (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) ? 4 : 1;
1010 int i;
1011
1012 /*
1013 * Choose a write address of 1MB. It should be
1014 * harmless as all bars haven't been setup.
1015 */
1016 uint64_t write_address = (cvmx_pcie_get_mem_base_address(pcie_port) + 0x100000) | (1ull<<63);
1017
1018 /*
1019 * Make sure at least in_p_offset have been executed before we try and
1020 * read in_fif_p_count
1021 */
1022 i = in_p_offset;
1023 while (i--) {
1024 cvmx_write64_uint32(write_address, 0);
1025 __delay(10000);
1026 }
1027
1028 /*
1029 * Read the IN_FIF_P_COUNT from the debug
1030 * select. IN_FIF_P_COUNT can be unstable sometimes so
1031 * read it twice with a write between the reads. This
1032 * way we can tell the value is good as it will
1033 * increment by one due to the write
1034 */
1035 cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd7fc : 0xcffc);
1036 cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT);
1037 do {
1038 dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1039 old_in_fif_p_count = dbg_data.s.data & 0xff;
1040 cvmx_write64_uint32(write_address, 0);
1041 __delay(10000);
1042 dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1043 in_fif_p_count = dbg_data.s.data & 0xff;
1044 } while (in_fif_p_count != ((old_in_fif_p_count+1) & 0xff));
1045
1046 /* Update in_fif_p_count for its offset with respect to out_p_count */
1047 in_fif_p_count = (in_fif_p_count + in_p_offset) & 0xff;
1048
1049 /* Read the OUT_P_COUNT from the debug select */
1050 cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd00f : 0xc80f);
1051 cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT);
1052 dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1053 out_p_count = (dbg_data.s.data>>1) & 0xff;
1054
1055 /* Check that the two counters are aligned */
1056 if (out_p_count != in_fif_p_count) {
1057 cvmx_dprintf("PCIe: Port %d aligning TLP counters as workaround to maintain ordering\n", pcie_port);
1058 while (in_fif_p_count != 0) {
1059 cvmx_write64_uint32(write_address, 0);
1060 __delay(10000);
1061 in_fif_p_count = (in_fif_p_count + 1) & 0xff;
1062 }
1063 /*
1064 * The EBH5200 board swapped the PCIe reset
1065 * lines on the board. This means we must
1066 * bring both links down and up, which will
1067 * cause the PCIe0 to need alignment
1068 * again. Lots of messages will be displayed,
1069 * but everything should work
1070 */
1071 if ((cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) &&
1072 (pcie_port == 1))
1073 cvmx_pcie_rc_initialize(0);
1074 /* Rety bringing this port up */
1075 goto retry;
1076 }
1077 }
1078
1079 /* Display the link status */
1080 pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1081 cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port, pciercx_cfg032.s.nlw);
1082
1083 return 0;
1084 }
1085
1086 /**
1087 * Initialize a host mode PCIe gen 2 link. This function takes a PCIe
1088 * port from reset to a link up state. Software can then begin
1089 * configuring the rest of the link.
1090 *
1091 * @pcie_port: PCIe port to initialize
1092 *
1093 * Return Zero on success.
1094 */
1095 static int __cvmx_pcie_rc_initialize_link_gen2(int pcie_port)
1096 {
1097 uint64_t start_cycle;
1098 union cvmx_pemx_ctl_status pem_ctl_status;
1099 union cvmx_pciercx_cfg032 pciercx_cfg032;
1100 union cvmx_pciercx_cfg448 pciercx_cfg448;
1101
1102 /* Bring up the link */
1103 pem_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));
1104 pem_ctl_status.s.lnk_enb = 1;
1105 cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pem_ctl_status.u64);
1106
1107 /* Wait for the link to come up */
1108 start_cycle = cvmx_get_cycle();
1109 do {
1110 if (cvmx_get_cycle() - start_cycle > octeon_get_clock_rate())
1111 return -1;
1112 __delay(10000);
1113 pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1114 } while ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1));
1115
1116 /*
1117 * Update the Replay Time Limit. Empirically, some PCIe
1118 * devices take a little longer to respond than expected under
1119 * load. As a workaround for this we configure the Replay Time
1120 * Limit to the value expected for a 512 byte MPS instead of
1121 * our actual 256 byte MPS. The numbers below are directly
1122 * from the PCIe spec table 3-4
1123 */
1124 pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
1125 switch (pciercx_cfg032.s.nlw) {
1126 case 1: /* 1 lane */
1127 pciercx_cfg448.s.rtl = 1677;
1128 break;
1129 case 2: /* 2 lanes */
1130 pciercx_cfg448.s.rtl = 867;
1131 break;
1132 case 4: /* 4 lanes */
1133 pciercx_cfg448.s.rtl = 462;
1134 break;
1135 case 8: /* 8 lanes */
1136 pciercx_cfg448.s.rtl = 258;
1137 break;
1138 }
1139 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);
1140
1141 return 0;
1142 }
1143
1144
1145 /**
1146 * Initialize a PCIe gen 2 port for use in host(RC) mode. It doesn't enumerate
1147 * the bus.
1148 *
1149 * @pcie_port: PCIe port to initialize
1150 *
1151 * Returns Zero on success.
1152 */
1153 static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
1154 {
1155 int i;
1156 union cvmx_ciu_soft_prst ciu_soft_prst;
1157 union cvmx_mio_rst_ctlx mio_rst_ctl;
1158 union cvmx_pemx_bar_ctl pemx_bar_ctl;
1159 union cvmx_pemx_ctl_status pemx_ctl_status;
1160 union cvmx_pemx_bist_status pemx_bist_status;
1161 union cvmx_pemx_bist_status2 pemx_bist_status2;
1162 union cvmx_pciercx_cfg032 pciercx_cfg032;
1163 union cvmx_pciercx_cfg515 pciercx_cfg515;
1164 union cvmx_sli_ctl_portx sli_ctl_portx;
1165 union cvmx_sli_mem_access_ctl sli_mem_access_ctl;
1166 union cvmx_sli_mem_access_subidx mem_access_subid;
1167 union cvmx_sriox_status_reg sriox_status_reg;
1168 union cvmx_pemx_bar1_indexx bar1_index;
1169
1170 if (octeon_has_feature(OCTEON_FEATURE_SRIO)) {
1171 /* Make sure this interface isn't SRIO */
1172 if (OCTEON_IS_MODEL(OCTEON_CN66XX)) {
1173 /*
1174 * The CN66XX requires reading the
1175 * MIO_QLMX_CFG register to figure out the
1176 * port type.
1177 */
1178 union cvmx_mio_qlmx_cfg qlmx_cfg;
1179 qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(pcie_port));
1180
1181 if (qlmx_cfg.s.qlm_spd == 15) {
1182 pr_notice("PCIe: Port %d is disabled, skipping.\n", pcie_port);
1183 return -1;
1184 }
1185
1186 switch (qlmx_cfg.s.qlm_spd) {
1187 case 0x1: /* SRIO 1x4 short */
1188 case 0x3: /* SRIO 1x4 long */
1189 case 0x4: /* SRIO 2x2 short */
1190 case 0x6: /* SRIO 2x2 long */
1191 pr_notice("PCIe: Port %d is SRIO, skipping.\n", pcie_port);
1192 return -1;
1193 case 0x9: /* SGMII */
1194 pr_notice("PCIe: Port %d is SGMII, skipping.\n", pcie_port);
1195 return -1;
1196 case 0xb: /* XAUI */
1197 pr_notice("PCIe: Port %d is XAUI, skipping.\n", pcie_port);
1198 return -1;
1199 case 0x0: /* PCIE gen2 */
1200 case 0x8: /* PCIE gen2 (alias) */
1201 case 0x2: /* PCIE gen1 */
1202 case 0xa: /* PCIE gen1 (alias) */
1203 break;
1204 default:
1205 pr_notice("PCIe: Port %d is unknown, skipping.\n", pcie_port);
1206 return -1;
1207 }
1208 } else {
1209 sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(pcie_port));
1210 if (sriox_status_reg.s.srio) {
1211 pr_notice("PCIe: Port %d is SRIO, skipping.\n", pcie_port);
1212 return -1;
1213 }
1214 }
1215 }
1216
1217 #if 0
1218 /* This code is so that the PCIe analyzer is able to see 63XX traffic */
1219 pr_notice("PCIE : init for pcie analyzer.\n");
1220 cvmx_helper_qlm_jtag_init();
1221 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
1222 cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
1223 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1224 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
1225 cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
1226 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1227 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
1228 cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
1229 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1230 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
1231 cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
1232 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1233 cvmx_helper_qlm_jtag_update(pcie_port);
1234 #endif
1235
1236 /* Make sure we aren't trying to setup a target mode interface in host mode */
1237 mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(pcie_port));
1238 if (!mio_rst_ctl.s.host_mode) {
1239 pr_notice("PCIe: Port %d in endpoint mode.\n", pcie_port);
1240 return -1;
1241 }
1242
1243 /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */
1244 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0)) {
1245 if (pcie_port) {
1246 union cvmx_ciu_qlm ciu_qlm;
1247 ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM1);
1248 ciu_qlm.s.txbypass = 1;
1249 ciu_qlm.s.txdeemph = 5;
1250 ciu_qlm.s.txmargin = 0x17;
1251 cvmx_write_csr(CVMX_CIU_QLM1, ciu_qlm.u64);
1252 } else {
1253 union cvmx_ciu_qlm ciu_qlm;
1254 ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM0);
1255 ciu_qlm.s.txbypass = 1;
1256 ciu_qlm.s.txdeemph = 5;
1257 ciu_qlm.s.txmargin = 0x17;
1258 cvmx_write_csr(CVMX_CIU_QLM0, ciu_qlm.u64);
1259 }
1260 }
1261 /* Bring the PCIe out of reset */
1262 if (pcie_port)
1263 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1264 else
1265 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1266 /*
1267 * After a chip reset the PCIe will also be in reset. If it
1268 * isn't, most likely someone is trying to init it again
1269 * without a proper PCIe reset
1270 */
1271 if (ciu_soft_prst.s.soft_prst == 0) {
1272 /* Reset the port */
1273 ciu_soft_prst.s.soft_prst = 1;
1274 if (pcie_port)
1275 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
1276 else
1277 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
1278 /* Wait until pcie resets the ports. */
1279 udelay(2000);
1280 }
1281 if (pcie_port) {
1282 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1283 ciu_soft_prst.s.soft_prst = 0;
1284 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
1285 } else {
1286 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1287 ciu_soft_prst.s.soft_prst = 0;
1288 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
1289 }
1290
1291 /* Wait for PCIe reset to complete */
1292 udelay(1000);
1293
1294 /*
1295 * Check and make sure PCIe came out of reset. If it doesn't
1296 * the board probably hasn't wired the clocks up and the
1297 * interface should be skipped.
1298 */
1299 if (CVMX_WAIT_FOR_FIELD64(CVMX_MIO_RST_CTLX(pcie_port), union cvmx_mio_rst_ctlx, rst_done, ==, 1, 10000)) {
1300 pr_notice("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);
1301 return -1;
1302 }
1303
1304 /* Check BIST status */
1305 pemx_bist_status.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS(pcie_port));
1306 if (pemx_bist_status.u64)
1307 pr_notice("PCIe: BIST FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status.u64));
1308 pemx_bist_status2.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS2(pcie_port));
1309 /* Errata PCIE-14766 may cause the lower 6 bits to be randomly set on CN63XXp1 */
1310 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
1311 pemx_bist_status2.u64 &= ~0x3full;
1312 if (pemx_bist_status2.u64)
1313 pr_notice("PCIe: BIST2 FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status2.u64));
1314
1315 /* Initialize the config space CSRs */
1316 __cvmx_pcie_rc_initialize_config_space(pcie_port);
1317
1318 /* Enable gen2 speed selection */
1319 pciercx_cfg515.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG515(pcie_port));
1320 pciercx_cfg515.s.dsc = 1;
1321 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG515(pcie_port), pciercx_cfg515.u32);
1322
1323 /* Bring the link up */
1324 if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port)) {
1325 /*
1326 * Some gen1 devices don't handle the gen 2 training
1327 * correctly. Disable gen2 and try again with only
1328 * gen1
1329 */
1330 union cvmx_pciercx_cfg031 pciercx_cfg031;
1331 pciercx_cfg031.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG031(pcie_port));
1332 pciercx_cfg031.s.mls = 1;
1333 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG031(pcie_port), pciercx_cfg031.u32);
1334 if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port)) {
1335 pr_notice("PCIe: Link timeout on port %d, probably the slot is empty\n", pcie_port);
1336 return -1;
1337 }
1338 }
1339
1340 /* Store merge control (SLI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
1341 sli_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL);
1342 sli_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */
1343 sli_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */
1344 cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL, sli_mem_access_ctl.u64);
1345
1346 /* Setup Mem access SubDIDs */
1347 mem_access_subid.u64 = 0;
1348 mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
1349 mem_access_subid.s.nmerge = 0; /* Allow merging as it works on CN6XXX. */
1350 mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */
1351 mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
1352 mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
1353 mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
1354 /* PCIe Address Bits <63:34>. */
1355 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
1356 mem_access_subid.cn68xx.ba = 0;
1357 else
1358 mem_access_subid.s.ba = 0;
1359
1360 /*
1361 * Setup mem access 12-15 for port 0, 16-19 for port 1,
1362 * supplying 36 bits of address space.
1363 */
1364 for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
1365 cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
1366 /* Set each SUBID to extend the addressable range */
1367 __cvmx_increment_ba(&mem_access_subid);
1368 }
1369
1370 /*
1371 * Disable the peer to peer forwarding register. This must be
1372 * setup by the OS after it enumerates the bus and assigns
1373 * addresses to the PCIe busses.
1374 */
1375 for (i = 0; i < 4; i++) {
1376 cvmx_write_csr(CVMX_PEMX_P2P_BARX_START(i, pcie_port), -1);
1377 cvmx_write_csr(CVMX_PEMX_P2P_BARX_END(i, pcie_port), -1);
1378 }
1379
1380 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
1381 cvmx_write_csr(CVMX_PEMX_P2N_BAR0_START(pcie_port), 0);
1382
1383 /*
1384 * Set Octeon's BAR2 to decode 0-2^41. Bar0 and Bar1 take
1385 * precedence where they overlap. It also overlaps with the
1386 * device addresses, so make sure the peer to peer forwarding
1387 * is set right.
1388 */
1389 cvmx_write_csr(CVMX_PEMX_P2N_BAR2_START(pcie_port), 0);
1390
1391 /*
1392 * Setup BAR2 attributes
1393 * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
1394 * - PTLP_RO,CTLP_RO should normally be set (except for debug).
1395 * - WAIT_COM=0 will likely work for all applications.
1396 * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM])
1397 */
1398 pemx_bar_ctl.u64 = cvmx_read_csr(CVMX_PEMX_BAR_CTL(pcie_port));
1399 pemx_bar_ctl.s.bar1_siz = 3; /* 256MB BAR1*/
1400 pemx_bar_ctl.s.bar2_enb = 1;
1401 pemx_bar_ctl.s.bar2_esx = 1;
1402 pemx_bar_ctl.s.bar2_cax = 0;
1403 cvmx_write_csr(CVMX_PEMX_BAR_CTL(pcie_port), pemx_bar_ctl.u64);
1404 sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port));
1405 sli_ctl_portx.s.ptlp_ro = 1;
1406 sli_ctl_portx.s.ctlp_ro = 1;
1407 sli_ctl_portx.s.wait_com = 0;
1408 sli_ctl_portx.s.waitl_com = 0;
1409 cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port), sli_ctl_portx.u64);
1410
1411 /* BAR1 follows BAR2 */
1412 cvmx_write_csr(CVMX_PEMX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
1413
1414 bar1_index.u64 = 0;
1415 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
1416 bar1_index.s.ca = 1; /* Not Cached */
1417 bar1_index.s.end_swp = 1; /* Endian Swap mode */
1418 bar1_index.s.addr_v = 1; /* Valid entry */
1419
1420 for (i = 0; i < 16; i++) {
1421 cvmx_write_csr(CVMX_PEMX_BAR1_INDEXX(i, pcie_port), bar1_index.u64);
1422 /* 256MB / 16 >> 22 == 4 */
1423 bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
1424 }
1425
1426 /*
1427 * Allow config retries for 250ms. Count is based off the 5Ghz
1428 * SERDES clock.
1429 */
1430 pemx_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));
1431 pemx_ctl_status.s.cfg_rtry = 250 * 5000000 / 0x10000;
1432 cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pemx_ctl_status.u64);
1433
1434 /* Display the link status */
1435 pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1436 pr_notice("PCIe: Port %d link active, %d lanes, speed gen%d\n", pcie_port, pciercx_cfg032.s.nlw, pciercx_cfg032.s.ls);
1437
1438 return 0;
1439 }
1440
1441 /**
1442 * Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus.
1443 *
1444 * @pcie_port: PCIe port to initialize
1445 *
1446 * Returns Zero on success
1447 */
1448 static int cvmx_pcie_rc_initialize(int pcie_port)
1449 {
1450 int result;
1451 if (octeon_has_feature(OCTEON_FEATURE_NPEI))
1452 result = __cvmx_pcie_rc_initialize_gen1(pcie_port);
1453 else
1454 result = __cvmx_pcie_rc_initialize_gen2(pcie_port);
1455 return result;
1456 }
1457
1458 /* Above was cvmx-pcie.c, below original pcie.c */
1459
1460 /**
1461 * Map a PCI device to the appropriate interrupt line
1462 *
1463 * @dev: The Linux PCI device structure for the device to map
1464 * @slot: The slot number for this device on __BUS 0__. Linux
1465 * enumerates through all the bridges and figures out the
1466 * slot on Bus 0 where this device eventually hooks to.
1467 * @pin: The PCI interrupt pin read from the device, then swizzled
1468 * as it goes through each bridge.
1469 * Returns Interrupt number for the device
1470 */
1471 int octeon_pcie_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
1472 {
1473 /*
1474 * The EBH5600 board with the PCI to PCIe bridge mistakenly
1475 * wires the first slot for both device id 2 and interrupt
1476 * A. According to the PCI spec, device id 2 should be C. The
1477 * following kludge attempts to fix this.
1478 */
1479 if (strstr(octeon_board_type_string(), "EBH5600") &&
1480 dev->bus && dev->bus->parent) {
1481 /*
1482 * Iterate all the way up the device chain and find
1483 * the root bus.
1484 */
1485 while (dev->bus && dev->bus->parent)
1486 dev = to_pci_dev(dev->bus->bridge);
1487 /*
1488 * If the root bus is number 0 and the PEX 8114 is the
1489 * root, assume we are behind the miswired bus. We
1490 * need to correct the swizzle level by two. Yuck.
1491 */
1492 if ((dev->bus->number == 1) &&
1493 (dev->vendor == 0x10b5) && (dev->device == 0x8114)) {
1494 /*
1495 * The pin field is one based, not zero. We
1496 * need to swizzle it by minus two.
1497 */
1498 pin = ((pin - 3) & 3) + 1;
1499 }
1500 }
1501 /*
1502 * The -1 is because pin starts with one, not zero. It might
1503 * be that this equation needs to include the slot number, but
1504 * I don't have hardware to check that against.
1505 */
1506 return pin - 1 + OCTEON_IRQ_PCI_INT0;
1507 }
1508
1509 static void set_cfg_read_retry(u32 retry_cnt)
1510 {
1511 union cvmx_pemx_ctl_status pemx_ctl;
1512 pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));
1513 pemx_ctl.s.cfg_rtry = retry_cnt;
1514 cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64);
1515 }
1516
1517
1518 static u32 disable_cfg_read_retry(void)
1519 {
1520 u32 retry_cnt;
1521
1522 union cvmx_pemx_ctl_status pemx_ctl;
1523 pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));
1524 retry_cnt = pemx_ctl.s.cfg_rtry;
1525 pemx_ctl.s.cfg_rtry = 0;
1526 cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64);
1527 return retry_cnt;
1528 }
1529
1530 static int is_cfg_retry(void)
1531 {
1532 union cvmx_pemx_int_sum pemx_int_sum;
1533 pemx_int_sum.u64 = cvmx_read_csr(CVMX_PEMX_INT_SUM(1));
1534 if (pemx_int_sum.s.crs_dr)
1535 return 1;
1536 return 0;
1537 }
1538
1539 /*
1540 * Read a value from configuration space
1541 *
1542 */
1543 static int octeon_pcie_read_config(unsigned int pcie_port, struct pci_bus *bus,
1544 unsigned int devfn, int reg, int size,
1545 u32 *val)
1546 {
1547 union octeon_cvmemctl cvmmemctl;
1548 union octeon_cvmemctl cvmmemctl_save;
1549 int bus_number = bus->number;
1550 int cfg_retry = 0;
1551 int retry_cnt = 0;
1552 int max_retry_cnt = 10;
1553 u32 cfg_retry_cnt = 0;
1554
1555 cvmmemctl_save.u64 = 0;
1556 BUG_ON(pcie_port >= ARRAY_SIZE(enable_pcie_bus_num_war));
1557 /*
1558 * For the top level bus make sure our hardware bus number
1559 * matches the software one
1560 */
1561 if (bus->parent == NULL) {
1562 if (enable_pcie_bus_num_war[pcie_port])
1563 bus_number = 0;
1564 else {
1565 union cvmx_pciercx_cfg006 pciercx_cfg006;
1566 pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port,
1567 CVMX_PCIERCX_CFG006(pcie_port));
1568 if (pciercx_cfg006.s.pbnum != bus_number) {
1569 pciercx_cfg006.s.pbnum = bus_number;
1570 pciercx_cfg006.s.sbnum = bus_number;
1571 pciercx_cfg006.s.subbnum = bus_number;
1572 cvmx_pcie_cfgx_write(pcie_port,
1573 CVMX_PCIERCX_CFG006(pcie_port),
1574 pciercx_cfg006.u32);
1575 }
1576 }
1577 }
1578
1579 /*
1580 * PCIe only has a single device connected to Octeon. It is
1581 * always device ID 0. Don't bother doing reads for other
1582 * device IDs on the first segment.
1583 */
1584 if ((bus->parent == NULL) && (devfn >> 3 != 0))
1585 return PCIBIOS_FUNC_NOT_SUPPORTED;
1586
1587 /*
1588 * The following is a workaround for the CN57XX, CN56XX,
1589 * CN55XX, and CN54XX errata with PCIe config reads from non
1590 * existent devices. These chips will hang the PCIe link if a
1591 * config read is performed that causes a UR response.
1592 */
1593 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
1594 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1)) {
1595 /*
1596 * For our EBH5600 board, port 0 has a bridge with two
1597 * PCI-X slots. We need a new special checks to make
1598 * sure we only probe valid stuff. The PCIe->PCI-X
1599 * bridge only respondes to device ID 0, function
1600 * 0-1
1601 */
1602 if ((bus->parent == NULL) && (devfn >= 2))
1603 return PCIBIOS_FUNC_NOT_SUPPORTED;
1604 /*
1605 * The PCI-X slots are device ID 2,3. Choose one of
1606 * the below "if" blocks based on what is plugged into
1607 * the board.
1608 */
1609 #if 1
1610 /* Use this option if you aren't using either slot */
1611 if (bus_number == 2)
1612 return PCIBIOS_FUNC_NOT_SUPPORTED;
1613 #elif 0
1614 /*
1615 * Use this option if you are using the first slot but
1616 * not the second.
1617 */
1618 if ((bus_number == 2) && (devfn >> 3 != 2))
1619 return PCIBIOS_FUNC_NOT_SUPPORTED;
1620 #elif 0
1621 /*
1622 * Use this option if you are using the second slot
1623 * but not the first.
1624 */
1625 if ((bus_number == 2) && (devfn >> 3 != 3))
1626 return PCIBIOS_FUNC_NOT_SUPPORTED;
1627 #elif 0
1628 /* Use this opion if you are using both slots */
1629 if ((bus_number == 2) &&
1630 !((devfn == (2 << 3)) || (devfn == (3 << 3))))
1631 return PCIBIOS_FUNC_NOT_SUPPORTED;
1632 #endif
1633
1634 /* The following #if gives a more complicated example. This is
1635 the required checks for running a Nitrox CN16XX-NHBX in the
1636 slot of the EBH5600. This card has a PLX PCIe bridge with
1637 four Nitrox PLX parts behind it */
1638 #if 0
1639 /* PLX bridge with 4 ports */
1640 if ((bus_number == 4) &&
1641 !((devfn >> 3 >= 1) && (devfn >> 3 <= 4)))
1642 return PCIBIOS_FUNC_NOT_SUPPORTED;
1643 /* Nitrox behind PLX 1 */
1644 if ((bus_number == 5) && (devfn >> 3 != 0))
1645 return PCIBIOS_FUNC_NOT_SUPPORTED;
1646 /* Nitrox behind PLX 2 */
1647 if ((bus_number == 6) && (devfn >> 3 != 0))
1648 return PCIBIOS_FUNC_NOT_SUPPORTED;
1649 /* Nitrox behind PLX 3 */
1650 if ((bus_number == 7) && (devfn >> 3 != 0))
1651 return PCIBIOS_FUNC_NOT_SUPPORTED;
1652 /* Nitrox behind PLX 4 */
1653 if ((bus_number == 8) && (devfn >> 3 != 0))
1654 return PCIBIOS_FUNC_NOT_SUPPORTED;
1655 #endif
1656
1657 /*
1658 * Shorten the DID timeout so bus errors for PCIe
1659 * config reads from non existent devices happen
1660 * faster. This allows us to continue booting even if
1661 * the above "if" checks are wrong. Once one of these
1662 * errors happens, the PCIe port is dead.
1663 */
1664 cvmmemctl_save.u64 = __read_64bit_c0_register($11, 7);
1665 cvmmemctl.u64 = cvmmemctl_save.u64;
1666 cvmmemctl.s.didtto = 2;
1667 __write_64bit_c0_register($11, 7, cvmmemctl.u64);
1668 }
1669
1670 if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) && (enable_pcie_14459_war))
1671 cfg_retry_cnt = disable_cfg_read_retry();
1672
1673 pr_debug("pcie_cfg_rd port=%d b=%d devfn=0x%03x reg=0x%03x"
1674 " size=%d ", pcie_port, bus_number, devfn, reg, size);
1675 do {
1676 switch (size) {
1677 case 4:
1678 *val = cvmx_pcie_config_read32(pcie_port, bus_number,
1679 devfn >> 3, devfn & 0x7, reg);
1680 break;
1681 case 2:
1682 *val = cvmx_pcie_config_read16(pcie_port, bus_number,
1683 devfn >> 3, devfn & 0x7, reg);
1684 break;
1685 case 1:
1686 *val = cvmx_pcie_config_read8(pcie_port, bus_number,
1687 devfn >> 3, devfn & 0x7, reg);
1688 break;
1689 default:
1690 if (OCTEON_IS_MODEL(OCTEON_CN63XX))
1691 set_cfg_read_retry(cfg_retry_cnt);
1692 return PCIBIOS_FUNC_NOT_SUPPORTED;
1693 }
1694 if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) &&
1695 (enable_pcie_14459_war)) {
1696 cfg_retry = is_cfg_retry();
1697 retry_cnt++;
1698 if (retry_cnt > max_retry_cnt) {
1699 pr_err(" pcie cfg_read retries failed. retry_cnt=%d\n",
1700 retry_cnt);
1701 cfg_retry = 0;
1702 }
1703 }
1704 } while (cfg_retry);
1705
1706 if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) && (enable_pcie_14459_war))
1707 set_cfg_read_retry(cfg_retry_cnt);
1708 pr_debug("val=%08x : tries=%02d\n", *val, retry_cnt);
1709 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
1710 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1))
1711 write_c0_cvmmemctl(cvmmemctl_save.u64);
1712 return PCIBIOS_SUCCESSFUL;
1713 }
1714
1715 static int octeon_pcie0_read_config(struct pci_bus *bus, unsigned int devfn,
1716 int reg, int size, u32 *val)
1717 {
1718 return octeon_pcie_read_config(0, bus, devfn, reg, size, val);
1719 }
1720
1721 static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn,
1722 int reg, int size, u32 *val)
1723 {
1724 return octeon_pcie_read_config(1, bus, devfn, reg, size, val);
1725 }
1726
1727 static int octeon_dummy_read_config(struct pci_bus *bus, unsigned int devfn,
1728 int reg, int size, u32 *val)
1729 {
1730 return PCIBIOS_FUNC_NOT_SUPPORTED;
1731 }
1732
1733 /*
1734 * Write a value to PCI configuration space
1735 */
1736 static int octeon_pcie_write_config(unsigned int pcie_port, struct pci_bus *bus,
1737 unsigned int devfn, int reg,
1738 int size, u32 val)
1739 {
1740 int bus_number = bus->number;
1741
1742 BUG_ON(pcie_port >= ARRAY_SIZE(enable_pcie_bus_num_war));
1743
1744 if ((bus->parent == NULL) && (enable_pcie_bus_num_war[pcie_port]))
1745 bus_number = 0;
1746
1747 pr_debug("pcie_cfg_wr port=%d b=%d devfn=0x%03x"
1748 " reg=0x%03x size=%d val=%08x\n", pcie_port, bus_number, devfn,
1749 reg, size, val);
1750
1751
1752 switch (size) {
1753 case 4:
1754 cvmx_pcie_config_write32(pcie_port, bus_number, devfn >> 3,
1755 devfn & 0x7, reg, val);
1756 break;
1757 case 2:
1758 cvmx_pcie_config_write16(pcie_port, bus_number, devfn >> 3,
1759 devfn & 0x7, reg, val);
1760 break;
1761 case 1:
1762 cvmx_pcie_config_write8(pcie_port, bus_number, devfn >> 3,
1763 devfn & 0x7, reg, val);
1764 break;
1765 default:
1766 return PCIBIOS_FUNC_NOT_SUPPORTED;
1767 }
1768 return PCIBIOS_SUCCESSFUL;
1769 }
1770
1771 static int octeon_pcie0_write_config(struct pci_bus *bus, unsigned int devfn,
1772 int reg, int size, u32 val)
1773 {
1774 return octeon_pcie_write_config(0, bus, devfn, reg, size, val);
1775 }
1776
1777 static int octeon_pcie1_write_config(struct pci_bus *bus, unsigned int devfn,
1778 int reg, int size, u32 val)
1779 {
1780 return octeon_pcie_write_config(1, bus, devfn, reg, size, val);
1781 }
1782
1783 static int octeon_dummy_write_config(struct pci_bus *bus, unsigned int devfn,
1784 int reg, int size, u32 val)
1785 {
1786 return PCIBIOS_FUNC_NOT_SUPPORTED;
1787 }
1788
1789 static struct pci_ops octeon_pcie0_ops = {
1790 .read = octeon_pcie0_read_config,
1791 .write = octeon_pcie0_write_config,
1792 };
1793
1794 static struct resource octeon_pcie0_mem_resource = {
1795 .name = "Octeon PCIe0 MEM",
1796 .flags = IORESOURCE_MEM,
1797 };
1798
1799 static struct resource octeon_pcie0_io_resource = {
1800 .name = "Octeon PCIe0 IO",
1801 .flags = IORESOURCE_IO,
1802 };
1803
1804 static struct pci_controller octeon_pcie0_controller = {
1805 .pci_ops = &octeon_pcie0_ops,
1806 .mem_resource = &octeon_pcie0_mem_resource,
1807 .io_resource = &octeon_pcie0_io_resource,
1808 };
1809
1810 static struct pci_ops octeon_pcie1_ops = {
1811 .read = octeon_pcie1_read_config,
1812 .write = octeon_pcie1_write_config,
1813 };
1814
1815 static struct resource octeon_pcie1_mem_resource = {
1816 .name = "Octeon PCIe1 MEM",
1817 .flags = IORESOURCE_MEM,
1818 };
1819
1820 static struct resource octeon_pcie1_io_resource = {
1821 .name = "Octeon PCIe1 IO",
1822 .flags = IORESOURCE_IO,
1823 };
1824
1825 static struct pci_controller octeon_pcie1_controller = {
1826 .pci_ops = &octeon_pcie1_ops,
1827 .mem_resource = &octeon_pcie1_mem_resource,
1828 .io_resource = &octeon_pcie1_io_resource,
1829 };
1830
1831 static struct pci_ops octeon_dummy_ops = {
1832 .read = octeon_dummy_read_config,
1833 .write = octeon_dummy_write_config,
1834 };
1835
1836 static struct resource octeon_dummy_mem_resource = {
1837 .name = "Virtual PCIe MEM",
1838 .flags = IORESOURCE_MEM,
1839 };
1840
1841 static struct resource octeon_dummy_io_resource = {
1842 .name = "Virtual PCIe IO",
1843 .flags = IORESOURCE_IO,
1844 };
1845
1846 static struct pci_controller octeon_dummy_controller = {
1847 .pci_ops = &octeon_dummy_ops,
1848 .mem_resource = &octeon_dummy_mem_resource,
1849 .io_resource = &octeon_dummy_io_resource,
1850 };
1851
1852 static int device_needs_bus_num_war(uint32_t deviceid)
1853 {
1854 #define IDT_VENDOR_ID 0x111d
1855
1856 if ((deviceid & 0xffff) == IDT_VENDOR_ID)
1857 return 1;
1858 return 0;
1859 }
1860
1861 /**
1862 * Initialize the Octeon PCIe controllers
1863 *
1864 * Returns
1865 */
1866 static int __init octeon_pcie_setup(void)
1867 {
1868 int result;
1869 int host_mode;
1870 int srio_war15205 = 0, port;
1871 union cvmx_sli_ctl_portx sli_ctl_portx;
1872 union cvmx_sriox_status_reg sriox_status_reg;
1873
1874 /* These chips don't have PCIe */
1875 if (!octeon_has_feature(OCTEON_FEATURE_PCIE))
1876 return 0;
1877
1878 /* No PCIe simulation */
1879 if (octeon_is_simulation())
1880 return 0;
1881
1882 /* Disable PCI if instructed on the command line */
1883 if (pcie_disable)
1884 return 0;
1885
1886 /* Point pcibios_map_irq() to the PCIe version of it */
1887 octeon_pcibios_map_irq = octeon_pcie_pcibios_map_irq;
1888
1889 /*
1890 * PCIe I/O range. It is based on port 0 but includes up until
1891 * port 1's end.
1892 */
1893 set_io_port_base(CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0)));
1894 ioport_resource.start = 0;
1895 ioport_resource.end =
1896 cvmx_pcie_get_io_base_address(1) -
1897 cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1;
1898
1899 /*
1900 * Create a dummy PCIe controller to swallow up bus 0. IDT bridges
1901 * don't work if the primary bus number is zero. Here we add a fake
1902 * PCIe controller that the kernel will give bus 0. This allows
1903 * us to not change the normal kernel bus enumeration
1904 */
1905 octeon_dummy_controller.io_map_base = -1;
1906 octeon_dummy_controller.mem_resource->start = (1ull<<48);
1907 octeon_dummy_controller.mem_resource->end = (1ull<<48);
1908 register_pci_controller(&octeon_dummy_controller);
1909
1910 if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
1911 union cvmx_npei_ctl_status npei_ctl_status;
1912 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
1913 host_mode = npei_ctl_status.s.host_mode;
1914 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
1915 } else {
1916 union cvmx_mio_rst_ctlx mio_rst_ctl;
1917 mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(0));
1918 host_mode = mio_rst_ctl.s.host_mode;
1919 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE2;
1920 }
1921
1922 if (host_mode) {
1923 pr_notice("PCIe: Initializing port 0\n");
1924 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
1925 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
1926 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
1927 sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(0));
1928 if (sriox_status_reg.s.srio) {
1929 srio_war15205 += 1; /* Port is SRIO */
1930 port = 0;
1931 }
1932 }
1933 result = cvmx_pcie_rc_initialize(0);
1934 if (result == 0) {
1935 uint32_t device0;
1936 /* Memory offsets are physical addresses */
1937 octeon_pcie0_controller.mem_offset =
1938 cvmx_pcie_get_mem_base_address(0);
1939 /* IO offsets are Mips virtual addresses */
1940 octeon_pcie0_controller.io_map_base =
1941 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address
1942 (0));
1943 octeon_pcie0_controller.io_offset = 0;
1944 /*
1945 * To keep things similar to PCI, we start
1946 * device addresses at the same place as PCI
1947 * uisng big bar support. This normally
1948 * translates to 4GB-256MB, which is the same
1949 * as most x86 PCs.
1950 */
1951 octeon_pcie0_controller.mem_resource->start =
1952 cvmx_pcie_get_mem_base_address(0) +
1953 (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
1954 octeon_pcie0_controller.mem_resource->end =
1955 cvmx_pcie_get_mem_base_address(0) +
1956 cvmx_pcie_get_mem_size(0) - 1;
1957 /*
1958 * Ports must be above 16KB for the ISA bus
1959 * filtering in the PCI-X to PCI bridge.
1960 */
1961 octeon_pcie0_controller.io_resource->start = 4 << 10;
1962 octeon_pcie0_controller.io_resource->end =
1963 cvmx_pcie_get_io_size(0) - 1;
1964 msleep(100); /* Some devices need extra time */
1965 register_pci_controller(&octeon_pcie0_controller);
1966 device0 = cvmx_pcie_config_read32(0, 0, 0, 0, 0);
1967 enable_pcie_bus_num_war[0] =
1968 device_needs_bus_num_war(device0);
1969 }
1970 } else {
1971 pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n");
1972 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
1973 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
1974 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
1975 srio_war15205 += 1;
1976 port = 0;
1977 }
1978 }
1979
1980 if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
1981 host_mode = 1;
1982 /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
1983 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
1984 union cvmx_npei_dbg_data dbg_data;
1985 dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1986 if (dbg_data.cn52xx.qlm0_link_width)
1987 host_mode = 0;
1988 }
1989 } else {
1990 union cvmx_mio_rst_ctlx mio_rst_ctl;
1991 mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(1));
1992 host_mode = mio_rst_ctl.s.host_mode;
1993 }
1994
1995 if (host_mode) {
1996 pr_notice("PCIe: Initializing port 1\n");
1997 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
1998 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
1999 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
2000 sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(1));
2001 if (sriox_status_reg.s.srio) {
2002 srio_war15205 += 1; /* Port is SRIO */
2003 port = 1;
2004 }
2005 }
2006 result = cvmx_pcie_rc_initialize(1);
2007 if (result == 0) {
2008 uint32_t device0;
2009 /* Memory offsets are physical addresses */
2010 octeon_pcie1_controller.mem_offset =
2011 cvmx_pcie_get_mem_base_address(1);
2012 /*
2013 * To calculate the address for accessing the 2nd PCIe device,
2014 * either 'io_map_base' (pci_iomap()), or 'mips_io_port_base'
2015 * (ioport_map()) value is added to
2016 * pci_resource_start(dev,bar)). The 'mips_io_port_base' is set
2017 * only once based on first PCIe. Also changing 'io_map_base'
2018 * based on first slot's value so that both the routines will
2019 * work properly.
2020 */
2021 octeon_pcie1_controller.io_map_base =
2022 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0));
2023 /* IO offsets are Mips virtual addresses */
2024 octeon_pcie1_controller.io_offset =
2025 cvmx_pcie_get_io_base_address(1) -
2026 cvmx_pcie_get_io_base_address(0);
2027 /*
2028 * To keep things similar to PCI, we start device
2029 * addresses at the same place as PCI uisng big bar
2030 * support. This normally translates to 4GB-256MB,
2031 * which is the same as most x86 PCs.
2032 */
2033 octeon_pcie1_controller.mem_resource->start =
2034 cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
2035 (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
2036 octeon_pcie1_controller.mem_resource->end =
2037 cvmx_pcie_get_mem_base_address(1) +
2038 cvmx_pcie_get_mem_size(1) - 1;
2039 /*
2040 * Ports must be above 16KB for the ISA bus filtering
2041 * in the PCI-X to PCI bridge.
2042 */
2043 octeon_pcie1_controller.io_resource->start =
2044 cvmx_pcie_get_io_base_address(1) -
2045 cvmx_pcie_get_io_base_address(0);
2046 octeon_pcie1_controller.io_resource->end =
2047 octeon_pcie1_controller.io_resource->start +
2048 cvmx_pcie_get_io_size(1) - 1;
2049 msleep(100); /* Some devices need extra time */
2050 register_pci_controller(&octeon_pcie1_controller);
2051 device0 = cvmx_pcie_config_read32(1, 0, 0, 0, 0);
2052 enable_pcie_bus_num_war[1] =
2053 device_needs_bus_num_war(device0);
2054 }
2055 } else {
2056 pr_notice("PCIe: Port 1 not in root complex mode, skipping.\n");
2057 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
2058 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
2059 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
2060 srio_war15205 += 1;
2061 port = 1;
2062 }
2063 }
2064
2065 /*
2066 * CN63XX pass 1_x/2.0 errata PCIe-15205 requires setting all
2067 * of SRIO MACs SLI_CTL_PORT*[INT*_MAP] to similar value and
2068 * all of PCIe Macs SLI_CTL_PORT*[INT*_MAP] to different value
2069 * from the previous set values
2070 */
2071 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
2072 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
2073 if (srio_war15205 == 1) {
2074 sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(port));
2075 sli_ctl_portx.s.inta_map = 1;
2076 sli_ctl_portx.s.intb_map = 1;
2077 sli_ctl_portx.s.intc_map = 1;
2078 sli_ctl_portx.s.intd_map = 1;
2079 cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(port), sli_ctl_portx.u64);
2080
2081 sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(!port));
2082 sli_ctl_portx.s.inta_map = 0;
2083 sli_ctl_portx.s.intb_map = 0;
2084 sli_ctl_portx.s.intc_map = 0;
2085 sli_ctl_portx.s.intd_map = 0;
2086 cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(!port), sli_ctl_portx.u64);
2087 }
2088 }
2089
2090 octeon_pci_dma_init();
2091
2092 return 0;
2093 }
2094 arch_initcall(octeon_pcie_setup);
2095
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