1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 Altera Corporation. All rights reserved.
4 */
5
6 /dts-v1/;
7
8 / {
9 model = "Altera NiosII Max10";
10 compatible = "altr,niosii-max10";
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu: cpu@0 {
19 device_type = "cpu";
20 compatible = "altr,nios2-1.1";
21 reg = <0x00000000>;
22 interrupt-controller;
23 #interrupt-cells = <1>;
24 altr,exception-addr = <0xc8000120>;
25 altr,fast-tlb-miss-addr = <0xc0000100>;
26 altr,has-div = <1>;
27 altr,has-initda = <1>;
28 altr,has-mmu = <1>;
29 altr,has-mul = <1>;
30 altr,implementation = "fast";
31 altr,pid-num-bits = <8>;
32 altr,reset-addr = <0xd4000000>;
33 altr,tlb-num-entries = <256>;
34 altr,tlb-num-ways = <16>;
35 altr,tlb-ptr-sz = <8>;
36 clock-frequency = <75000000>;
37 dcache-line-size = <32>;
38 dcache-size = <32768>;
39 icache-line-size = <32>;
40 icache-size = <32768>;
41 };
42 };
43
44 memory {
45 device_type = "memory";
46 reg = <0x08000000 0x08000000>,
47 <0x00000000 0x00000400>;
48 };
49
50 sopc0: sopc@0 {
51 device_type = "soc";
52 ranges;
53 #address-cells = <1>;
54 #size-cells = <1>;
55 compatible = "altr,avalon", "simple-bus";
56 bus-frequency = <75000000>;
57
58 jtag_uart: serial@18001530 {
59 compatible = "altr,juart-1.0";
60 reg = <0x18001530 0x00000008>;
61 interrupt-parent = <&cpu>;
62 interrupts = <7>;
63 };
64
65 a_16550_uart_0: serial@18001600 {
66 compatible = "altr,16550-FIFO32", "ns16550a";
67 reg = <0x18001600 0x00000200>;
68 interrupt-parent = <&cpu>;
69 interrupts = <1>;
70 auto-flow-control = <1>;
71 clock-frequency = <50000000>;
72 fifo-size = <32>;
73 reg-io-width = <4>;
74 reg-shift = <2>;
75 tx-threshold = <16>;
76 };
77
78 sysid: sysid@18001528 {
79 compatible = "altr,sysid-1.0";
80 reg = <0x18001528 0x00000008>;
81 id = <4207856382>;
82 timestamp = <1431309290>;
83 };
84
85 rgmii_0_eth_tse_0: ethernet@400 {
86 compatible = "altr,tse-msgdma-1.0", "altr,tse-1.0";
87 reg = <0x00000400 0x00000400>,
88 <0x00000820 0x00000020>,
89 <0x00000800 0x00000020>,
90 <0x000008c0 0x00000008>,
91 <0x00000840 0x00000020>,
92 <0x00000860 0x00000020>;
93 reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc";
94 interrupt-parent = <&cpu>;
95 interrupts = <2 3>;
96 interrupt-names = "rx_irq", "tx_irq";
97 rx-fifo-depth = <8192>;
98 tx-fifo-depth = <8192>;
99 address-bits = <48>;
100 max-frame-size = <1500>;
101 local-mac-address = [00 00 00 00 00 00];
102 altr,has-supplementary-unicast;
103 altr,enable-sup-addr = <1>;
104 altr,has-hash-multicast-filter;
105 altr,enable-hash = <1>;
106 phy-mode = "rgmii-id";
107 phy-handle = <&phy0>;
108 rgmii_0_eth_tse_0_mdio: mdio {
109 compatible = "altr,tse-mdio";
110 #address-cells = <1>;
111 #size-cells = <0>;
112 phy0: ethernet-phy@0 {
113 reg = <0>;
114 device_type = "ethernet-phy";
115 };
116 };
117 };
118
119 enet_pll: clock@0 {
120 compatible = "altr,pll-1.0";
121 #clock-cells = <1>;
122
123 enet_pll_c0: enet_pll_c0 {
124 compatible = "fixed-clock";
125 #clock-cells = <0>;
126 clock-frequency = <125000000>;
127 clock-output-names = "enet_pll-c0";
128 };
129
130 enet_pll_c1: enet_pll_c1 {
131 compatible = "fixed-clock";
132 #clock-cells = <0>;
133 clock-frequency = <25000000>;
134 clock-output-names = "enet_pll-c1";
135 };
136
137 enet_pll_c2: enet_pll_c2 {
138 compatible = "fixed-clock";
139 #clock-cells = <0>;
140 clock-frequency = <2500000>;
141 clock-output-names = "enet_pll-c2";
142 };
143 };
144
145 sys_pll: clock@1 {
146 compatible = "altr,pll-1.0";
147 #clock-cells = <1>;
148
149 sys_pll_c0: sys_pll_c0 {
150 compatible = "fixed-clock";
151 #clock-cells = <0>;
152 clock-frequency = <100000000>;
153 clock-output-names = "sys_pll-c0";
154 };
155
156 sys_pll_c1: sys_pll_c1 {
157 compatible = "fixed-clock";
158 #clock-cells = <0>;
159 clock-frequency = <50000000>;
160 clock-output-names = "sys_pll-c1";
161 };
162
163 sys_pll_c2: sys_pll_c2 {
164 compatible = "fixed-clock";
165 #clock-cells = <0>;
166 clock-frequency = <75000000>;
167 clock-output-names = "sys_pll-c2";
168 };
169 };
170
171 sys_clk_timer: timer@18001440 {
172 compatible = "altr,timer-1.0";
173 reg = <0x18001440 0x00000020>;
174 interrupt-parent = <&cpu>;
175 interrupts = <0>;
176 clock-frequency = <75000000>;
177 };
178
179 led_pio: gpio@180014d0 {
180 compatible = "altr,pio-1.0";
181 reg = <0x180014d0 0x00000010>;
182 altr,ngpio = <4>;
183 #gpio-cells = <2>;
184 gpio-controller;
185 };
186
187 button_pio: gpio@180014c0 {
188 compatible = "altr,pio-1.0";
189 reg = <0x180014c0 0x00000010>;
190 interrupt-parent = <&cpu>;
191 interrupts = <6>;
192 altr,ngpio = <3>;
193 altr,interrupt-type = <2>;
194 edge_type = <1>;
195 level_trigger = <0>;
196 #gpio-cells = <2>;
197 gpio-controller;
198 };
199
200 sys_clk_timer_1: timer@880 {
201 compatible = "altr,timer-1.0";
202 reg = <0x00000880 0x00000020>;
203 interrupt-parent = <&cpu>;
204 interrupts = <5>;
205 clock-frequency = <75000000>;
206 };
207
208 fpga_leds: leds {
209 compatible = "gpio-leds";
210
211 led_fpga0: fpga0 {
212 label = "fpga_led0";
213 gpios = <&led_pio 0 1>;
214 };
215
216 led_fpga1: fpga1 {
217 label = "fpga_led1";
218 gpios = <&led_pio 1 1>;
219 };
220
221 led_fpga2: fpga2 {
222 label = "fpga_led2";
223 gpios = <&led_pio 2 1>;
224 };
225
226 led_fpga3: fpga3 {
227 label = "fpga_led3";
228 gpios = <&led_pio 3 1>;
229 };
230 };
231 };
232
233 chosen {
234 bootargs = "debug earlycon console=ttyS0,115200";
235 stdout-path = &a_16550_uart_0;
236 };
237 };
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