1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * include/asm-parisc/cache.h
4 */
5
6 #ifndef __ARCH_PARISC_CACHE_H
7 #define __ARCH_PARISC_CACHE_H
8
9 #include <asm/alternative.h>
10
11 /*
12 * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors
13 * have 32-byte cachelines. The L1 length appears to be 16 bytes but this
14 * is not clearly documented.
15 */
16 #define L1_CACHE_BYTES 16
17 #define L1_CACHE_SHIFT 4
18
19 #ifndef __ASSEMBLY__
20
21 #define SMP_CACHE_BYTES L1_CACHE_BYTES
22
23 #ifdef CONFIG_PA20
24 #define ARCH_DMA_MINALIGN 128
25 #else
26 #define ARCH_DMA_MINALIGN 32
27 #endif
28 #define ARCH_KMALLOC_MINALIGN 16 /* ldcw requires 16-byte alignment */
29
30 #define arch_slab_minalign() ((unsigned)dcache_stride)
31 #define cache_line_size() dcache_stride
32 #define dma_get_cache_alignment cache_line_size
33
34 #define __read_mostly __section(".data..read_mostly")
35
36 void parisc_cache_init(void); /* initializes cache-flushing */
37 void disable_sr_hashing_asm(int); /* low level support for above */
38 void disable_sr_hashing(void); /* turns off space register hashing */
39 void free_sid(unsigned long);
40 unsigned long alloc_sid(void);
41
42 struct seq_file;
43 extern void show_cache_info(struct seq_file *m);
44
45 extern int split_tlb;
46 extern int dcache_stride;
47 extern int icache_stride;
48 extern struct pdc_cache_info cache_info;
49 extern struct pdc_btlb_info btlb_info;
50 void parisc_setup_cache_timing(void);
51
52 #define pdtlb(sr, addr) asm volatile("pdtlb 0(%%sr%0,%1)" \
53 ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
54 : : "i"(sr), "r" (addr) : "memory")
55 #define pitlb(sr, addr) asm volatile("pitlb 0(%%sr%0,%1)" \
56 ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
57 ALTERNATIVE(ALT_COND_NO_SPLIT_TLB, INSN_NOP) \
58 : : "i"(sr), "r" (addr) : "memory")
59
60 #define asm_io_fdc(addr) asm volatile("fdc %%r0(%0)" \
61 ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
62 ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) \
63 : : "r" (addr) : "memory")
64 #define asm_io_sync() asm volatile("sync" \
65 ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
66 ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) :::"memory")
67 #define asm_syncdma() asm volatile("syncdma" :::"memory")
68
69 #endif /* ! __ASSEMBLY__ */
70
71 /* Classes of processor wrt: disabling space register hashing */
72
73 #define SRHASH_PCXST 0 /* pcxs, pcxt, pcxt_ */
74 #define SRHASH_PCXL 1 /* pcxl */
75 #define SRHASH_PA20 2 /* pcxu, pcxu_, pcxw, pcxw_ */
76
77 #endif
78
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