1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _PARISC_SUPERIO_H
3 #define _PARISC_SUPERIO_H
4
5 #define IC_PIC1 0x20 /* PCI I/O address of master 8259 */
6 #define IC_PIC2 0xA0 /* PCI I/O address of slave */
7
8 /* Config Space Offsets to configuration and base address registers */
9 #define SIO_CR 0x5A /* Configuration Register */
10 #define SIO_ACPIBAR 0x88 /* ACPI BAR */
11 #define SIO_FDCBAR 0x90 /* Floppy Disk Controller BAR */
12 #define SIO_SP1BAR 0x94 /* Serial 1 BAR */
13 #define SIO_SP2BAR 0x98 /* Serial 2 BAR */
14 #define SIO_PPBAR 0x9C /* Parallel BAR */
15
16 #define TRIGGER_1 0x67 /* Edge/level trigger register 1 */
17 #define TRIGGER_2 0x68 /* Edge/level trigger register 2 */
18
19 /* Interrupt Routing Control registers */
20 #define CFG_IR_SER 0x69 /* Serial 1 [0:3] and Serial 2 [4:7] */
21 #define CFG_IR_PFD 0x6a /* Parallel [0:3] and Floppy [4:7] */
22 #define CFG_IR_IDE 0x6b /* IDE1 [0:3] and IDE2 [4:7] */
23 #define CFG_IR_INTAB 0x6c /* PCI INTA [0:3] and INT B [4:7] */
24 #define CFG_IR_INTCD 0x6d /* PCI INTC [0:3] and INT D [4:7] */
25 #define CFG_IR_PS2 0x6e /* PS/2 KBINT [0:3] and Mouse [4:7] */
26 #define CFG_IR_FXBUS 0x6f /* FXIRQ[0] [0:3] and FXIRQ[1] [4:7] */
27 #define CFG_IR_USB 0x70 /* FXIRQ[2] [0:3] and USB [4:7] */
28 #define CFG_IR_ACPI 0x71 /* ACPI SCI [0:3] and reserved [4:7] */
29
30 #define CFG_IR_LOW CFG_IR_SER /* Lowest interrupt routing reg */
31 #define CFG_IR_HIGH CFG_IR_ACPI /* Highest interrupt routing reg */
32
33 /* 8259 operational control words */
34 #define OCW2_EOI 0x20 /* Non-specific EOI */
35 #define OCW2_SEOI 0x60 /* Specific EOI */
36 #define OCW3_IIR 0x0A /* Read request register */
37 #define OCW3_ISR 0x0B /* Read service register */
38 #define OCW3_POLL 0x0C /* Poll the PIC for an interrupt vector */
39
40 /* Interrupt lines. Only PIC1 is used */
41 #define USB_IRQ 1 /* USB */
42 #define SP1_IRQ 3 /* Serial port 1 */
43 #define SP2_IRQ 4 /* Serial port 2 */
44 #define PAR_IRQ 5 /* Parallel port */
45 #define FDC_IRQ 6 /* Floppy controller */
46 #define IDE_IRQ 7 /* IDE (pri+sec) */
47
48 /* ACPI registers */
49 #define USB_REG_CR 0x1f /* USB Regulator Control Register */
50
51 #define SUPERIO_NIRQS 8
52
53 struct superio_device {
54 u32 fdc_base;
55 u32 sp1_base;
56 u32 sp2_base;
57 u32 pp_base;
58 u32 acpi_base;
59 int suckyio_irq_enabled;
60 struct pci_dev *lio_pdev; /* pci device for legacy IO (fn 1) */
61 struct pci_dev *usb_pdev; /* pci device for USB (fn 2) */
62 };
63
64 /*
65 * Does NS make a 87415 based plug in PCI card? If so, because of this
66 * macro we currently don't support it being plugged into a machine
67 * that contains a SuperIO chip AND has CONFIG_SUPERIO enabled.
68 *
69 * This could be fixed by checking to see if function 1 exists, and
70 * if it is SuperIO Legacy IO; but really now, is this combination
71 * going to EVER happen?
72 */
73
74 #define SUPERIO_IDE_FN 0 /* Function number of IDE controller */
75 #define SUPERIO_LIO_FN 1 /* Function number of Legacy IO controller */
76 #define SUPERIO_USB_FN 2 /* Function number of USB controller */
77
78 #define is_superio_device(x) \
79 (((x)->vendor == PCI_VENDOR_ID_NS) && \
80 ( ((x)->device == PCI_DEVICE_ID_NS_87415) \
81 || ((x)->device == PCI_DEVICE_ID_NS_87560_LIO) \
82 || ((x)->device == PCI_DEVICE_ID_NS_87560_USB) ) )
83
84 extern int superio_fixup_irq(struct pci_dev *pcidev); /* called by iosapic */
85
86 #endif /* _PARISC_SUPERIO_H */
87
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