1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Unaligned memory access handler
4 *
5 * Copyright (C) 2001 Randolph Chung <tausq@debian.org>
6 * Copyright (C) 2022 Helge Deller <deller@gmx.de>
7 * Significantly tweaked by LaMont Jones <lamont@debian.org>
8 */
9
10 #include <linux/sched/signal.h>
11 #include <linux/signal.h>
12 #include <linux/ratelimit.h>
13 #include <linux/uaccess.h>
14 #include <linux/sysctl.h>
15 #include <asm/unaligned.h>
16 #include <asm/hardirq.h>
17 #include <asm/traps.h>
18
19 /* #define DEBUG_UNALIGNED 1 */
20
21 #ifdef DEBUG_UNALIGNED
22 #define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __func__ ); printk(KERN_DEBUG fmt, ##args ); } while (0)
23 #else
24 #define DPRINTF(fmt, args...)
25 #endif
26
27 #define RFMT "%#08lx"
28
29 /* 1111 1100 0000 0000 0001 0011 1100 0000 */
30 #define OPCODE1(a,b,c) ((a)<<26|(b)<<12|(c)<<6)
31 #define OPCODE2(a,b) ((a)<<26|(b)<<1)
32 #define OPCODE3(a,b) ((a)<<26|(b)<<2)
33 #define OPCODE4(a) ((a)<<26)
34 #define OPCODE1_MASK OPCODE1(0x3f,1,0xf)
35 #define OPCODE2_MASK OPCODE2(0x3f,1)
36 #define OPCODE3_MASK OPCODE3(0x3f,1)
37 #define OPCODE4_MASK OPCODE4(0x3f)
38
39 /* skip LDB - never unaligned (index) */
40 #define OPCODE_LDH_I OPCODE1(0x03,0,0x1)
41 #define OPCODE_LDW_I OPCODE1(0x03,0,0x2)
42 #define OPCODE_LDD_I OPCODE1(0x03,0,0x3)
43 #define OPCODE_LDDA_I OPCODE1(0x03,0,0x4)
44 #define OPCODE_LDCD_I OPCODE1(0x03,0,0x5)
45 #define OPCODE_LDWA_I OPCODE1(0x03,0,0x6)
46 #define OPCODE_LDCW_I OPCODE1(0x03,0,0x7)
47 /* skip LDB - never unaligned (short) */
48 #define OPCODE_LDH_S OPCODE1(0x03,1,0x1)
49 #define OPCODE_LDW_S OPCODE1(0x03,1,0x2)
50 #define OPCODE_LDD_S OPCODE1(0x03,1,0x3)
51 #define OPCODE_LDDA_S OPCODE1(0x03,1,0x4)
52 #define OPCODE_LDCD_S OPCODE1(0x03,1,0x5)
53 #define OPCODE_LDWA_S OPCODE1(0x03,1,0x6)
54 #define OPCODE_LDCW_S OPCODE1(0x03,1,0x7)
55 /* skip STB - never unaligned */
56 #define OPCODE_STH OPCODE1(0x03,1,0x9)
57 #define OPCODE_STW OPCODE1(0x03,1,0xa)
58 #define OPCODE_STD OPCODE1(0x03,1,0xb)
59 /* skip STBY - never unaligned */
60 /* skip STDBY - never unaligned */
61 #define OPCODE_STWA OPCODE1(0x03,1,0xe)
62 #define OPCODE_STDA OPCODE1(0x03,1,0xf)
63
64 #define OPCODE_FLDWX OPCODE1(0x09,0,0x0)
65 #define OPCODE_FLDWXR OPCODE1(0x09,0,0x1)
66 #define OPCODE_FSTWX OPCODE1(0x09,0,0x8)
67 #define OPCODE_FSTWXR OPCODE1(0x09,0,0x9)
68 #define OPCODE_FLDWS OPCODE1(0x09,1,0x0)
69 #define OPCODE_FLDWSR OPCODE1(0x09,1,0x1)
70 #define OPCODE_FSTWS OPCODE1(0x09,1,0x8)
71 #define OPCODE_FSTWSR OPCODE1(0x09,1,0x9)
72 #define OPCODE_FLDDX OPCODE1(0x0b,0,0x0)
73 #define OPCODE_FSTDX OPCODE1(0x0b,0,0x8)
74 #define OPCODE_FLDDS OPCODE1(0x0b,1,0x0)
75 #define OPCODE_FSTDS OPCODE1(0x0b,1,0x8)
76
77 #define OPCODE_LDD_L OPCODE2(0x14,0)
78 #define OPCODE_FLDD_L OPCODE2(0x14,1)
79 #define OPCODE_STD_L OPCODE2(0x1c,0)
80 #define OPCODE_FSTD_L OPCODE2(0x1c,1)
81
82 #define OPCODE_LDW_M OPCODE3(0x17,1)
83 #define OPCODE_FLDW_L OPCODE3(0x17,0)
84 #define OPCODE_FSTW_L OPCODE3(0x1f,0)
85 #define OPCODE_STW_M OPCODE3(0x1f,1)
86
87 #define OPCODE_LDH_L OPCODE4(0x11)
88 #define OPCODE_LDW_L OPCODE4(0x12)
89 #define OPCODE_LDWM OPCODE4(0x13)
90 #define OPCODE_STH_L OPCODE4(0x19)
91 #define OPCODE_STW_L OPCODE4(0x1A)
92 #define OPCODE_STWM OPCODE4(0x1B)
93
94 #define MAJOR_OP(i) (((i)>>26)&0x3f)
95 #define R1(i) (((i)>>21)&0x1f)
96 #define R2(i) (((i)>>16)&0x1f)
97 #define R3(i) ((i)&0x1f)
98 #define FR3(i) ((((i)&0x1f)<<1)|(((i)>>6)&1))
99 #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))
100 #define IM5_2(i) IM((i)>>16,5)
101 #define IM5_3(i) IM((i),5)
102 #define IM14(i) IM((i),14)
103
104 #define ERR_NOTHANDLED -1
105
106 int unaligned_enabled __read_mostly = 1;
107 int no_unaligned_warning __read_mostly;
108
109 static int emulate_ldh(struct pt_regs *regs, int toreg)
110 {
111 unsigned long saddr = regs->ior;
112 unsigned long val = 0, temp1;
113 ASM_EXCEPTIONTABLE_VAR(ret);
114
115 DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n",
116 regs->isr, regs->ior, toreg);
117
118 __asm__ __volatile__ (
119 " mtsp %4, %%sr1\n"
120 "1: ldbs 0(%%sr1,%3), %2\n"
121 "2: ldbs 1(%%sr1,%3), %0\n"
122 " depw %2, 23, 24, %0\n"
123 "3: \n"
124 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
125 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
126 : "+r" (val), "+r" (ret), "=&r" (temp1)
127 : "r" (saddr), "r" (regs->isr) );
128
129 DPRINTF("val = " RFMT "\n", val);
130
131 if (toreg)
132 regs->gr[toreg] = val;
133
134 return ret;
135 }
136
137 static int emulate_ldw(struct pt_regs *regs, int toreg, int flop)
138 {
139 unsigned long saddr = regs->ior;
140 unsigned long val = 0, temp1, temp2;
141 ASM_EXCEPTIONTABLE_VAR(ret);
142
143 DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n",
144 regs->isr, regs->ior, toreg);
145
146 __asm__ __volatile__ (
147 " zdep %4,28,2,%2\n" /* r19=(ofs&3)*8 */
148 " mtsp %5, %%sr1\n"
149 " depw %%r0,31,2,%4\n"
150 "1: ldw 0(%%sr1,%4),%0\n"
151 "2: ldw 4(%%sr1,%4),%3\n"
152 " subi 32,%2,%2\n"
153 " mtctl %2,11\n"
154 " vshd %0,%3,%0\n"
155 "3: \n"
156 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
157 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
158 : "+r" (val), "+r" (ret), "=&r" (temp1), "=&r" (temp2)
159 : "r" (saddr), "r" (regs->isr) );
160
161 DPRINTF("val = " RFMT "\n", val);
162
163 if (flop)
164 ((__u32*)(regs->fr))[toreg] = val;
165 else if (toreg)
166 regs->gr[toreg] = val;
167
168 return ret;
169 }
170 static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
171 {
172 unsigned long saddr = regs->ior;
173 unsigned long shift, temp1;
174 __u64 val = 0;
175 ASM_EXCEPTIONTABLE_VAR(ret);
176
177 DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n",
178 regs->isr, regs->ior, toreg);
179
180 if (!IS_ENABLED(CONFIG_64BIT) && !flop)
181 return ERR_NOTHANDLED;
182
183 #ifdef CONFIG_64BIT
184 __asm__ __volatile__ (
185 " depd,z %2,60,3,%3\n" /* shift=(ofs&7)*8 */
186 " mtsp %5, %%sr1\n"
187 " depd %%r0,63,3,%2\n"
188 "1: ldd 0(%%sr1,%2),%0\n"
189 "2: ldd 8(%%sr1,%2),%4\n"
190 " subi 64,%3,%3\n"
191 " mtsar %3\n"
192 " shrpd %0,%4,%%sar,%0\n"
193 "3: \n"
194 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
195 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
196 : "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1)
197 : "r" (regs->isr) );
198 #else
199 __asm__ __volatile__ (
200 " zdep %2,29,2,%3\n" /* shift=(ofs&3)*8 */
201 " mtsp %5, %%sr1\n"
202 " dep %%r0,31,2,%2\n"
203 "1: ldw 0(%%sr1,%2),%0\n"
204 "2: ldw 4(%%sr1,%2),%R0\n"
205 "3: ldw 8(%%sr1,%2),%4\n"
206 " subi 32,%3,%3\n"
207 " mtsar %3\n"
208 " vshd %0,%R0,%0\n"
209 " vshd %R0,%4,%R0\n"
210 "4: \n"
211 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 4b, "%1")
212 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 4b, "%1")
213 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 4b, "%1")
214 : "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1)
215 : "r" (regs->isr) );
216 #endif
217
218 DPRINTF("val = 0x%llx\n", val);
219
220 if (flop)
221 regs->fr[toreg] = val;
222 else if (toreg)
223 regs->gr[toreg] = val;
224
225 return ret;
226 }
227
228 static int emulate_sth(struct pt_regs *regs, int frreg)
229 {
230 unsigned long val = regs->gr[frreg], temp1;
231 ASM_EXCEPTIONTABLE_VAR(ret);
232
233 if (!frreg)
234 val = 0;
235
236 DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg,
237 val, regs->isr, regs->ior);
238
239 __asm__ __volatile__ (
240 " mtsp %4, %%sr1\n"
241 " extrw,u %2, 23, 8, %1\n"
242 "1: stb %1, 0(%%sr1, %3)\n"
243 "2: stb %2, 1(%%sr1, %3)\n"
244 "3: \n"
245 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0")
246 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0")
247 : "+r" (ret), "=&r" (temp1)
248 : "r" (val), "r" (regs->ior), "r" (regs->isr) );
249
250 return ret;
251 }
252
253 static int emulate_stw(struct pt_regs *regs, int frreg, int flop)
254 {
255 unsigned long val;
256 ASM_EXCEPTIONTABLE_VAR(ret);
257
258 if (flop)
259 val = ((__u32*)(regs->fr))[frreg];
260 else if (frreg)
261 val = regs->gr[frreg];
262 else
263 val = 0;
264
265 DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg,
266 val, regs->isr, regs->ior);
267
268
269 __asm__ __volatile__ (
270 " mtsp %3, %%sr1\n"
271 " zdep %2, 28, 2, %%r19\n"
272 " dep %%r0, 31, 2, %2\n"
273 " mtsar %%r19\n"
274 " depwi,z -2, %%sar, 32, %%r19\n"
275 "1: ldw 0(%%sr1,%2),%%r20\n"
276 "2: ldw 4(%%sr1,%2),%%r21\n"
277 " vshd %%r0, %1, %%r22\n"
278 " vshd %1, %%r0, %%r1\n"
279 " and %%r20, %%r19, %%r20\n"
280 " andcm %%r21, %%r19, %%r21\n"
281 " or %%r22, %%r20, %%r20\n"
282 " or %%r1, %%r21, %%r21\n"
283 " stw %%r20,0(%%sr1,%2)\n"
284 " stw %%r21,4(%%sr1,%2)\n"
285 "3: \n"
286 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0")
287 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0")
288 : "+r" (ret)
289 : "r" (val), "r" (regs->ior), "r" (regs->isr)
290 : "r19", "r20", "r21", "r22", "r1" );
291
292 return ret;
293 }
294 static int emulate_std(struct pt_regs *regs, int frreg, int flop)
295 {
296 __u64 val;
297 ASM_EXCEPTIONTABLE_VAR(ret);
298
299 if (flop)
300 val = regs->fr[frreg];
301 else if (frreg)
302 val = regs->gr[frreg];
303 else
304 val = 0;
305
306 DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg,
307 val, regs->isr, regs->ior);
308
309 if (!IS_ENABLED(CONFIG_64BIT) && !flop)
310 return ERR_NOTHANDLED;
311
312 #ifdef CONFIG_64BIT
313 __asm__ __volatile__ (
314 " mtsp %3, %%sr1\n"
315 " depd,z %2, 60, 3, %%r19\n"
316 " depd %%r0, 63, 3, %2\n"
317 " mtsar %%r19\n"
318 " depdi,z -2, %%sar, 64, %%r19\n"
319 "1: ldd 0(%%sr1,%2),%%r20\n"
320 "2: ldd 8(%%sr1,%2),%%r21\n"
321 " shrpd %%r0, %1, %%sar, %%r22\n"
322 " shrpd %1, %%r0, %%sar, %%r1\n"
323 " and %%r20, %%r19, %%r20\n"
324 " andcm %%r21, %%r19, %%r21\n"
325 " or %%r22, %%r20, %%r20\n"
326 " or %%r1, %%r21, %%r21\n"
327 "3: std %%r20,0(%%sr1,%2)\n"
328 "4: std %%r21,8(%%sr1,%2)\n"
329 "5: \n"
330 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 5b, "%0")
331 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 5b, "%0")
332 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 5b, "%0")
333 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 5b, "%0")
334 : "+r" (ret)
335 : "r" (val), "r" (regs->ior), "r" (regs->isr)
336 : "r19", "r20", "r21", "r22", "r1" );
337 #else
338 {
339 __asm__ __volatile__ (
340 " mtsp %3, %%sr1\n"
341 " zdep %R1, 29, 2, %%r19\n"
342 " dep %%r0, 31, 2, %2\n"
343 " mtsar %%r19\n"
344 " zvdepi -2, 32, %%r19\n"
345 "1: ldw 0(%%sr1,%2),%%r20\n"
346 "2: ldw 8(%%sr1,%2),%%r21\n"
347 " vshd %1, %R1, %%r1\n"
348 " vshd %%r0, %1, %1\n"
349 " vshd %R1, %%r0, %R1\n"
350 " and %%r20, %%r19, %%r20\n"
351 " andcm %%r21, %%r19, %%r21\n"
352 " or %1, %%r20, %1\n"
353 " or %R1, %%r21, %R1\n"
354 "3: stw %1,0(%%sr1,%2)\n"
355 "4: stw %%r1,4(%%sr1,%2)\n"
356 "5: stw %R1,8(%%sr1,%2)\n"
357 "6: \n"
358 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 6b, "%0")
359 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 6b, "%0")
360 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 6b, "%0")
361 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 6b, "%0")
362 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(5b, 6b, "%0")
363 : "+r" (ret)
364 : "r" (val), "r" (regs->ior), "r" (regs->isr)
365 : "r19", "r20", "r21", "r1" );
366 }
367 #endif
368
369 return ret;
370 }
371
372 void handle_unaligned(struct pt_regs *regs)
373 {
374 static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
375 unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0;
376 int modify = 0;
377 int ret = ERR_NOTHANDLED;
378
379 __inc_irq_stat(irq_unaligned_count);
380
381 /* log a message with pacing */
382 if (user_mode(regs)) {
383 if (current->thread.flags & PARISC_UAC_SIGBUS) {
384 goto force_sigbus;
385 }
386
387 if (!(current->thread.flags & PARISC_UAC_NOPRINT) &&
388 __ratelimit(&ratelimit)) {
389 printk(KERN_WARNING "%s(%d): unaligned access to " RFMT
390 " at ip " RFMT " (iir " RFMT ")\n",
391 current->comm, task_pid_nr(current), regs->ior,
392 regs->iaoq[0], regs->iir);
393 #ifdef DEBUG_UNALIGNED
394 show_regs(regs);
395 #endif
396 }
397
398 if (!unaligned_enabled)
399 goto force_sigbus;
400 } else {
401 static DEFINE_RATELIMIT_STATE(kernel_ratelimit, 5 * HZ, 5);
402 if (!(current->thread.flags & PARISC_UAC_NOPRINT) &&
403 !no_unaligned_warning &&
404 __ratelimit(&kernel_ratelimit))
405 pr_warn("Kernel: unaligned access to " RFMT " in %pS "
406 "(iir " RFMT ")\n",
407 regs->ior, (void *)regs->iaoq[0], regs->iir);
408 }
409
410 /* handle modification - OK, it's ugly, see the instruction manual */
411 switch (MAJOR_OP(regs->iir))
412 {
413 case 0x03:
414 case 0x09:
415 case 0x0b:
416 if (regs->iir&0x20)
417 {
418 modify = 1;
419 if (regs->iir&0x1000) /* short loads */
420 if (regs->iir&0x200)
421 newbase += IM5_3(regs->iir);
422 else
423 newbase += IM5_2(regs->iir);
424 else if (regs->iir&0x2000) /* scaled indexed */
425 {
426 int shift=0;
427 switch (regs->iir & OPCODE1_MASK)
428 {
429 case OPCODE_LDH_I:
430 shift= 1; break;
431 case OPCODE_LDW_I:
432 shift= 2; break;
433 case OPCODE_LDD_I:
434 case OPCODE_LDDA_I:
435 shift= 3; break;
436 }
437 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;
438 } else /* simple indexed */
439 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);
440 }
441 break;
442 case 0x13:
443 case 0x1b:
444 modify = 1;
445 newbase += IM14(regs->iir);
446 break;
447 case 0x14:
448 case 0x1c:
449 if (regs->iir&8)
450 {
451 modify = 1;
452 newbase += IM14(regs->iir&~0xe);
453 }
454 break;
455 case 0x16:
456 case 0x1e:
457 modify = 1;
458 newbase += IM14(regs->iir&6);
459 break;
460 case 0x17:
461 case 0x1f:
462 if (regs->iir&4)
463 {
464 modify = 1;
465 newbase += IM14(regs->iir&~4);
466 }
467 break;
468 }
469
470 /* TODO: make this cleaner... */
471 switch (regs->iir & OPCODE1_MASK)
472 {
473 case OPCODE_LDH_I:
474 case OPCODE_LDH_S:
475 ret = emulate_ldh(regs, R3(regs->iir));
476 break;
477
478 case OPCODE_LDW_I:
479 case OPCODE_LDWA_I:
480 case OPCODE_LDW_S:
481 case OPCODE_LDWA_S:
482 ret = emulate_ldw(regs, R3(regs->iir), 0);
483 break;
484
485 case OPCODE_STH:
486 ret = emulate_sth(regs, R2(regs->iir));
487 break;
488
489 case OPCODE_STW:
490 case OPCODE_STWA:
491 ret = emulate_stw(regs, R2(regs->iir), 0);
492 break;
493
494 #ifdef CONFIG_64BIT
495 case OPCODE_LDD_I:
496 case OPCODE_LDDA_I:
497 case OPCODE_LDD_S:
498 case OPCODE_LDDA_S:
499 ret = emulate_ldd(regs, R3(regs->iir), 0);
500 break;
501
502 case OPCODE_STD:
503 case OPCODE_STDA:
504 ret = emulate_std(regs, R2(regs->iir), 0);
505 break;
506 #endif
507
508 case OPCODE_FLDWX:
509 case OPCODE_FLDWS:
510 case OPCODE_FLDWXR:
511 case OPCODE_FLDWSR:
512 ret = emulate_ldw(regs, FR3(regs->iir), 1);
513 break;
514
515 case OPCODE_FLDDX:
516 case OPCODE_FLDDS:
517 ret = emulate_ldd(regs, R3(regs->iir), 1);
518 break;
519
520 case OPCODE_FSTWX:
521 case OPCODE_FSTWS:
522 case OPCODE_FSTWXR:
523 case OPCODE_FSTWSR:
524 ret = emulate_stw(regs, FR3(regs->iir), 1);
525 break;
526
527 case OPCODE_FSTDX:
528 case OPCODE_FSTDS:
529 ret = emulate_std(regs, R3(regs->iir), 1);
530 break;
531
532 case OPCODE_LDCD_I:
533 case OPCODE_LDCW_I:
534 case OPCODE_LDCD_S:
535 case OPCODE_LDCW_S:
536 ret = ERR_NOTHANDLED; /* "undefined", but lets kill them. */
537 break;
538 }
539 switch (regs->iir & OPCODE2_MASK)
540 {
541 case OPCODE_FLDD_L:
542 ret = emulate_ldd(regs,R2(regs->iir),1);
543 break;
544 case OPCODE_FSTD_L:
545 ret = emulate_std(regs, R2(regs->iir),1);
546 break;
547 #ifdef CONFIG_64BIT
548 case OPCODE_LDD_L:
549 ret = emulate_ldd(regs, R2(regs->iir),0);
550 break;
551 case OPCODE_STD_L:
552 ret = emulate_std(regs, R2(regs->iir),0);
553 break;
554 #endif
555 }
556 switch (regs->iir & OPCODE3_MASK)
557 {
558 case OPCODE_FLDW_L:
559 ret = emulate_ldw(regs, R2(regs->iir), 1);
560 break;
561 case OPCODE_LDW_M:
562 ret = emulate_ldw(regs, R2(regs->iir), 0);
563 break;
564
565 case OPCODE_FSTW_L:
566 ret = emulate_stw(regs, R2(regs->iir),1);
567 break;
568 case OPCODE_STW_M:
569 ret = emulate_stw(regs, R2(regs->iir),0);
570 break;
571 }
572 switch (regs->iir & OPCODE4_MASK)
573 {
574 case OPCODE_LDH_L:
575 ret = emulate_ldh(regs, R2(regs->iir));
576 break;
577 case OPCODE_LDW_L:
578 case OPCODE_LDWM:
579 ret = emulate_ldw(regs, R2(regs->iir),0);
580 break;
581 case OPCODE_STH_L:
582 ret = emulate_sth(regs, R2(regs->iir));
583 break;
584 case OPCODE_STW_L:
585 case OPCODE_STWM:
586 ret = emulate_stw(regs, R2(regs->iir),0);
587 break;
588 }
589
590 if (ret == 0 && modify && R1(regs->iir))
591 regs->gr[R1(regs->iir)] = newbase;
592
593
594 if (ret == ERR_NOTHANDLED)
595 printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);
596
597 DPRINTF("ret = %d\n", ret);
598
599 if (ret)
600 {
601 /*
602 * The unaligned handler failed.
603 * If we were called by __get_user() or __put_user() jump
604 * to it's exception fixup handler instead of crashing.
605 */
606 if (!user_mode(regs) && fixup_exception(regs))
607 return;
608
609 printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret);
610 die_if_kernel("Unaligned data reference", regs, 28);
611
612 if (ret == -EFAULT)
613 {
614 force_sig_fault(SIGSEGV, SEGV_MAPERR,
615 (void __user *)regs->ior);
616 }
617 else
618 {
619 force_sigbus:
620 /* couldn't handle it ... */
621 force_sig_fault(SIGBUS, BUS_ADRALN,
622 (void __user *)regs->ior);
623 }
624
625 return;
626 }
627
628 /* else we handled it, let life go on. */
629 regs->gr[0]|=PSW_N;
630 }
631
632 /*
633 * NB: check_unaligned() is only used for PCXS processors right
634 * now, so we only check for PA1.1 encodings at this point.
635 */
636
637 int
638 check_unaligned(struct pt_regs *regs)
639 {
640 unsigned long align_mask;
641
642 /* Get alignment mask */
643
644 align_mask = 0UL;
645 switch (regs->iir & OPCODE1_MASK) {
646
647 case OPCODE_LDH_I:
648 case OPCODE_LDH_S:
649 case OPCODE_STH:
650 align_mask = 1UL;
651 break;
652
653 case OPCODE_LDW_I:
654 case OPCODE_LDWA_I:
655 case OPCODE_LDW_S:
656 case OPCODE_LDWA_S:
657 case OPCODE_STW:
658 case OPCODE_STWA:
659 align_mask = 3UL;
660 break;
661
662 default:
663 switch (regs->iir & OPCODE4_MASK) {
664 case OPCODE_LDH_L:
665 case OPCODE_STH_L:
666 align_mask = 1UL;
667 break;
668 case OPCODE_LDW_L:
669 case OPCODE_LDWM:
670 case OPCODE_STW_L:
671 case OPCODE_STWM:
672 align_mask = 3UL;
673 break;
674 }
675 break;
676 }
677
678 return (int)(regs->ior & align_mask);
679 }
680
681
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