1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * charon board Device Tree Source
4 *
5 * Copyright (C) 2007 Semihalf
6 * Marian Balakowicz <m8@semihalf.com>
7 *
8 * Copyright (C) 2010 DENX Software Engineering GmbH
9 * Heiko Schocher <hs@denx.de>
10 */
11
12 /dts-v1/;
13
14 / {
15 model = "anon,charon";
16 compatible = "anon,charon";
17 #address-cells = <1>;
18 #size-cells = <1>;
19 interrupt-parent = <&mpc5200_pic>;
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 PowerPC,5200@0 {
26 device_type = "cpu";
27 reg = <0>;
28 d-cache-line-size = <32>;
29 i-cache-line-size = <32>;
30 d-cache-size = <0x4000>; // L1, 16K
31 i-cache-size = <0x4000>; // L1, 16K
32 timebase-frequency = <0>; // from bootloader
33 bus-frequency = <0>; // from bootloader
34 clock-frequency = <0>; // from bootloader
35 };
36 };
37
38 memory@0 {
39 device_type = "memory";
40 reg = <0x00000000 0x08000000>; // 128MB
41 };
42
43 soc5200@f0000000 {
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "fsl,mpc5200-immr";
47 ranges = <0 0xf0000000 0x0000c000>;
48 reg = <0xf0000000 0x00000100>;
49 bus-frequency = <0>; // from bootloader
50 system-frequency = <0>; // from bootloader
51
52 cdm@200 {
53 compatible = "fsl,mpc5200-cdm";
54 reg = <0x200 0x38>;
55 };
56
57 mpc5200_pic: interrupt-controller@500 {
58 // 5200 interrupts are encoded into two levels;
59 interrupt-controller;
60 #interrupt-cells = <3>;
61 compatible = "fsl,mpc5200-pic";
62 reg = <0x500 0x80>;
63 };
64
65 timer@600 { // General Purpose Timer
66 compatible = "fsl,mpc5200-gpt";
67 reg = <0x600 0x10>;
68 interrupts = <1 9 0>;
69 fsl,has-wdt;
70 };
71
72 can@900 {
73 compatible = "fsl,mpc5200-mscan";
74 interrupts = <2 17 0>;
75 reg = <0x900 0x80>;
76 };
77
78 can@980 {
79 compatible = "fsl,mpc5200-mscan";
80 interrupts = <2 18 0>;
81 reg = <0x980 0x80>;
82 };
83
84 gpio_simple: gpio@b00 {
85 compatible = "fsl,mpc5200-gpio";
86 reg = <0xb00 0x40>;
87 interrupts = <1 7 0>;
88 gpio-controller;
89 #gpio-cells = <2>;
90 };
91
92 usb@1000 {
93 compatible = "fsl,mpc5200-ohci","ohci-be";
94 reg = <0x1000 0xff>;
95 interrupts = <2 6 0>;
96 };
97
98 dma-controller@1200 {
99 device_type = "dma-controller";
100 compatible = "fsl,mpc5200-bestcomm";
101 reg = <0x1200 0x80>;
102 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
103 3 4 0 3 5 0 3 6 0 3 7 0
104 3 8 0 3 9 0 3 10 0 3 11 0
105 3 12 0 3 13 0 3 14 0 3 15 0>;
106 };
107
108 xlb@1f00 {
109 compatible = "fsl,mpc5200-xlb";
110 reg = <0x1f00 0x100>;
111 };
112
113 serial@2000 { // PSC1
114 compatible = "fsl,mpc5200-psc-uart";
115 reg = <0x2000 0x100>;
116 interrupts = <2 1 0>;
117 };
118
119 serial@2400 { // PSC3
120 compatible = "fsl,mpc5200-psc-uart";
121 reg = <0x2400 0x100>;
122 interrupts = <2 3 0>;
123 };
124
125 ethernet@3000 {
126 compatible = "fsl,mpc5200-fec";
127 reg = <0x3000 0x400>;
128 local-mac-address = [ 00 00 00 00 00 00 ];
129 interrupts = <2 5 0>;
130 fixed-link = <1 1 100 0 0>;
131 };
132
133 mdio@3000 {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 compatible = "fsl,mpc5200-mdio";
137 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
138 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
139 };
140
141 ata@3a00 {
142 compatible = "fsl,mpc5200-ata";
143 reg = <0x3a00 0x100>;
144 interrupts = <2 7 0>;
145 };
146
147 i2c@3d00 {
148 #address-cells = <1>;
149 #size-cells = <0>;
150 compatible = "fsl,mpc5200-i2c","fsl-i2c";
151 reg = <0x3d00 0x40>;
152 interrupts = <2 15 0>;
153 };
154
155
156 i2c@3d40 {
157 #address-cells = <1>;
158 #size-cells = <0>;
159 compatible = "fsl,mpc5200-i2c","fsl-i2c";
160 reg = <0x3d40 0x40>;
161 interrupts = <2 16 0>;
162
163 dtt@28 {
164 compatible = "national,lm80";
165 reg = <0x28>;
166 };
167
168 rtc@68 {
169 compatible = "dallas,ds1374";
170 reg = <0x68>;
171 };
172 };
173
174 sram@8000 {
175 compatible = "fsl,mpc5200-sram";
176 reg = <0x8000 0x4000>;
177 };
178 };
179
180 localbus {
181 compatible = "fsl,mpc5200-lpb","simple-bus";
182 #address-cells = <2>;
183 #size-cells = <1>;
184 ranges = < 0 0 0xfc000000 0x02000000
185 1 0 0xe0000000 0x04000000 // CS1 range, SM501
186 3 0 0xe8000000 0x00080000>;
187
188 flash@0,0 {
189 compatible = "cfi-flash";
190 reg = <0 0 0x02000000>;
191 bank-width = <4>;
192 device-width = <2>;
193 #size-cells = <1>;
194 #address-cells = <1>;
195 };
196
197 display@1,0 {
198 compatible = "smi,sm501";
199 reg = <1 0x00000000 0x00800000
200 1 0x03e00000 0x00200000>;
201 mode = "640x480-32@60";
202 interrupts = <1 1 3>;
203 little-endian;
204 };
205
206 mram0@3,0 {
207 compatible = "mtd-ram";
208 reg = <3 0x00000 0x80000>;
209 bank-width = <1>;
210 };
211 };
212
213 pci@f0000d00 {
214 #interrupt-cells = <1>;
215 #size-cells = <2>;
216 #address-cells = <3>;
217 device_type = "pci";
218 compatible = "fsl,mpc5200-pci";
219 reg = <0xf0000d00 0x100>;
220 interrupt-map-mask = <0xf800 0 0 7>;
221 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
222 0xc000 0 0 2 &mpc5200_pic 0 0 3
223 0xc000 0 0 3 &mpc5200_pic 0 0 3
224 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
225 clock-frequency = <0>; // From boot loader
226 interrupts = <2 8 0 2 9 0 2 10 0>;
227 bus-range = <0 0>;
228 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000>,
229 <0x02000000 0 0x90000000 0x90000000 0 0x10000000>,
230 <0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
231 };
232 };
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