1 /*
2 * B4420DS Device Tree Source
3 *
4 * Copyright 2012 - 2015 Freescale Semiconductor, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * This software is provided by Freescale Semiconductor "as is" and any
24 * express or implied warranties, including, but not limited to, the implied
25 * warranties of merchantability and fitness for a particular purpose are
26 * disclaimed. In no event shall Freescale Semiconductor be liable for any
27 * direct, indirect, incidental, special, exemplary, or consequential damages
28 * (including, but not limited to, procurement of substitute goods or services;
29 * loss of use, data, or profits; or business interruption) however caused and
30 * on any theory of liability, whether in contract, strict liability, or tort
31 * (including negligence or otherwise) arising in any way out of the use of
32 * this software, even if advised of the possibility of such damage.
33 */
34
35 / {
36 model = "fsl,B4QDS";
37 compatible = "fsl,B4QDS";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 crypto = &crypto;
44 phy_sgmii_10 = &phy_sgmii_10;
45 phy_sgmii_11 = &phy_sgmii_11;
46 phy_sgmii_1c = &phy_sgmii_1c;
47 phy_sgmii_1d = &phy_sgmii_1d;
48 };
49
50 ifc: localbus@ffe124000 {
51 reg = <0xf 0xfe124000 0 0x2000>;
52 ranges = <0 0 0xf 0xe8000000 0x08000000
53 2 0 0xf 0xff800000 0x00010000
54 3 0 0xf 0xffdf0000 0x00008000>;
55
56 nor@0,0 {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 compatible = "cfi-flash";
60 reg = <0x0 0x0 0x8000000>;
61 bank-width = <2>;
62 device-width = <1>;
63 };
64
65 nand@2,0 {
66 #address-cells = <1>;
67 #size-cells = <1>;
68 compatible = "fsl,ifc-nand";
69 reg = <0x2 0x0 0x10000>;
70
71 partition@0 {
72 /* This location must not be altered */
73 /* 1MB for u-boot Bootloader Image */
74 reg = <0x0 0x00100000>;
75 label = "NAND U-Boot Image";
76 read-only;
77 };
78
79 partition@100000 {
80 /* 1MB for DTB Image */
81 reg = <0x00100000 0x00100000>;
82 label = "NAND DTB Image";
83 };
84
85 partition@200000 {
86 /* 10MB for Linux Kernel Image */
87 reg = <0x00200000 0x00A00000>;
88 label = "NAND Linux Kernel Image";
89 };
90
91 partition@c00000 {
92 /* 500MB for Root file System Image */
93 reg = <0x00c00000 0x1F400000>;
94 label = "NAND RFS Image";
95 };
96 };
97
98 board-control@3,0 {
99 compatible = "fsl,b4qds-fpga", "fsl,fpga-qixis";
100 reg = <3 0 0x300>;
101 };
102 };
103
104 memory {
105 device_type = "memory";
106 };
107
108 reserved-memory {
109 #address-cells = <2>;
110 #size-cells = <2>;
111 ranges;
112
113 bman_fbpr: bman-fbpr {
114 size = <0 0x1000000>;
115 alignment = <0 0x1000000>;
116 };
117 qman_fqd: qman-fqd {
118 size = <0 0x400000>;
119 alignment = <0 0x400000>;
120 };
121 qman_pfdr: qman-pfdr {
122 size = <0 0x2000000>;
123 alignment = <0 0x2000000>;
124 };
125 };
126
127 dcsr: dcsr@f00000000 {
128 ranges = <0x00000000 0xf 0x00000000 0x01052000>;
129 };
130
131 bportals: bman-portals@ff4000000 {
132 ranges = <0x0 0xf 0xf4000000 0x2000000>;
133 };
134
135 qportals: qman-portals@ff6000000 {
136 ranges = <0x0 0xf 0xf6000000 0x2000000>;
137 };
138
139 soc: soc@ffe000000 {
140 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
141 reg = <0xf 0xfe000000 0 0x00001000>;
142 spi@110000 {
143 flash@0 {
144 #address-cells = <1>;
145 #size-cells = <1>;
146 compatible = "sst,sst25wf040", "jedec,spi-nor";
147 reg = <0>;
148 spi-max-frequency = <40000000>; /* input clock */
149 };
150 };
151
152 sdhc@114000 {
153 /*Disabled as there is no sdhc connector on B4420QDS board*/
154 status = "disabled";
155 };
156
157 i2c@118000 {
158 mux@77 {
159 compatible = "nxp,pca9547";
160 reg = <0x77>;
161 #address-cells = <1>;
162 #size-cells = <0>;
163
164 i2c@0 {
165 #address-cells = <1>;
166 #size-cells = <0>;
167 reg = <0>;
168
169 eeprom@50 {
170 compatible = "atmel,24c64";
171 reg = <0x50>;
172 };
173 eeprom@51 {
174 compatible = "atmel,24c256";
175 reg = <0x51>;
176 };
177 eeprom@53 {
178 compatible = "atmel,24c256";
179 reg = <0x53>;
180 };
181 eeprom@57 {
182 compatible = "atmel,24c256";
183 reg = <0x57>;
184 };
185 rtc@68 {
186 compatible = "dallas,ds3232";
187 reg = <0x68>;
188 };
189 };
190
191 i2c@2 {
192 #address-cells = <1>;
193 #size-cells = <0>;
194 reg = <0x2>;
195
196 ina220@40 {
197 compatible = "ti,ina220";
198 reg = <0x40>;
199 shunt-resistor = <1000>;
200 };
201 };
202
203 i2c@3 {
204 #address-cells = <1>;
205 #size-cells = <0>;
206 reg = <0x3>;
207
208 adt7461@4c {
209 compatible = "adi,adt7461";
210 reg = <0x4c>;
211 };
212 };
213 };
214 };
215
216 usb@210000 {
217 dr_mode = "host";
218 phy_type = "ulpi";
219 };
220
221 fman@400000 {
222 ethernet@e0000 {
223 phy-handle = <&phy_sgmii_10>;
224 phy-connection-type = "sgmii";
225 };
226
227 ethernet@e2000 {
228 phy-handle = <&phy_sgmii_11>;
229 phy-connection-type = "sgmii";
230 };
231
232 ethernet@e4000 {
233 phy-handle = <&phy_sgmii_1c>;
234 phy-connection-type = "sgmii";
235 };
236
237 ethernet@e6000 {
238 phy-handle = <&phy_sgmii_1d>;
239 phy-connection-type = "sgmii";
240 };
241
242 mdio@fc000 {
243 phy_sgmii_10: ethernet-phy@10 {
244 reg = <0x10>;
245 };
246
247 phy_sgmii_11: ethernet-phy@11 {
248 reg = <0x11>;
249 };
250
251 phy_sgmii_1c: ethernet-phy@1c {
252 reg = <0x1c>;
253 status = "disabled";
254 };
255
256 phy_sgmii_1d: ethernet-phy@1d {
257 reg = <0x1d>;
258 status = "disabled";
259 };
260 };
261 };
262 };
263
264 pci0: pcie@ffe200000 {
265 reg = <0xf 0xfe200000 0 0x10000>;
266 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
267 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
268 pcie@0 {
269 ranges = <0x02000000 0 0xe0000000
270 0x02000000 0 0xe0000000
271 0 0x20000000
272
273 0x01000000 0 0x00000000
274 0x01000000 0 0x00000000
275 0 0x00010000>;
276 };
277 };
278 };
279
280 /include/ "b4si-post.dtsi"
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