1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * GE IMP3A Device Tree Source
4 *
5 * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
6 *
7 * Based on: P2020 DS Device Tree Source
8 * Copyright 2009 Freescale Semiconductor Inc.
9 */
10
11 /include/ "p2020si-pre.dtsi"
12
13 / {
14 model = "GE_IMP3A";
15 compatible = "ge,imp3a";
16
17 memory {
18 device_type = "memory";
19 };
20
21 lbc: localbus@fef05000 {
22 reg = <0 0xfef05000 0 0x1000>;
23
24 ranges = <0x0 0x0 0x0 0xff000000 0x01000000
25 0x1 0x0 0x0 0xe0000000 0x08000000
26 0x2 0x0 0x0 0xe8000000 0x08000000
27 0x3 0x0 0x0 0xfc100000 0x00020000
28 0x4 0x0 0x0 0xfc000000 0x00008000
29 0x5 0x0 0x0 0xfc008000 0x00008000
30 0x6 0x0 0x0 0xfee00000 0x00040000
31 0x7 0x0 0x0 0xfee80000 0x00040000>;
32
33 /* nor@0,0 is a mirror of part of the memory in nor@1,0
34 nor@0,0 {
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "ge,imp3a-firmware-mirror", "cfi-flash";
38 reg = <0x0 0x0 0x1000000>;
39 bank-width = <2>;
40 device-width = <1>;
41
42 partition@0 {
43 label = "firmware";
44 reg = <0x0 0x1000000>;
45 read-only;
46 };
47 };
48 */
49
50 nor@1,0 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "ge,imp3a-paged-flash", "cfi-flash";
54 reg = <0x1 0x0 0x8000000>;
55 bank-width = <2>;
56 device-width = <1>;
57
58 partition@0 {
59 label = "user";
60 reg = <0x0 0x7800000>;
61 };
62
63 partition@7800000 {
64 label = "firmware";
65 reg = <0x7800000 0x800000>;
66 read-only;
67 };
68 };
69
70 nvram@3,0 {
71 device_type = "nvram";
72 compatible = "simtek,stk14ca8";
73 reg = <0x3 0x0 0x20000>;
74 };
75
76 fpga@4,0 {
77 compatible = "ge,imp3a-fpga-regs";
78 reg = <0x4 0x0 0x20>;
79 };
80
81 gef_pic: pic@4,20 {
82 #interrupt-cells = <1>;
83 interrupt-controller;
84 device_type = "interrupt-controller";
85 compatible = "ge,imp3a-fpga-pic", "gef,fpga-pic-1.00";
86 reg = <0x4 0x20 0x20>;
87 interrupts = <6 7 0 0>;
88 };
89
90 gef_gpio: gpio@4,400 {
91 #gpio-cells = <2>;
92 compatible = "ge,imp3a-gpio";
93 reg = <0x4 0x400 0x24>;
94 gpio-controller;
95 };
96
97 wdt@4,800 {
98 compatible = "ge,imp3a-fpga-wdt", "gef,fpga-wdt-1.00",
99 "gef,fpga-wdt";
100 reg = <0x4 0x800 0x8>;
101 interrupts = <10 4>;
102 interrupt-parent = <&gef_pic>;
103 };
104
105 /* Second watchdog available, driver currently supports one.
106 wdt@4,808 {
107 compatible = "gef,imp3a-fpga-wdt", "gef,fpga-wdt-1.00",
108 "gef,fpga-wdt";
109 reg = <0x4 0x808 0x8>;
110 interrupts = <9 4>;
111 interrupt-parent = <&gef_pic>;
112 };
113 */
114
115 nand@6,0 {
116 compatible = "fsl,elbc-fcm-nand";
117 reg = <0x6 0x0 0x40000>;
118 };
119
120 nand@7,0 {
121 compatible = "fsl,elbc-fcm-nand";
122 reg = <0x7 0x0 0x40000>;
123 };
124 };
125
126 soc: soc@fef00000 {
127 ranges = <0x0 0 0xfef00000 0x100000>;
128
129 i2c@3000 {
130 hwmon@48 {
131 compatible = "national,lm92";
132 reg = <0x48>;
133 };
134
135 hwmon@4c {
136 compatible = "adi,adt7461";
137 reg = <0x4c>;
138 };
139
140 rtc@51 {
141 compatible = "epson,rx8581";
142 reg = <0x51>;
143 };
144
145 eti@6b {
146 compatible = "dallas,ds1682";
147 reg = <0x6b>;
148 };
149 };
150
151 usb@22000 {
152 phy_type = "ulpi";
153 dr_mode = "host";
154 };
155
156 mdio@24520 {
157 phy0: ethernet-phy@0 {
158 interrupt-parent = <&gef_pic>;
159 interrupts = <0xc 0x4>;
160 reg = <0x1>;
161 };
162 phy1: ethernet-phy@1 {
163 interrupt-parent = <&gef_pic>;
164 interrupts = <0xb 0x4>;
165 reg = <0x2>;
166 };
167 tbi0: tbi-phy@11 {
168 reg = <0x11>;
169 device_type = "tbi-phy";
170 };
171 };
172
173 mdio@25520 {
174 tbi1: tbi-phy@11 {
175 reg = <0x11>;
176 device_type = "tbi-phy";
177 };
178 };
179
180 mdio@26520 {
181 status = "disabled";
182 };
183
184 enet0: ethernet@24000 {
185 tbi-handle = <&tbi0>;
186 phy-handle = <&phy0>;
187 phy-connection-type = "gmii";
188 };
189
190 enet1: ethernet@25000 {
191 tbi-handle = <&tbi1>;
192 phy-handle = <&phy1>;
193 phy-connection-type = "gmii";
194 };
195
196 enet2: ethernet@26000 {
197 status = "disabled";
198 };
199 };
200
201 pci0: pcie@fef08000 {
202 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
203 0x1000000 0x0 0x00000000 0 0xfe020000 0x0 0x10000>;
204 reg = <0 0xfef08000 0 0x1000>;
205
206 pcie@0 {
207 ranges = <0x2000000 0x0 0xc0000000
208 0x2000000 0x0 0xc0000000
209 0x0 0x20000000
210
211 0x1000000 0x0 0x0
212 0x1000000 0x0 0x0
213 0x0 0x10000>;
214 };
215 };
216
217 pci1: pcie@fef09000 {
218 reg = <0 0xfef09000 0 0x1000>;
219 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
220 0x1000000 0x0 0x00000000 0 0xfe010000 0x0 0x10000>;
221
222 pcie@0 {
223 ranges = <0x2000000 0x0 0xa0000000
224 0x2000000 0x0 0xa0000000
225 0x0 0x20000000
226
227 0x1000000 0x0 0x0
228 0x1000000 0x0 0x0
229 0x0 0x10000>;
230 };
231
232 };
233
234 pci2: pcie@fef0a000 {
235 reg = <0 0xfef0a000 0 0x1000>;
236 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
237 0x1000000 0x0 0x00000000 0 0xfe000000 0x0 0x10000>;
238
239 pcie@0 {
240 ranges = <0x2000000 0x0 0x80000000
241 0x2000000 0x0 0x80000000
242 0x0 0x20000000
243
244 0x1000000 0x0 0x0
245 0x1000000 0x0 0x0
246 0x0 0x10000>;
247 };
248 };
249 };
250
251 /include/ "p2020si-post.dtsi"
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