1 /*
2 * P1025 TWR Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 /{
36 aliases {
37 ethernet3 = &enet3;
38 ethernet4 = &enet4;
39 };
40 };
41
42 &lbc {
43 nor@0,0 {
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "cfi-flash";
47 reg = <0x0 0x0 0x4000000>;
48 bank-width = <2>;
49 device-width = <1>;
50
51 partition@0 {
52 /* This location must not be altered */
53 /* 256KB for Vitesse 7385 Switch firmware */
54 reg = <0x0 0x00040000>;
55 label = "NOR Vitesse-7385 Firmware";
56 read-only;
57 };
58
59 partition@40000 {
60 /* 256KB for DTB Image */
61 reg = <0x00040000 0x00040000>;
62 label = "NOR DTB Image";
63 };
64
65 partition@80000 {
66 /* 5.5 MB for Linux Kernel Image */
67 reg = <0x00080000 0x00580000>;
68 label = "NOR Linux Kernel Image";
69 };
70
71 partition@400000 {
72 /* 56.75MB for Root file System */
73 reg = <0x00600000 0x038c0000>;
74 label = "NOR Root File System";
75 };
76
77 partition@ec0000 {
78 /* This location must not be altered */
79 /* 256KB for QE ucode firmware*/
80 reg = <0x03ec0000 0x00040000>;
81 label = "NOR QE microcode firmware";
82 read-only;
83 };
84
85 partition@f00000 {
86 /* This location must not be altered */
87 /* 512KB for u-boot Bootloader Image */
88 /* 512KB for u-boot Environment Variables */
89 reg = <0x03f00000 0x00100000>;
90 label = "NOR U-Boot Image";
91 read-only;
92 };
93 };
94
95 /* CS2 for Display */
96 display@2,0 {
97 compatible = "solomon,ssd1289fb";
98 reg = <0x2 0x0000 0x0004>;
99 };
100
101 };
102
103 &soc {
104 usb@22000 {
105 phy_type = "ulpi";
106 };
107
108 mdio@24000 {
109 phy0: ethernet-phy@2 {
110 interrupt-parent = <&mpic>;
111 interrupts = <1 1 0 0>;
112 reg = <0x2>;
113 };
114
115 phy1: ethernet-phy@1 {
116 interrupt-parent = <&mpic>;
117 interrupts = <2 1 0 0>;
118 reg = <0x1>;
119 };
120
121 tbi0: tbi-phy@11 {
122 reg = <0x11>;
123 device_type = "tbi-phy";
124 };
125 };
126
127 mdio@25000 {
128 tbi1: tbi-phy@11 {
129 reg = <0x11>;
130 device_type = "tbi-phy";
131 };
132 };
133
134 mdio@26000 {
135 tbi2: tbi-phy@11 {
136 reg = <0x11>;
137 device_type = "tbi-phy";
138 };
139 };
140
141 ptp_clock@b0e00 {
142 compatible = "fsl,etsec-ptp";
143 reg = <0xb0e00 0xb0>;
144 interrupts = <68 2 0 0 69 2 0 0>;
145 fsl,tclk-period = <10>;
146 fsl,tmr-prsc = <2>;
147 fsl,tmr-add = <0xc0000021>;
148 fsl,tmr-fiper1 = <999999990>;
149 fsl,tmr-fiper2 = <99990>;
150 fsl,max-adj = <133333332>;
151 };
152
153 enet0: ethernet@b0000 {
154 phy-handle = <&phy0>;
155 phy-connection-type = "rgmii-id";
156
157 };
158
159 enet1: ethernet@b1000 {
160 status = "disabled";
161 };
162
163 enet2: ethernet@b2000 {
164 phy-handle = <&phy1>;
165 phy-connection-type = "rgmii-id";
166 };
167
168 par_io@e0100 {
169 #address-cells = <1>;
170 #size-cells = <1>;
171 reg = <0xe0100 0x60>;
172 ranges = <0x0 0xe0100 0x60>;
173 device_type = "par_io";
174 num-ports = <3>;
175 pio1: ucc_pin@1 {
176 pio-map = <
177 /* port pin dir open_drain assignment has_irq */
178 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
179 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
180 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
181 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */
182 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
183 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
184 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
185 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
186 0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */
187 0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */
188 0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
189 0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
190 0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
191 0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */
192 0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */
193 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */
194 0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */
195 0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
196 };
197
198 pio2: ucc_pin@2 {
199 pio-map = <
200 /* port pin dir open_drain assignment has_irq */
201 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
202 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
203 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */
204 0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */
205 0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */
206 0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */
207 0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */
208 0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */
209 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */
210 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
211 };
212
213 pio3: ucc_pin@3 {
214 pio-map = <
215 /* port pin dir open_drain assignment has_irq */
216 0x0 0x16 0x2 0x0 0x2 0x0 /* SER7_CD_B*/
217 0x0 0x12 0x2 0x0 0x2 0x0 /* SER7_CTS_B*/
218 0x0 0x13 0x1 0x0 0x2 0x0 /* SER7_RTS_B*/
219 0x0 0x14 0x2 0x0 0x2 0x0 /* SER7_RXD0*/
220 0x0 0x15 0x1 0x0 0x2 0x0>; /* SER7_TXD0*/
221 };
222
223 pio4: ucc_pin@4 {
224 pio-map = <
225 /* port pin dir open_drain assignment has_irq */
226 0x1 0x0 0x2 0x0 0x2 0x0 /* SER3_CD_B*/
227 0x0 0x1c 0x2 0x0 0x2 0x0 /* SER3_CTS_B*/
228 0x0 0x1d 0x1 0x0 0x2 0x0 /* SER3_RTS_B*/
229 0x0 0x1e 0x2 0x0 0x2 0x0 /* SER3_RXD0*/
230 0x0 0x1f 0x1 0x0 0x2 0x0>; /* SER3_TXD0*/
231 };
232 };
233 };
234
235 &qe {
236 enet3: ucc@2000 {
237 device_type = "network";
238 compatible = "ucc_geth";
239 rx-clock-name = "clk12";
240 tx-clock-name = "clk9";
241 pio-handle = <&pio1>;
242 phy-handle = <&qe_phy0>;
243 phy-connection-type = "mii";
244 };
245
246 mdio@2120 {
247 qe_phy0: ethernet-phy@18 {
248 interrupt-parent = <&mpic>;
249 interrupts = <4 1 0 0>;
250 reg = <0x18>;
251 device_type = "ethernet-phy";
252 };
253 qe_phy1: ethernet-phy@19 {
254 interrupt-parent = <&mpic>;
255 interrupts = <5 1 0 0>;
256 reg = <0x19>;
257 device_type = "ethernet-phy";
258 };
259 tbi-phy@11 {
260 reg = <0x11>;
261 device_type = "tbi-phy";
262 };
263 };
264
265 enet4: ucc@2400 {
266 device_type = "network";
267 compatible = "ucc_geth";
268 rx-clock-name = "none";
269 tx-clock-name = "clk13";
270 pio-handle = <&pio2>;
271 phy-handle = <&qe_phy1>;
272 phy-connection-type = "rmii";
273 };
274
275 serial2: ucc@2600 {
276 device_type = "serial";
277 compatible = "ucc_uart";
278 port-number = <0>;
279 rx-clock-name = "brg6";
280 tx-clock-name = "brg6";
281 pio-handle = <&pio3>;
282 };
283
284 serial3: ucc@2200 {
285 device_type = "serial";
286 compatible = "ucc_uart";
287 port-number = <1>;
288 rx-clock-name = "brg2";
289 tx-clock-name = "brg2";
290 pio-handle = <&pio4>;
291 };
292 };
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