1 /*
2 * T1024 RDB Device Tree Source
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 /include/ "t102xsi-pre.dtsi"
36
37 / {
38 model = "fsl,T1024RDB";
39 compatible = "fsl,T1024RDB";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 aliases {
45 sg_2500_aqr105_phy4 = &sg_2500_aqr105_phy4;
46 };
47
48 reserved-memory {
49 #address-cells = <2>;
50 #size-cells = <2>;
51 ranges;
52
53 bman_fbpr: bman-fbpr {
54 size = <0 0x1000000>;
55 alignment = <0 0x1000000>;
56 };
57
58 qman_fqd: qman-fqd {
59 size = <0 0x400000>;
60 alignment = <0 0x400000>;
61 };
62
63 qman_pfdr: qman-pfdr {
64 size = <0 0x2000000>;
65 alignment = <0 0x2000000>;
66 };
67 };
68
69 ifc: localbus@ffe124000 {
70 reg = <0xf 0xfe124000 0 0x2000>;
71 ranges = <0 0 0xf 0xe8000000 0x08000000
72 2 0 0xf 0xff800000 0x00010000
73 3 0 0xf 0xffdf0000 0x00008000>;
74
75 nor@0,0 {
76 #address-cells = <1>;
77 #size-cells = <1>;
78 compatible = "cfi-flash";
79 reg = <0x0 0x0 0x8000000>;
80 bank-width = <2>;
81 device-width = <1>;
82 };
83
84 nand@1,0 {
85 #address-cells = <1>;
86 #size-cells = <1>;
87 compatible = "fsl,ifc-nand";
88 reg = <0x2 0x0 0x10000>;
89 };
90
91 board-control@2,0 {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "fsl,t1024-cpld", "fsl,deepsleep-cpld";
95 reg = <3 0 0x300>;
96 ranges = <0 3 0 0x300>;
97 bank-width = <1>;
98 device-width = <1>;
99 };
100 };
101
102 memory {
103 device_type = "memory";
104 };
105
106 dcsr: dcsr@f00000000 {
107 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
108 };
109
110 bportals: bman-portals@ff4000000 {
111 ranges = <0x0 0xf 0xf4000000 0x2000000>;
112 };
113
114 qportals: qman-portals@ff6000000 {
115 ranges = <0x0 0xf 0xf6000000 0x2000000>;
116 };
117
118 soc: soc@ffe000000 {
119 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
120 reg = <0xf 0xfe000000 0 0x00001000>;
121 spi@110000 {
122 flash@0 {
123 #address-cells = <1>;
124 #size-cells = <1>;
125 compatible = "micron,n25q512ax3", "jedec,spi-nor";
126 reg = <0>;
127 spi-max-frequency = <10000000>; /* input clk */
128 };
129
130 slic@1 {
131 compatible = "maxim,ds26522";
132 reg = <1>;
133 spi-max-frequency = <2000000>;
134 };
135
136 slic@2 {
137 compatible = "maxim,ds26522";
138 reg = <2>;
139 spi-max-frequency = <2000000>;
140 };
141 };
142
143 i2c@118000 {
144 adt7461@4c {
145 /* Thermal Monitor */
146 compatible = "adi,adt7461";
147 reg = <0x4c>;
148 };
149
150 current-sensor@40 {
151 compatible = "ti,ina220";
152 reg = <0x40>;
153 shunt-resistor = <1000>;
154 };
155
156 eeprom@50 {
157 compatible = "atmel,24c256";
158 reg = <0x50>;
159 };
160
161 rtc@68 {
162 compatible = "dallas,ds1339";
163 reg = <0x68>;
164 };
165 };
166
167 i2c@118100 {
168 i2c-mux@77 {
169 compatible = "nxp,pca9546";
170 reg = <0x77>;
171 #address-cells = <1>;
172 #size-cells = <0>;
173 };
174 };
175
176 fman@400000 {
177 fm1mac1: ethernet@e0000 {
178 phy-handle = <&xg_aqr105_phy3>;
179 phy-connection-type = "xgmii";
180 sleep = <&rcpm 0x80000000>;
181 };
182
183 fm1mac2: ethernet@e2000 {
184 sleep = <&rcpm 0x40000000>;
185 };
186
187 fm1mac3: ethernet@e4000 {
188 phy-handle = <&rgmii_phy2>;
189 phy-connection-type = "rgmii";
190 sleep = <&rcpm 0x20000000>;
191 };
192
193 fm1mac4: ethernet@e6000 {
194 phy-handle = <&rgmii_phy1>;
195 phy-connection-type = "rgmii";
196 sleep = <&rcpm 0x10000000>;
197 };
198
199
200 mdio0: mdio@fc000 {
201 rgmii_phy1: ethernet-phy@2 {
202 reg = <0x2>;
203 };
204 rgmii_phy2: ethernet-phy@6 {
205 reg = <0x6>;
206 };
207 };
208
209 xmdio0: mdio@fd000 {
210 xg_aqr105_phy3: ethernet-phy@1 {
211 compatible = "ethernet-phy-ieee802.3-c45";
212 reg = <0x1>;
213 };
214 sg_2500_aqr105_phy4: ethernet-phy@2 {
215 compatible = "ethernet-phy-ieee802.3-c45";
216 reg = <0x2>;
217 };
218 };
219 };
220 };
221
222 pci0: pcie@ffe240000 {
223 reg = <0xf 0xfe240000 0 0x10000>;
224 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0 0x10000000
225 0x01000000 0 0x00000000 0xf 0xf8000000 0 0x00010000>;
226 pcie@0 {
227 ranges = <0x02000000 0 0xe0000000
228 0x02000000 0 0xe0000000
229 0 0x10000000
230
231 0x01000000 0 0x00000000
232 0x01000000 0 0x00000000
233 0 0x00010000>;
234 };
235 };
236
237 pci1: pcie@ffe250000 {
238 reg = <0xf 0xfe250000 0 0x10000>;
239 ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000
240 0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>;
241 pcie@0 {
242 ranges = <0x02000000 0 0xe0000000
243 0x02000000 0 0xe0000000
244 0 0x10000000
245
246 0x01000000 0 0x00000000
247 0x01000000 0 0x00000000
248 0 0x00010000>;
249 };
250 };
251
252 pci2: pcie@ffe260000 {
253 reg = <0xf 0xfe260000 0 0x10000>;
254 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
255 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
256 pcie@0 {
257 ranges = <0x02000000 0 0xe0000000
258 0x02000000 0 0xe0000000
259 0 0x10000000
260
261 0x01000000 0 0x00000000
262 0x01000000 0 0x00000000
263 0 0x00010000>;
264 };
265 };
266 };
267
268 #include "t1024si-post.dtsi"
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