1 /*
2 * T1040RDB Device Tree Source
3 *
4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 /include/ "t104xsi-pre.dtsi"
36 /include/ "t104xrdb.dtsi"
37
38 / {
39 model = "fsl,T1040RDB";
40 compatible = "fsl,T1040RDB";
41
42 aliases {
43 phy_sgmii_2 = &phy_sgmii_2;
44 };
45
46 soc@ffe000000 {
47 fman@400000 {
48 ethernet@e0000 {
49 fixed-link = <0 1 1000 0 0>;
50 phy-connection-type = "sgmii";
51 };
52
53 ethernet@e2000 {
54 fixed-link = <1 1 1000 0 0>;
55 phy-connection-type = "sgmii";
56 };
57
58 ethernet@e4000 {
59 phy-handle = <&phy_sgmii_2>;
60 phy-connection-type = "sgmii";
61 };
62
63 mdio@fc000 {
64 phy_sgmii_2: ethernet-phy@3 {
65 reg = <0x03>;
66 };
67
68 /* VSC8514 QSGMII PHY */
69 phy_qsgmii_0: ethernet-phy@4 {
70 reg = <0x4>;
71 };
72
73 phy_qsgmii_1: ethernet-phy@5 {
74 reg = <0x5>;
75 };
76
77 phy_qsgmii_2: ethernet-phy@6 {
78 reg = <0x6>;
79 };
80
81 phy_qsgmii_3: ethernet-phy@7 {
82 reg = <0x7>;
83 };
84
85 /* VSC8514 QSGMII PHY */
86 phy_qsgmii_4: ethernet-phy@8 {
87 reg = <0x8>;
88 };
89
90 phy_qsgmii_5: ethernet-phy@9 {
91 reg = <0x9>;
92 };
93
94 phy_qsgmii_6: ethernet-phy@a {
95 reg = <0xa>;
96 };
97
98 phy_qsgmii_7: ethernet-phy@b {
99 reg = <0xb>;
100 };
101 };
102 };
103 };
104
105 ifc: localbus@ffe124000 {
106 cpld@3,0 {
107 compatible = "fsl,t104xrdb-cpld", "fsl,deepsleep-cpld";
108 };
109 };
110 };
111
112 #include "t1040si-post.dtsi"
113
114 &seville_switch {
115 status = "okay";
116 };
117
118 &seville_port0 {
119 managed = "in-band-status";
120 phy-handle = <&phy_qsgmii_0>;
121 phy-mode = "qsgmii";
122 label = "ETH3";
123 status = "okay";
124 };
125
126 &seville_port1 {
127 managed = "in-band-status";
128 phy-handle = <&phy_qsgmii_1>;
129 phy-mode = "qsgmii";
130 label = "ETH4";
131 status = "okay";
132 };
133
134 &seville_port2 {
135 managed = "in-band-status";
136 phy-handle = <&phy_qsgmii_2>;
137 phy-mode = "qsgmii";
138 label = "ETH5";
139 status = "okay";
140 };
141
142 &seville_port3 {
143 managed = "in-band-status";
144 phy-handle = <&phy_qsgmii_3>;
145 phy-mode = "qsgmii";
146 label = "ETH6";
147 status = "okay";
148 };
149
150 &seville_port4 {
151 managed = "in-band-status";
152 phy-handle = <&phy_qsgmii_4>;
153 phy-mode = "qsgmii";
154 label = "ETH7";
155 status = "okay";
156 };
157
158 &seville_port5 {
159 managed = "in-band-status";
160 phy-handle = <&phy_qsgmii_5>;
161 phy-mode = "qsgmii";
162 label = "ETH8";
163 status = "okay";
164 };
165
166 &seville_port6 {
167 managed = "in-band-status";
168 phy-handle = <&phy_qsgmii_6>;
169 phy-mode = "qsgmii";
170 label = "ETH9";
171 status = "okay";
172 };
173
174 &seville_port7 {
175 managed = "in-band-status";
176 phy-handle = <&phy_qsgmii_7>;
177 phy-mode = "qsgmii";
178 label = "ETH10";
179 status = "okay";
180 };
181
182 &seville_port8 {
183 status = "okay";
184 };
185
186 &seville_port9 {
187 status = "okay";
188 };
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