1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * mpc8308_p1m Device Tree Source
4 *
5 * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
6 */
7
8 /dts-v1/;
9
10 / {
11 compatible = "denx,mpc8308_p1m";
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 aliases {
16 ethernet0 = &enet0;
17 ethernet1 = &enet1;
18 serial0 = &serial0;
19 serial1 = &serial1;
20 pci0 = &pci0;
21 };
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 PowerPC,8308@0 {
28 device_type = "cpu";
29 reg = <0x0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <16384>;
33 i-cache-size = <16384>;
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
37 };
38 };
39
40 memory {
41 device_type = "memory";
42 reg = <0x00000000 0x08000000>; // 128MB at 0
43 };
44
45 localbus@e0005000 {
46 #address-cells = <2>;
47 #size-cells = <1>;
48 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
49 reg = <0xe0005000 0x1000>;
50 interrupts = <77 0x8>;
51 interrupt-parent = <&ipic>;
52
53 ranges = <0x0 0x0 0xfc000000 0x04000000
54 0x1 0x0 0xfbff0000 0x00008000
55 0x2 0x0 0xfbff8000 0x00008000>;
56
57 flash@0,0 {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "cfi-flash";
61 reg = <0x0 0x0 0x4000000>;
62 bank-width = <2>;
63 device-width = <1>;
64
65 u-boot@0 {
66 reg = <0x0 0x60000>;
67 read-only;
68 };
69 env@60000 {
70 reg = <0x60000 0x20000>;
71 };
72 env1@80000 {
73 reg = <0x80000 0x20000>;
74 };
75 kernel@a0000 {
76 reg = <0xa0000 0x200000>;
77 };
78 dtb@2a0000 {
79 reg = <0x2a0000 0x20000>;
80 };
81 ramdisk@2c0000 {
82 reg = <0x2c0000 0x640000>;
83 };
84 user@700000 {
85 reg = <0x700000 0x3900000>;
86 };
87 };
88
89 can@1,0 {
90 compatible = "nxp,sja1000";
91 reg = <0x1 0x0 0x80>;
92 interrupts = <18 0x8>;
93 interrups-parent = <&ipic>;
94 };
95
96 cpld@2,0 {
97 compatible = "denx,mpc8308_p1m-cpld";
98 reg = <0x2 0x0 0x8>;
99 interrupts = <48 0x8>;
100 interrups-parent = <&ipic>;
101 };
102 };
103
104 immr@e0000000 {
105 #address-cells = <1>;
106 #size-cells = <1>;
107 device_type = "soc";
108 compatible = "fsl,mpc8308-immr", "simple-bus";
109 ranges = <0 0xe0000000 0x00100000>;
110 reg = <0xe0000000 0x00000200>;
111 bus-frequency = <0>;
112
113 i2c@3000 {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 compatible = "fsl-i2c";
117 reg = <0x3000 0x100>;
118 interrupts = <14 0x8>;
119 interrupt-parent = <&ipic>;
120 dfsrr;
121 fram@50 {
122 compatible = "ramtron,24c64", "atmel,24c64";
123 reg = <0x50>;
124 };
125 };
126
127 i2c@3100 {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 compatible = "fsl-i2c";
131 reg = <0x3100 0x100>;
132 interrupts = <15 0x8>;
133 interrupt-parent = <&ipic>;
134 dfsrr;
135 pwm@28 {
136 compatible = "maxim,ds1050";
137 reg = <0x28>;
138 };
139 sensor@48 {
140 compatible = "maxim,max6625";
141 reg = <0x48>;
142 };
143 sensor@49 {
144 compatible = "maxim,max6625";
145 reg = <0x49>;
146 };
147 sensor@4b {
148 compatible = "maxim,max6625";
149 reg = <0x4b>;
150 };
151 };
152
153 usb@23000 {
154 compatible = "fsl-usb2-dr";
155 reg = <0x23000 0x1000>;
156 #address-cells = <1>;
157 #size-cells = <0>;
158 interrupt-parent = <&ipic>;
159 interrupts = <38 0x8>;
160 dr_mode = "peripheral";
161 phy_type = "ulpi";
162 };
163
164 enet0: ethernet@24000 {
165 #address-cells = <1>;
166 #size-cells = <1>;
167 ranges = <0x0 0x24000 0x1000>;
168
169 cell-index = <0>;
170 device_type = "network";
171 model = "eTSEC";
172 compatible = "gianfar";
173 reg = <0x24000 0x1000>;
174 local-mac-address = [ 00 00 00 00 00 00 ];
175 interrupts = <32 0x8 33 0x8 34 0x8>;
176 interrupt-parent = <&ipic>;
177 phy-handle = < &phy1 >;
178
179 mdio@520 {
180 #address-cells = <1>;
181 #size-cells = <0>;
182 compatible = "fsl,gianfar-mdio";
183 reg = <0x520 0x20>;
184 phy1: ethernet-phy@1 {
185 interrupt-parent = <&ipic>;
186 interrupts = <17 0x8>;
187 reg = <0x1>;
188 };
189 phy2: ethernet-phy@2 {
190 interrupt-parent = <&ipic>;
191 interrupts = <19 0x8>;
192 reg = <0x2>;
193 };
194 tbi0: tbi-phy@11 {
195 reg = <0x11>;
196 device_type = "tbi-phy";
197 };
198 };
199 };
200
201 enet1: ethernet@25000 {
202 #address-cells = <1>;
203 #size-cells = <1>;
204 cell-index = <1>;
205 device_type = "network";
206 model = "eTSEC";
207 compatible = "gianfar";
208 reg = <0x25000 0x1000>;
209 ranges = <0x0 0x25000 0x1000>;
210 local-mac-address = [ 00 00 00 00 00 00 ];
211 interrupts = <35 0x8 36 0x8 37 0x8>;
212 interrupt-parent = <&ipic>;
213 phy-handle = < &phy2 >;
214
215 mdio@520 {
216 #address-cells = <1>;
217 #size-cells = <0>;
218 compatible = "fsl,gianfar-tbi";
219 reg = <0x520 0x20>;
220 tbi1: tbi-phy@11 {
221 reg = <0x11>;
222 device_type = "tbi-phy";
223 };
224 };
225 };
226
227 serial0: serial@4500 {
228 cell-index = <0>;
229 device_type = "serial";
230 compatible = "fsl,ns16550", "ns16550";
231 reg = <0x4500 0x100>;
232 clock-frequency = <133333333>;
233 interrupts = <9 0x8>;
234 interrupt-parent = <&ipic>;
235 };
236
237 serial1: serial@4600 {
238 cell-index = <1>;
239 device_type = "serial";
240 compatible = "fsl,ns16550", "ns16550";
241 reg = <0x4600 0x100>;
242 clock-frequency = <133333333>;
243 interrupts = <10 0x8>;
244 interrupt-parent = <&ipic>;
245 };
246
247 gpio@c00 {
248 #gpio-cells = <2>;
249 compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
250 reg = <0xc00 0x18>;
251 interrupts = <74 0x8>;
252 interrupt-parent = <&ipic>;
253 gpio-controller;
254 };
255
256 timer@500 {
257 compatible = "fsl,mpc8308-gtm", "fsl,gtm";
258 reg = <0x500 0x100>;
259 interrupts = <90 8 78 8 84 8 72 8>;
260 interrupt-parent = <&ipic>;
261 clock-frequency = <133333333>;
262 };
263
264 /* IPIC
265 * interrupts cell = <intr #, sense>
266 * sense values match linux IORESOURCE_IRQ_* defines:
267 * sense == 8: Level, low assertion
268 * sense == 2: Edge, high-to-low change
269 */
270 ipic: interrupt-controller@700 {
271 compatible = "fsl,ipic";
272 interrupt-controller;
273 #address-cells = <0>;
274 #interrupt-cells = <2>;
275 reg = <0x700 0x100>;
276 device_type = "ipic";
277 };
278
279 ipic-msi@7c0 {
280 compatible = "fsl,ipic-msi";
281 reg = <0x7c0 0x40>;
282 msi-available-ranges = <0x0 0x100>;
283 interrupts = < 0x43 0x8
284 0x4 0x8
285 0x51 0x8
286 0x52 0x8
287 0x56 0x8
288 0x57 0x8
289 0x58 0x8
290 0x59 0x8 >;
291 interrupt-parent = < &ipic >;
292 };
293
294 dma@2c000 {
295 compatible = "fsl,mpc8308-dma";
296 reg = <0x2c000 0x1800>;
297 interrupts = <3 0x8
298 94 0x8>;
299 interrupt-parent = < &ipic >;
300 };
301
302 };
303
304 pci0: pcie@e0009000 {
305 #address-cells = <3>;
306 #size-cells = <2>;
307 #interrupt-cells = <1>;
308 device_type = "pci";
309 compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
310 reg = <0xe0009000 0x00001000
311 0xb0000000 0x01000000>;
312 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
313 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
314 bus-range = <0 0>;
315 interrupt-map-mask = <0 0 0 0>;
316 interrupt-map = <0 0 0 0 &ipic 1 8>;
317 interrupts = <0x1 0x8>;
318 interrupt-parent = <&ipic>;
319 clock-frequency = <0>;
320
321 pcie@0 {
322 #address-cells = <3>;
323 #size-cells = <2>;
324 device_type = "pci";
325 reg = <0 0 0 0 0>;
326 ranges = <0x02000000 0 0xa0000000
327 0x02000000 0 0xa0000000
328 0 0x10000000
329 0x01000000 0 0x00000000
330 0x01000000 0 0x00000000
331 0 0x00800000>;
332 };
333 };
334 };
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