1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2009 Extreme Engineering Solutions, Inc.
4 * Based on TQM8548 device tree
5 *
6 * XPedite5200 PrPMC/XMC module based on MPC8548E
7 */
8
9 /dts-v1/;
10
11 / {
12 model = "xes,xpedite5200";
13 compatible = "xes,xpedite5200", "xes,MPC8548";
14 #address-cells = <1>;
15 #size-cells = <1>;
16
17 aliases {
18 ethernet0 = &enet0;
19 ethernet1 = &enet1;
20 ethernet2 = &enet2;
21 ethernet3 = &enet3;
22
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 PowerPC,8548@0 {
33 device_type = "cpu";
34 reg = <0>;
35 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
39 next-level-cache = <&L2>;
40 };
41 };
42
43 memory {
44 device_type = "memory";
45 reg = <0x0 0x0>; // Filled in by U-Boot
46 };
47
48 soc@ef000000 {
49 #address-cells = <1>;
50 #size-cells = <1>;
51 device_type = "soc";
52 ranges = <0x0 0xef000000 0x100000>;
53 bus-frequency = <0>;
54 compatible = "fsl,mpc8548-immr", "simple-bus";
55
56 ecm-law@0 {
57 compatible = "fsl,ecm-law";
58 reg = <0x0 0x1000>;
59 fsl,num-laws = <12>;
60 };
61
62 ecm@1000 {
63 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
64 reg = <0x1000 0x1000>;
65 interrupts = <17 2>;
66 interrupt-parent = <&mpic>;
67 };
68
69 memory-controller@2000 {
70 compatible = "fsl,mpc8548-memory-controller";
71 reg = <0x2000 0x1000>;
72 interrupt-parent = <&mpic>;
73 interrupts = <18 2>;
74 };
75
76 L2: l2-cache-controller@20000 {
77 compatible = "fsl,mpc8548-l2-cache-controller";
78 reg = <0x20000 0x1000>;
79 cache-line-size = <32>; // 32 bytes
80 cache-size = <0x80000>; // L2, 512K
81 interrupt-parent = <&mpic>;
82 interrupts = <16 2>;
83 };
84
85 /* On-card I2C */
86 i2c@3000 {
87 #address-cells = <1>;
88 #size-cells = <0>;
89 cell-index = <0>;
90 compatible = "fsl-i2c";
91 reg = <0x3000 0x100>;
92 interrupts = <43 2>;
93 interrupt-parent = <&mpic>;
94 dfsrr;
95
96 /*
97 * Board GPIO:
98 * 0: BRD_CFG0 (1: P14 IO present)
99 * 1: BRD_CFG1 (1: FP ethernet present)
100 * 2: BRD_CFG2 (1: XMC IO present)
101 * 3: XMC root complex indicator
102 * 4: Flash boot device indicator
103 * 5: Flash write protect enable
104 * 6: PMC monarch indicator
105 * 7: PMC EREADY
106 */
107 gpio1: gpio@18 {
108 compatible = "nxp,pca9556";
109 reg = <0x18>;
110 #gpio-cells = <2>;
111 gpio-controller;
112 polarity = <0x00>;
113 };
114
115 /* P14 GPIO */
116 gpio2: gpio@19 {
117 compatible = "nxp,pca9556";
118 reg = <0x19>;
119 #gpio-cells = <2>;
120 gpio-controller;
121 polarity = <0x00>;
122 };
123
124 eeprom@50 {
125 compatible = "atmel,at24c16";
126 reg = <0x50>;
127 };
128
129 rtc@68 {
130 compatible = "st,m41t00",
131 "dallas,ds1338";
132 reg = <0x68>;
133 };
134
135 dtt@34 {
136 compatible = "maxim,max1237";
137 reg = <0x34>;
138 };
139 };
140
141 /* Off-card I2C */
142 i2c@3100 {
143 #address-cells = <1>;
144 #size-cells = <0>;
145 cell-index = <1>;
146 compatible = "fsl-i2c";
147 reg = <0x3100 0x100>;
148 interrupts = <43 2>;
149 interrupt-parent = <&mpic>;
150 dfsrr;
151 };
152
153 dma@21300 {
154 #address-cells = <1>;
155 #size-cells = <1>;
156 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
157 reg = <0x21300 0x4>;
158 ranges = <0x0 0x21100 0x200>;
159 cell-index = <0>;
160 dma-channel@0 {
161 compatible = "fsl,mpc8548-dma-channel",
162 "fsl,eloplus-dma-channel";
163 reg = <0x0 0x80>;
164 cell-index = <0>;
165 interrupt-parent = <&mpic>;
166 interrupts = <20 2>;
167 };
168 dma-channel@80 {
169 compatible = "fsl,mpc8548-dma-channel",
170 "fsl,eloplus-dma-channel";
171 reg = <0x80 0x80>;
172 cell-index = <1>;
173 interrupt-parent = <&mpic>;
174 interrupts = <21 2>;
175 };
176 dma-channel@100 {
177 compatible = "fsl,mpc8548-dma-channel",
178 "fsl,eloplus-dma-channel";
179 reg = <0x100 0x80>;
180 cell-index = <2>;
181 interrupt-parent = <&mpic>;
182 interrupts = <22 2>;
183 };
184 dma-channel@180 {
185 compatible = "fsl,mpc8548-dma-channel",
186 "fsl,eloplus-dma-channel";
187 reg = <0x180 0x80>;
188 cell-index = <3>;
189 interrupt-parent = <&mpic>;
190 interrupts = <23 2>;
191 };
192 };
193
194 /* eTSEC1: Front panel port 0 */
195 enet0: ethernet@24000 {
196 #address-cells = <1>;
197 #size-cells = <1>;
198 cell-index = <0>;
199 device_type = "network";
200 model = "eTSEC";
201 compatible = "gianfar";
202 reg = <0x24000 0x1000>;
203 ranges = <0x0 0x24000 0x1000>;
204 local-mac-address = [ 00 00 00 00 00 00 ];
205 interrupts = <29 2 30 2 34 2>;
206 interrupt-parent = <&mpic>;
207 tbi-handle = <&tbi0>;
208 phy-handle = <&phy0>;
209
210 mdio@520 {
211 #address-cells = <1>;
212 #size-cells = <0>;
213 compatible = "fsl,gianfar-mdio";
214 reg = <0x520 0x20>;
215
216 phy0: ethernet-phy@1 {
217 interrupt-parent = <&mpic>;
218 interrupts = <8 1>;
219 reg = <0x1>;
220 };
221 phy1: ethernet-phy@2 {
222 interrupt-parent = <&mpic>;
223 interrupts = <8 1>;
224 reg = <0x2>;
225 };
226 phy2: ethernet-phy@3 {
227 interrupt-parent = <&mpic>;
228 interrupts = <8 1>;
229 reg = <0x3>;
230 };
231 phy3: ethernet-phy@4 {
232 interrupt-parent = <&mpic>;
233 interrupts = <8 1>;
234 reg = <0x4>;
235 };
236 tbi0: tbi-phy@11 {
237 reg = <0x11>;
238 device_type = "tbi-phy";
239 };
240 };
241 };
242
243 /* eTSEC2: Front panel port 1 */
244 enet1: ethernet@25000 {
245 #address-cells = <1>;
246 #size-cells = <1>;
247 cell-index = <1>;
248 device_type = "network";
249 model = "eTSEC";
250 compatible = "gianfar";
251 reg = <0x25000 0x1000>;
252 ranges = <0x0 0x25000 0x1000>;
253 local-mac-address = [ 00 00 00 00 00 00 ];
254 interrupts = <35 2 36 2 40 2>;
255 interrupt-parent = <&mpic>;
256 tbi-handle = <&tbi1>;
257 phy-handle = <&phy1>;
258
259 mdio@520 {
260 #address-cells = <1>;
261 #size-cells = <0>;
262 compatible = "fsl,gianfar-tbi";
263 reg = <0x520 0x20>;
264
265 tbi1: tbi-phy@11 {
266 reg = <0x11>;
267 device_type = "tbi-phy";
268 };
269 };
270 };
271
272 /* eTSEC3: Rear panel port 2 */
273 enet2: ethernet@26000 {
274 #address-cells = <1>;
275 #size-cells = <1>;
276 cell-index = <2>;
277 device_type = "network";
278 model = "eTSEC";
279 compatible = "gianfar";
280 reg = <0x26000 0x1000>;
281 ranges = <0x0 0x26000 0x1000>;
282 local-mac-address = [ 00 00 00 00 00 00 ];
283 interrupts = <31 2 32 2 33 2>;
284 interrupt-parent = <&mpic>;
285 tbi-handle = <&tbi2>;
286 phy-handle = <&phy2>;
287
288 mdio@520 {
289 #address-cells = <1>;
290 #size-cells = <0>;
291 compatible = "fsl,gianfar-tbi";
292 reg = <0x520 0x20>;
293
294 tbi2: tbi-phy@11 {
295 reg = <0x11>;
296 device_type = "tbi-phy";
297 };
298 };
299 };
300
301 /* eTSEC4: Rear panel port 3 */
302 enet3: ethernet@27000 {
303 #address-cells = <1>;
304 #size-cells = <1>;
305 cell-index = <3>;
306 device_type = "network";
307 model = "eTSEC";
308 compatible = "gianfar";
309 reg = <0x27000 0x1000>;
310 ranges = <0x0 0x27000 0x1000>;
311 local-mac-address = [ 00 00 00 00 00 00 ];
312 interrupts = <37 2 38 2 39 2>;
313 interrupt-parent = <&mpic>;
314 tbi-handle = <&tbi3>;
315 phy-handle = <&phy3>;
316
317 mdio@520 {
318 #address-cells = <1>;
319 #size-cells = <0>;
320 compatible = "fsl,gianfar-tbi";
321 reg = <0x520 0x20>;
322
323 tbi3: tbi-phy@11 {
324 reg = <0x11>;
325 device_type = "tbi-phy";
326 };
327 };
328 };
329
330 serial0: serial@4500 {
331 cell-index = <0>;
332 device_type = "serial";
333 compatible = "fsl,ns16550", "ns16550";
334 reg = <0x4500 0x100>;
335 clock-frequency = <0>;
336 current-speed = <115200>;
337 interrupts = <42 2>;
338 interrupt-parent = <&mpic>;
339 };
340
341 serial1: serial@4600 {
342 cell-index = <1>;
343 device_type = "serial";
344 compatible = "fsl,ns16550", "ns16550";
345 reg = <0x4600 0x100>;
346 clock-frequency = <0>;
347 current-speed = <115200>;
348 interrupts = <42 2>;
349 interrupt-parent = <&mpic>;
350 };
351
352 global-utilities@e0000 { // global utilities reg
353 compatible = "fsl,mpc8548-guts";
354 reg = <0xe0000 0x1000>;
355 fsl,has-rstcr;
356 };
357
358 mpic: pic@40000 {
359 interrupt-controller;
360 #address-cells = <0>;
361 #interrupt-cells = <2>;
362 reg = <0x40000 0x40000>;
363 compatible = "chrp,open-pic";
364 device_type = "open-pic";
365 };
366 };
367
368 localbus@ef005000 {
369 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
370 "simple-bus";
371 #address-cells = <2>;
372 #size-cells = <1>;
373 reg = <0xef005000 0x100>; // BRx, ORx, etc.
374 interrupt-parent = <&mpic>;
375 interrupts = <19 2>;
376
377 ranges = <
378 0 0x0 0xfc000000 0x04000000 // NOR boot flash
379 1 0x0 0xf8000000 0x04000000 // NOR expansion flash
380 2 0x0 0xef800000 0x00010000 // NAND CE1
381 3 0x0 0xef840000 0x00010000 // NAND CE2
382 >;
383
384 nor-boot@0,0 {
385 #address-cells = <1>;
386 #size-cells = <1>;
387 compatible = "cfi-flash";
388 reg = <0 0x0 0x4000000>;
389 bank-width = <2>;
390
391 partition@0 {
392 label = "Primary OS";
393 reg = <0x00000000 0x180000>;
394 };
395 partition@180000 {
396 label = "Secondary OS";
397 reg = <0x00180000 0x180000>;
398 };
399 partition@300000 {
400 label = "User";
401 reg = <0x00300000 0x3c80000>;
402 };
403 partition@3f80000 {
404 label = "Boot firmware";
405 reg = <0x03f80000 0x80000>;
406 };
407 };
408
409 nor-alternate@1,0 {
410 #address-cells = <1>;
411 #size-cells = <1>;
412 compatible = "cfi-flash";
413 reg = <1 0x0 0x4000000>;
414 bank-width = <2>;
415
416 partition@0 {
417 label = "Filesystem";
418 reg = <0x00000000 0x3f80000>;
419 };
420 partition@3f80000 {
421 label = "Alternate boot firmware";
422 reg = <0x03f80000 0x80000>;
423 };
424 };
425
426 nand@2,0 {
427 #address-cells = <1>;
428 #size-cells = <1>;
429 compatible = "xes,address-ctl-nand";
430 reg = <2 0x0 0x10000>;
431 cle-line = <0x8>; /* CLE tied to A3 */
432 ale-line = <0x10>; /* ALE tied to A4 */
433
434 /* U-Boot should fix this up */
435 partition@0 {
436 label = "NAND Filesystem";
437 reg = <0 0x40000000>;
438 };
439 };
440 };
441
442 /* PMC interface */
443 pci0: pci@ef008000 {
444 #interrupt-cells = <1>;
445 #size-cells = <2>;
446 #address-cells = <3>;
447 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
448 device_type = "pci";
449 reg = <0xef008000 0x1000>;
450 clock-frequency = <33333333>;
451 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
452 interrupt-map = <
453 /* IDSEL */
454 0xe000 0 0 1 &mpic 2 1
455 0xe000 0 0 2 &mpic 3 1>;
456
457 interrupt-parent = <&mpic>;
458 interrupts = <24 2>;
459 bus-range = <0 0>;
460 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x40000000
461 0x01000000 0 0x00000000 0xe8000000 0 0x00800000>;
462 };
463
464 /* XMC PCIe is not yet enabled in U-Boot on XPedite5200 */
465 };
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