1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
4
5 #include <asm-generic/pgtable-nop4d.h>
6
7 #ifndef __ASSEMBLY__
8 #include <linux/mmdebug.h>
9 #include <linux/bug.h>
10 #include <linux/sizes.h>
11 #endif
12
13 /*
14 * Common bits between hash and Radix page table
15 */
16
17 #define _PAGE_EXEC 0x00001 /* execute permission */
18 #define _PAGE_WRITE 0x00002 /* write access allowed */
19 #define _PAGE_READ 0x00004 /* read access allowed */
20 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */
21 #define _PAGE_SAO 0x00010 /* Strong access order */
22 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */
23 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */
24 #define _PAGE_DIRTY 0x00080 /* C: page changed */
25 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */
26 /*
27 * Software bits
28 */
29 #define _RPAGE_SW0 0x2000000000000000UL
30 #define _RPAGE_SW1 0x00800
31 #define _RPAGE_SW2 0x00400
32 #define _RPAGE_SW3 0x00200
33 #define _RPAGE_RSV1 0x00040UL
34
35 #define _RPAGE_PKEY_BIT4 0x1000000000000000UL
36 #define _RPAGE_PKEY_BIT3 0x0800000000000000UL
37 #define _RPAGE_PKEY_BIT2 0x0400000000000000UL
38 #define _RPAGE_PKEY_BIT1 0x0200000000000000UL
39 #define _RPAGE_PKEY_BIT0 0x0100000000000000UL
40
41 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */
42 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */
43 /*
44 * We need to mark a pmd pte invalid while splitting. We can do that by clearing
45 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to
46 * differentiate between two use a SW field when invalidating.
47 *
48 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags
49 *
50 * This is used only when _PAGE_PRESENT is cleared.
51 */
52 #define _PAGE_INVALID _RPAGE_SW0
53
54 /*
55 * Top and bottom bits of RPN which can be used by hash
56 * translation mode, because we expect them to be zero
57 * otherwise.
58 */
59 #define _RPAGE_RPN0 0x01000
60 #define _RPAGE_RPN1 0x02000
61 #define _RPAGE_RPN43 0x0080000000000000UL
62 #define _RPAGE_RPN42 0x0040000000000000UL
63 #define _RPAGE_RPN41 0x0020000000000000UL
64
65 /* Max physical address bit as per radix table */
66 #define _RPAGE_PA_MAX 56
67
68 /*
69 * Max physical address bit we will use for now.
70 *
71 * This is mostly a hardware limitation and for now Power9 has
72 * a 51 bit limit.
73 *
74 * This is different from the number of physical bit required to address
75 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS.
76 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum
77 * number of sections we can support (SECTIONS_SHIFT).
78 *
79 * This is different from Radix page table limitation above and
80 * should always be less than that. The limit is done such that
81 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX
82 * for hash linux page table specific bits.
83 *
84 * In order to be compatible with future hardware generations we keep
85 * some offsets and limit this for now to 53
86 */
87 #define _PAGE_PA_MAX 53
88
89 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */
90 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
91 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */
92
93 /*
94 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
95 * Instead of fixing all of them, add an alternate define which
96 * maps CI pte mapping.
97 */
98 #define _PAGE_NO_CACHE _PAGE_TOLERANT
99 /*
100 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side
101 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX
102 * and every thing below PAGE_SHIFT;
103 */
104 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK))
105 #define PTE_RPN_SHIFT PAGE_SHIFT
106 /*
107 * set of bits not changed in pmd_modify. Even though we have hash specific bits
108 * in here, on radix we expect them to be zero.
109 */
110 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
111 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \
112 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP)
113 /*
114 * user access blocked by key
115 */
116 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY)
117 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ)
118 #define _PAGE_KERNEL_ROX (_PAGE_PRIVILEGED | _PAGE_READ | _PAGE_EXEC)
119 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC)
120 /*
121 * _PAGE_CHG_MASK masks of bits that are to be preserved across
122 * pgprot changes
123 */
124 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
125 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \
126 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP)
127
128 /*
129 * We define 2 sets of base prot bits, one for basic pages (ie,
130 * cacheable kernel and user pages) and one for non cacheable
131 * pages. We always set _PAGE_COHERENT when SMP is enabled or
132 * the processor might need it for DMA coherency.
133 */
134 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED)
135 #define _PAGE_BASE (_PAGE_BASE_NC)
136
137 #include <asm/pgtable-masks.h>
138
139 /* Permission masks used for kernel mappings */
140 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
141 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_TOLERANT)
142 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NON_IDEMPOTENT)
143 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
144 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
145 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
146
147 #ifndef __ASSEMBLY__
148 /*
149 * page table defines
150 */
151 extern unsigned long __pte_index_size;
152 extern unsigned long __pmd_index_size;
153 extern unsigned long __pud_index_size;
154 extern unsigned long __pgd_index_size;
155 extern unsigned long __pud_cache_index;
156 #define PTE_INDEX_SIZE __pte_index_size
157 #define PMD_INDEX_SIZE __pmd_index_size
158 #define PUD_INDEX_SIZE __pud_index_size
159 #define PGD_INDEX_SIZE __pgd_index_size
160 /* pmd table use page table fragments */
161 #define PMD_CACHE_INDEX 0
162 #define PUD_CACHE_INDEX __pud_cache_index
163 /*
164 * Because of use of pte fragments and THP, size of page table
165 * are not always derived out of index size above.
166 */
167 extern unsigned long __pte_table_size;
168 extern unsigned long __pmd_table_size;
169 extern unsigned long __pud_table_size;
170 extern unsigned long __pgd_table_size;
171 #define PTE_TABLE_SIZE __pte_table_size
172 #define PMD_TABLE_SIZE __pmd_table_size
173 #define PUD_TABLE_SIZE __pud_table_size
174 #define PGD_TABLE_SIZE __pgd_table_size
175
176 extern unsigned long __pmd_val_bits;
177 extern unsigned long __pud_val_bits;
178 extern unsigned long __pgd_val_bits;
179 #define PMD_VAL_BITS __pmd_val_bits
180 #define PUD_VAL_BITS __pud_val_bits
181 #define PGD_VAL_BITS __pgd_val_bits
182
183 extern unsigned long __pte_frag_nr;
184 #define PTE_FRAG_NR __pte_frag_nr
185 extern unsigned long __pte_frag_size_shift;
186 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift
187 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
188
189 extern unsigned long __pmd_frag_nr;
190 #define PMD_FRAG_NR __pmd_frag_nr
191 extern unsigned long __pmd_frag_size_shift;
192 #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift
193 #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT)
194
195 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
196 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
197 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)
198 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
199
200 #define MAX_PTRS_PER_PTE ((H_PTRS_PER_PTE > R_PTRS_PER_PTE) ? H_PTRS_PER_PTE : R_PTRS_PER_PTE)
201 #define MAX_PTRS_PER_PMD ((H_PTRS_PER_PMD > R_PTRS_PER_PMD) ? H_PTRS_PER_PMD : R_PTRS_PER_PMD)
202 #define MAX_PTRS_PER_PUD ((H_PTRS_PER_PUD > R_PTRS_PER_PUD) ? H_PTRS_PER_PUD : R_PTRS_PER_PUD)
203 #define MAX_PTRS_PER_PGD (1 << (H_PGD_INDEX_SIZE > RADIX_PGD_INDEX_SIZE ? \
204 H_PGD_INDEX_SIZE : RADIX_PGD_INDEX_SIZE))
205
206 /* PMD_SHIFT determines what a second-level page table entry can map */
207 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
208 #define PMD_SIZE (1UL << PMD_SHIFT)
209 #define PMD_MASK (~(PMD_SIZE-1))
210
211 /* PUD_SHIFT determines what a third-level page table entry can map */
212 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
213 #define PUD_SIZE (1UL << PUD_SHIFT)
214 #define PUD_MASK (~(PUD_SIZE-1))
215
216 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */
217 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
218 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
219 #define PGDIR_MASK (~(PGDIR_SIZE-1))
220
221 /* Bits to mask out from a PMD to get to the PTE page */
222 #define PMD_MASKED_BITS 0xc0000000000000ffUL
223 /* Bits to mask out from a PUD to get to the PMD page */
224 #define PUD_MASKED_BITS 0xc0000000000000ffUL
225 /* Bits to mask out from a PGD to get to the PUD page */
226 #define P4D_MASKED_BITS 0xc0000000000000ffUL
227
228 /*
229 * Used as an indicator for rcu callback functions
230 */
231 enum pgtable_index {
232 PTE_INDEX = 0,
233 PMD_INDEX,
234 PUD_INDEX,
235 PGD_INDEX,
236 /*
237 * Below are used with 4k page size and hugetlb
238 */
239 HTLB_16M_INDEX,
240 HTLB_16G_INDEX,
241 };
242
243 extern unsigned long __vmalloc_start;
244 extern unsigned long __vmalloc_end;
245 #define VMALLOC_START __vmalloc_start
246 #define VMALLOC_END __vmalloc_end
247
248 static inline unsigned int ioremap_max_order(void)
249 {
250 if (radix_enabled())
251 return PUD_SHIFT;
252 return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */
253 }
254 #define IOREMAP_MAX_ORDER ioremap_max_order()
255
256 extern unsigned long __kernel_virt_start;
257 extern unsigned long __kernel_io_start;
258 extern unsigned long __kernel_io_end;
259 #define KERN_VIRT_START __kernel_virt_start
260 #define KERN_IO_START __kernel_io_start
261 #define KERN_IO_END __kernel_io_end
262
263 extern struct page *vmemmap;
264 extern unsigned long pci_io_base;
265
266 #define pmd_leaf pmd_leaf
267 static inline bool pmd_leaf(pmd_t pmd)
268 {
269 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE));
270 }
271
272 #define pud_leaf pud_leaf
273 static inline bool pud_leaf(pud_t pud)
274 {
275 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE));
276 }
277
278 #define pmd_leaf_size pmd_leaf_size
279 static inline unsigned long pmd_leaf_size(pmd_t pmd)
280 {
281 if (IS_ENABLED(CONFIG_PPC_4K_PAGES) && !radix_enabled())
282 return SZ_16M;
283 else
284 return PMD_SIZE;
285 }
286
287 #define pud_leaf_size pud_leaf_size
288 static inline unsigned long pud_leaf_size(pud_t pud)
289 {
290 if (IS_ENABLED(CONFIG_PPC_4K_PAGES) && !radix_enabled())
291 return SZ_16G;
292 else
293 return PUD_SIZE;
294 }
295 #endif /* __ASSEMBLY__ */
296
297 #include <asm/book3s/64/hash.h>
298 #include <asm/book3s/64/radix.h>
299
300 #if H_MAX_PHYSMEM_BITS > R_MAX_PHYSMEM_BITS
301 #define MAX_PHYSMEM_BITS H_MAX_PHYSMEM_BITS
302 #else
303 #define MAX_PHYSMEM_BITS R_MAX_PHYSMEM_BITS
304 #endif
305
306 /* hash 4k can't share hugetlb and also doesn't support THP */
307 #ifdef CONFIG_PPC_64K_PAGES
308 #include <asm/book3s/64/pgtable-64k.h>
309 #endif
310
311 #include <asm/barrier.h>
312 /*
313 * IO space itself carved into the PIO region (ISA and PHB IO space) and
314 * the ioremap space
315 *
316 * ISA_IO_BASE = KERN_IO_START, 64K reserved area
317 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
318 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
319 */
320 #define FULL_IO_SIZE 0x80000000ul
321 #define ISA_IO_BASE (KERN_IO_START)
322 #define ISA_IO_END (KERN_IO_START + 0x10000ul)
323 #define PHB_IO_BASE (ISA_IO_END)
324 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE)
325 #define IOREMAP_BASE (PHB_IO_END)
326 #define IOREMAP_START (ioremap_bot)
327 #define IOREMAP_END (KERN_IO_END - FIXADDR_SIZE)
328 #define FIXADDR_SIZE SZ_32M
329 #define FIXADDR_TOP (IOREMAP_END + FIXADDR_SIZE)
330
331 #ifndef __ASSEMBLY__
332
333 /*
334 * This is the default implementation of various PTE accessors, it's
335 * used in all cases except Book3S with 64K pages where we have a
336 * concept of sub-pages
337 */
338 #ifndef __real_pte
339
340 #define __real_pte(e, p, o) ((real_pte_t){(e)})
341 #define __rpte_to_pte(r) ((r).pte)
342 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT)
343
344 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
345 do { \
346 index = 0; \
347 shift = mmu_psize_defs[psize].shift; \
348
349 #define pte_iterate_hashed_end() } while(0)
350
351 /*
352 * We expect this to be called only for user addresses or kernel virtual
353 * addresses other than the linear mapping.
354 */
355 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
356
357 #endif /* __real_pte */
358
359 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr,
360 pte_t *ptep, unsigned long clr,
361 unsigned long set, int huge)
362 {
363 if (radix_enabled())
364 return radix__pte_update(mm, addr, ptep, clr, set, huge);
365 return hash__pte_update(mm, addr, ptep, clr, set, huge);
366 }
367 /*
368 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update.
369 * We currently remove entries from the hashtable regardless of whether
370 * the entry was young or dirty.
371 *
372 * We should be more intelligent about this but for the moment we override
373 * these functions and force a tlb flush unconditionally
374 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same
375 * function for both hash and radix.
376 */
377 static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
378 unsigned long addr, pte_t *ptep)
379 {
380 unsigned long old;
381
382 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
383 return 0;
384 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
385 return (old & _PAGE_ACCESSED) != 0;
386 }
387
388 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
389 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
390 ({ \
391 __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
392 })
393
394 /*
395 * On Book3S CPUs, clearing the accessed bit without a TLB flush
396 * doesn't cause data corruption. [ It could cause incorrect
397 * page aging and the (mistaken) reclaim of hot pages, but the
398 * chance of that should be relatively low. ]
399 *
400 * So as a performance optimization don't flush the TLB when
401 * clearing the accessed bit, it will eventually be flushed by
402 * a context switch or a VM operation anyway. [ In the rare
403 * event of it not getting flushed for a long time the delay
404 * shouldn't really matter because there's no real memory
405 * pressure for swapout to react to. ]
406 *
407 * Note: this optimisation also exists in pte_needs_flush() and
408 * huge_pmd_needs_flush().
409 */
410 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
411 #define ptep_clear_flush_young ptep_test_and_clear_young
412
413 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
414 #define pmdp_clear_flush_young pmdp_test_and_clear_young
415
416 static inline int pte_write(pte_t pte)
417 {
418 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE));
419 }
420
421 static inline int pte_read(pte_t pte)
422 {
423 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ));
424 }
425
426 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
427 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
428 pte_t *ptep)
429 {
430 if (pte_write(*ptep))
431 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0);
432 }
433
434 #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT
435 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
436 unsigned long addr, pte_t *ptep)
437 {
438 if (pte_write(*ptep))
439 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1);
440 }
441
442 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
443 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
444 unsigned long addr, pte_t *ptep)
445 {
446 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
447 return __pte(old);
448 }
449
450 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
451 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
452 unsigned long addr,
453 pte_t *ptep, int full)
454 {
455 if (full && radix_enabled()) {
456 /*
457 * We know that this is a full mm pte clear and
458 * hence can be sure there is no parallel set_pte.
459 */
460 return radix__ptep_get_and_clear_full(mm, addr, ptep, full);
461 }
462 return ptep_get_and_clear(mm, addr, ptep);
463 }
464
465
466 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
467 pte_t * ptep)
468 {
469 pte_update(mm, addr, ptep, ~0UL, 0, 0);
470 }
471
472 static inline int pte_dirty(pte_t pte)
473 {
474 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY));
475 }
476
477 static inline int pte_young(pte_t pte)
478 {
479 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED));
480 }
481
482 static inline int pte_special(pte_t pte)
483 {
484 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL));
485 }
486
487 static inline bool pte_exec(pte_t pte)
488 {
489 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC));
490 }
491
492
493 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
494 static inline bool pte_soft_dirty(pte_t pte)
495 {
496 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY));
497 }
498
499 static inline pte_t pte_mksoft_dirty(pte_t pte)
500 {
501 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY));
502 }
503
504 static inline pte_t pte_clear_soft_dirty(pte_t pte)
505 {
506 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY));
507 }
508 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
509
510 #ifdef CONFIG_NUMA_BALANCING
511 static inline int pte_protnone(pte_t pte)
512 {
513 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) ==
514 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE);
515 }
516 #endif /* CONFIG_NUMA_BALANCING */
517
518 static inline bool pte_hw_valid(pte_t pte)
519 {
520 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE)) ==
521 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE);
522 }
523
524 static inline int pte_present(pte_t pte)
525 {
526 /*
527 * A pte is considerent present if _PAGE_PRESENT is set.
528 * We also need to consider the pte present which is marked
529 * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID
530 * if we find _PAGE_PRESENT cleared.
531 */
532
533 if (pte_hw_valid(pte))
534 return true;
535 return (pte_raw(pte) & cpu_to_be64(_PAGE_INVALID | _PAGE_PTE)) ==
536 cpu_to_be64(_PAGE_INVALID | _PAGE_PTE);
537 }
538
539 #ifdef CONFIG_PPC_MEM_KEYS
540 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute);
541 #else
542 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute)
543 {
544 return true;
545 }
546 #endif /* CONFIG_PPC_MEM_KEYS */
547
548 static inline bool pte_user(pte_t pte)
549 {
550 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED));
551 }
552
553 #define pte_access_permitted pte_access_permitted
554 static inline bool pte_access_permitted(pte_t pte, bool write)
555 {
556 /*
557 * _PAGE_READ is needed for any access and will be cleared for
558 * PROT_NONE. Execute-only mapping via PROT_EXEC also returns false.
559 */
560 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte))
561 return false;
562
563 if (write && !pte_write(pte))
564 return false;
565
566 return arch_pte_access_permitted(pte_val(pte), write, 0);
567 }
568
569 /*
570 * Conversion functions: convert a page and protection to a page entry,
571 * and a page entry and page directory to the page they refer to.
572 *
573 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
574 * long for now.
575 */
576 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
577 {
578 VM_BUG_ON(pfn >> (64 - PAGE_SHIFT));
579 VM_BUG_ON((pfn << PAGE_SHIFT) & ~PTE_RPN_MASK);
580
581 return __pte(((pte_basic_t)pfn << PAGE_SHIFT) | pgprot_val(pgprot) | _PAGE_PTE);
582 }
583
584 /* Generic modifiers for PTE bits */
585 static inline pte_t pte_wrprotect(pte_t pte)
586 {
587 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE));
588 }
589
590 static inline pte_t pte_exprotect(pte_t pte)
591 {
592 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC));
593 }
594
595 static inline pte_t pte_mkclean(pte_t pte)
596 {
597 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY));
598 }
599
600 static inline pte_t pte_mkold(pte_t pte)
601 {
602 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED));
603 }
604
605 static inline pte_t pte_mkexec(pte_t pte)
606 {
607 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC));
608 }
609
610 static inline pte_t pte_mkwrite_novma(pte_t pte)
611 {
612 /*
613 * write implies read, hence set both
614 */
615 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW));
616 }
617
618 static inline pte_t pte_mkdirty(pte_t pte)
619 {
620 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY));
621 }
622
623 static inline pte_t pte_mkyoung(pte_t pte)
624 {
625 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED));
626 }
627
628 static inline pte_t pte_mkspecial(pte_t pte)
629 {
630 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL));
631 }
632
633 static inline pte_t pte_mkhuge(pte_t pte)
634 {
635 return pte;
636 }
637
638 static inline pte_t pte_mkdevmap(pte_t pte)
639 {
640 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP));
641 }
642
643 /*
644 * This is potentially called with a pmd as the argument, in which case it's not
645 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set.
646 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software
647 * use in page directory entries (ie. non-ptes).
648 */
649 static inline int pte_devmap(pte_t pte)
650 {
651 __be64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE);
652
653 return (pte_raw(pte) & mask) == mask;
654 }
655
656 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
657 {
658 /* FIXME!! check whether this need to be a conditional */
659 return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) |
660 cpu_to_be64(pgprot_val(newprot)));
661 }
662
663 /* Encode and de-code a swap entry */
664 #define MAX_SWAPFILES_CHECK() do { \
665 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
666 /* \
667 * Don't have overlapping bits with _PAGE_HPTEFLAGS \
668 * We filter HPTEFLAGS on set_pte. \
669 */ \
670 BUILD_BUG_ON(_PAGE_HPTEFLAGS & SWP_TYPE_MASK); \
671 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \
672 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_EXCLUSIVE); \
673 } while (0)
674
675 #define SWP_TYPE_BITS 5
676 #define SWP_TYPE_MASK ((1UL << SWP_TYPE_BITS) - 1)
677 #define __swp_type(x) ((x).val & SWP_TYPE_MASK)
678 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT)
679 #define __swp_entry(type, offset) ((swp_entry_t) { \
680 (type) | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)})
681 /*
682 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from
683 * swap type and offset we get from swap and convert that to pte to find a
684 * matching pte in linux page table.
685 * Clear bits not found in swap entries here.
686 */
687 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE })
688 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE)
689 #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd)))
690 #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x)))
691
692 #ifdef CONFIG_MEM_SOFT_DIRTY
693 #define _PAGE_SWP_SOFT_DIRTY _PAGE_SOFT_DIRTY
694 #else
695 #define _PAGE_SWP_SOFT_DIRTY 0UL
696 #endif /* CONFIG_MEM_SOFT_DIRTY */
697
698 #define _PAGE_SWP_EXCLUSIVE _PAGE_NON_IDEMPOTENT
699
700 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
701 static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
702 {
703 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY));
704 }
705
706 static inline bool pte_swp_soft_dirty(pte_t pte)
707 {
708 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY));
709 }
710
711 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
712 {
713 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY));
714 }
715 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
716
717 static inline pte_t pte_swp_mkexclusive(pte_t pte)
718 {
719 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_EXCLUSIVE));
720 }
721
722 static inline int pte_swp_exclusive(pte_t pte)
723 {
724 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_EXCLUSIVE));
725 }
726
727 static inline pte_t pte_swp_clear_exclusive(pte_t pte)
728 {
729 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_EXCLUSIVE));
730 }
731
732 static inline bool check_pte_access(unsigned long access, unsigned long ptev)
733 {
734 /*
735 * This check for _PAGE_RWX and _PAGE_PRESENT bits
736 */
737 if (access & ~ptev)
738 return false;
739 /*
740 * This check for access to privilege space
741 */
742 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED))
743 return false;
744
745 return true;
746 }
747 /*
748 * Generic functions with hash/radix callbacks
749 */
750
751 static inline void __ptep_set_access_flags(struct vm_area_struct *vma,
752 pte_t *ptep, pte_t entry,
753 unsigned long address,
754 int psize)
755 {
756 if (radix_enabled())
757 return radix__ptep_set_access_flags(vma, ptep, entry,
758 address, psize);
759 return hash__ptep_set_access_flags(ptep, entry);
760 }
761
762 #define __HAVE_ARCH_PTE_SAME
763 static inline int pte_same(pte_t pte_a, pte_t pte_b)
764 {
765 if (radix_enabled())
766 return radix__pte_same(pte_a, pte_b);
767 return hash__pte_same(pte_a, pte_b);
768 }
769
770 static inline int pte_none(pte_t pte)
771 {
772 if (radix_enabled())
773 return radix__pte_none(pte);
774 return hash__pte_none(pte);
775 }
776
777 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
778 pte_t *ptep, pte_t pte, int percpu)
779 {
780
781 VM_WARN_ON(!(pte_raw(pte) & cpu_to_be64(_PAGE_PTE)));
782 /*
783 * Keep the _PAGE_PTE added till we are sure we handle _PAGE_PTE
784 * in all the callers.
785 */
786 pte = __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE));
787
788 if (radix_enabled())
789 return radix__set_pte_at(mm, addr, ptep, pte, percpu);
790 return hash__set_pte_at(mm, addr, ptep, pte, percpu);
791 }
792
793 #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)
794
795 #define pgprot_noncached pgprot_noncached
796 static inline pgprot_t pgprot_noncached(pgprot_t prot)
797 {
798 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
799 _PAGE_NON_IDEMPOTENT);
800 }
801
802 #define pgprot_noncached_wc pgprot_noncached_wc
803 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
804 {
805 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
806 _PAGE_TOLERANT);
807 }
808
809 #define pgprot_cached pgprot_cached
810 static inline pgprot_t pgprot_cached(pgprot_t prot)
811 {
812 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL));
813 }
814
815 #define pgprot_writecombine pgprot_writecombine
816 static inline pgprot_t pgprot_writecombine(pgprot_t prot)
817 {
818 return pgprot_noncached_wc(prot);
819 }
820 /*
821 * check a pte mapping have cache inhibited property
822 */
823 static inline bool pte_ci(pte_t pte)
824 {
825 __be64 pte_v = pte_raw(pte);
826
827 if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) ||
828 ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT)))
829 return true;
830 return false;
831 }
832
833 static inline void pmd_clear(pmd_t *pmdp)
834 {
835 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) {
836 /*
837 * Don't use this if we can possibly have a hash page table
838 * entry mapping this.
839 */
840 WARN_ON((pmd_val(*pmdp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE));
841 }
842 *pmdp = __pmd(0);
843 }
844
845 static inline int pmd_none(pmd_t pmd)
846 {
847 return !pmd_raw(pmd);
848 }
849
850 static inline int pmd_present(pmd_t pmd)
851 {
852 /*
853 * A pmd is considerent present if _PAGE_PRESENT is set.
854 * We also need to consider the pmd present which is marked
855 * invalid during a split. Hence we look for _PAGE_INVALID
856 * if we find _PAGE_PRESENT cleared.
857 */
858 if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID))
859 return true;
860
861 return false;
862 }
863
864 static inline int pmd_is_serializing(pmd_t pmd)
865 {
866 /*
867 * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear
868 * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate).
869 *
870 * This condition may also occur when flushing a pmd while flushing
871 * it (see ptep_modify_prot_start), so callers must ensure this
872 * case is fine as well.
873 */
874 if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) ==
875 cpu_to_be64(_PAGE_INVALID))
876 return true;
877
878 return false;
879 }
880
881 static inline int pmd_bad(pmd_t pmd)
882 {
883 if (radix_enabled())
884 return radix__pmd_bad(pmd);
885 return hash__pmd_bad(pmd);
886 }
887
888 static inline void pud_clear(pud_t *pudp)
889 {
890 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) {
891 /*
892 * Don't use this if we can possibly have a hash page table
893 * entry mapping this.
894 */
895 WARN_ON((pud_val(*pudp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE));
896 }
897 *pudp = __pud(0);
898 }
899
900 static inline int pud_none(pud_t pud)
901 {
902 return !pud_raw(pud);
903 }
904
905 static inline int pud_present(pud_t pud)
906 {
907 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT));
908 }
909
910 extern struct page *pud_page(pud_t pud);
911 extern struct page *pmd_page(pmd_t pmd);
912 static inline pte_t pud_pte(pud_t pud)
913 {
914 return __pte_raw(pud_raw(pud));
915 }
916
917 static inline pud_t pte_pud(pte_t pte)
918 {
919 return __pud_raw(pte_raw(pte));
920 }
921
922 static inline pte_t *pudp_ptep(pud_t *pud)
923 {
924 return (pte_t *)pud;
925 }
926
927 #define pud_pfn(pud) pte_pfn(pud_pte(pud))
928 #define pud_dirty(pud) pte_dirty(pud_pte(pud))
929 #define pud_young(pud) pte_young(pud_pte(pud))
930 #define pud_mkold(pud) pte_pud(pte_mkold(pud_pte(pud)))
931 #define pud_wrprotect(pud) pte_pud(pte_wrprotect(pud_pte(pud)))
932 #define pud_mkdirty(pud) pte_pud(pte_mkdirty(pud_pte(pud)))
933 #define pud_mkclean(pud) pte_pud(pte_mkclean(pud_pte(pud)))
934 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud)))
935 #define pud_mkwrite(pud) pte_pud(pte_mkwrite_novma(pud_pte(pud)))
936 #define pud_write(pud) pte_write(pud_pte(pud))
937
938 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
939 #define pud_soft_dirty(pmd) pte_soft_dirty(pud_pte(pud))
940 #define pud_mksoft_dirty(pmd) pte_pud(pte_mksoft_dirty(pud_pte(pud)))
941 #define pud_clear_soft_dirty(pmd) pte_pud(pte_clear_soft_dirty(pud_pte(pud)))
942 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
943
944 static inline int pud_bad(pud_t pud)
945 {
946 if (radix_enabled())
947 return radix__pud_bad(pud);
948 return hash__pud_bad(pud);
949 }
950
951 #define pud_access_permitted pud_access_permitted
952 static inline bool pud_access_permitted(pud_t pud, bool write)
953 {
954 return pte_access_permitted(pud_pte(pud), write);
955 }
956
957 #define __p4d_raw(x) ((p4d_t) { __pgd_raw(x) })
958 static inline __be64 p4d_raw(p4d_t x)
959 {
960 return pgd_raw(x.pgd);
961 }
962
963 #define p4d_write(p4d) pte_write(p4d_pte(p4d))
964
965 static inline void p4d_clear(p4d_t *p4dp)
966 {
967 *p4dp = __p4d(0);
968 }
969
970 static inline int p4d_none(p4d_t p4d)
971 {
972 return !p4d_raw(p4d);
973 }
974
975 static inline int p4d_present(p4d_t p4d)
976 {
977 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PRESENT));
978 }
979
980 static inline pte_t p4d_pte(p4d_t p4d)
981 {
982 return __pte_raw(p4d_raw(p4d));
983 }
984
985 static inline p4d_t pte_p4d(pte_t pte)
986 {
987 return __p4d_raw(pte_raw(pte));
988 }
989
990 static inline int p4d_bad(p4d_t p4d)
991 {
992 if (radix_enabled())
993 return radix__p4d_bad(p4d);
994 return hash__p4d_bad(p4d);
995 }
996
997 #define p4d_access_permitted p4d_access_permitted
998 static inline bool p4d_access_permitted(p4d_t p4d, bool write)
999 {
1000 return pte_access_permitted(p4d_pte(p4d), write);
1001 }
1002
1003 extern struct page *p4d_page(p4d_t p4d);
1004
1005 /* Pointers in the page table tree are physical addresses */
1006 #define __pgtable_ptr_val(ptr) __pa(ptr)
1007
1008 static inline pud_t *p4d_pgtable(p4d_t p4d)
1009 {
1010 return (pud_t *)__va(p4d_val(p4d) & ~P4D_MASKED_BITS);
1011 }
1012
1013 static inline pmd_t *pud_pgtable(pud_t pud)
1014 {
1015 return (pmd_t *)__va(pud_val(pud) & ~PUD_MASKED_BITS);
1016 }
1017
1018 #define pmd_ERROR(e) \
1019 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
1020 #define pud_ERROR(e) \
1021 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
1022 #define pgd_ERROR(e) \
1023 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
1024
1025 static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot)
1026 {
1027 if (radix_enabled()) {
1028 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM)
1029 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift;
1030 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE");
1031 #endif
1032 return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE);
1033 }
1034 return hash__map_kernel_page(ea, pa, prot);
1035 }
1036
1037 void unmap_kernel_page(unsigned long va);
1038
1039 static inline int __meminit vmemmap_create_mapping(unsigned long start,
1040 unsigned long page_size,
1041 unsigned long phys)
1042 {
1043 if (radix_enabled())
1044 return radix__vmemmap_create_mapping(start, page_size, phys);
1045 return hash__vmemmap_create_mapping(start, page_size, phys);
1046 }
1047
1048 #ifdef CONFIG_MEMORY_HOTPLUG
1049 static inline void vmemmap_remove_mapping(unsigned long start,
1050 unsigned long page_size)
1051 {
1052 if (radix_enabled())
1053 return radix__vmemmap_remove_mapping(start, page_size);
1054 return hash__vmemmap_remove_mapping(start, page_size);
1055 }
1056 #endif
1057
1058 static inline pte_t pmd_pte(pmd_t pmd)
1059 {
1060 return __pte_raw(pmd_raw(pmd));
1061 }
1062
1063 static inline pmd_t pte_pmd(pte_t pte)
1064 {
1065 return __pmd_raw(pte_raw(pte));
1066 }
1067
1068 static inline pte_t *pmdp_ptep(pmd_t *pmd)
1069 {
1070 return (pte_t *)pmd;
1071 }
1072 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd))
1073 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
1074 #define pmd_young(pmd) pte_young(pmd_pte(pmd))
1075 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
1076 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
1077 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
1078 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
1079 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
1080 #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd)))
1081
1082 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
1083 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd))
1084 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)))
1085 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)))
1086
1087 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
1088 #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)))
1089 #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd))
1090 #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)))
1091 #endif
1092 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
1093
1094 #ifdef CONFIG_NUMA_BALANCING
1095 static inline int pmd_protnone(pmd_t pmd)
1096 {
1097 return pte_protnone(pmd_pte(pmd));
1098 }
1099 #endif /* CONFIG_NUMA_BALANCING */
1100
1101 #define pmd_write(pmd) pte_write(pmd_pte(pmd))
1102
1103 #define pmd_access_permitted pmd_access_permitted
1104 static inline bool pmd_access_permitted(pmd_t pmd, bool write)
1105 {
1106 /*
1107 * pmdp_invalidate sets this combination (which is not caught by
1108 * !pte_present() check in pte_access_permitted), to prevent
1109 * lock-free lookups, as part of the serialize_against_pte_lookup()
1110 * synchronisation.
1111 *
1112 * This also catches the case where the PTE's hardware PRESENT bit is
1113 * cleared while TLB is flushed, which is suboptimal but should not
1114 * be frequent.
1115 */
1116 if (pmd_is_serializing(pmd))
1117 return false;
1118
1119 return pte_access_permitted(pmd_pte(pmd), write);
1120 }
1121
1122 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1123 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot);
1124 extern pud_t pfn_pud(unsigned long pfn, pgprot_t pgprot);
1125 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot);
1126 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot);
1127 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1128 pmd_t *pmdp, pmd_t pmd);
1129 extern void set_pud_at(struct mm_struct *mm, unsigned long addr,
1130 pud_t *pudp, pud_t pud);
1131
1132 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
1133 unsigned long addr, pmd_t *pmd)
1134 {
1135 }
1136
1137 static inline void update_mmu_cache_pud(struct vm_area_struct *vma,
1138 unsigned long addr, pud_t *pud)
1139 {
1140 }
1141
1142 extern int hash__has_transparent_hugepage(void);
1143 static inline int has_transparent_hugepage(void)
1144 {
1145 if (radix_enabled())
1146 return radix__has_transparent_hugepage();
1147 return hash__has_transparent_hugepage();
1148 }
1149 #define has_transparent_hugepage has_transparent_hugepage
1150
1151 static inline int has_transparent_pud_hugepage(void)
1152 {
1153 if (radix_enabled())
1154 return radix__has_transparent_pud_hugepage();
1155 return 0;
1156 }
1157 #define has_transparent_pud_hugepage has_transparent_pud_hugepage
1158
1159 static inline unsigned long
1160 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp,
1161 unsigned long clr, unsigned long set)
1162 {
1163 if (radix_enabled())
1164 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set);
1165 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set);
1166 }
1167
1168 static inline unsigned long
1169 pud_hugepage_update(struct mm_struct *mm, unsigned long addr, pud_t *pudp,
1170 unsigned long clr, unsigned long set)
1171 {
1172 if (radix_enabled())
1173 return radix__pud_hugepage_update(mm, addr, pudp, clr, set);
1174 BUG();
1175 return pud_val(*pudp);
1176 }
1177
1178 /*
1179 * For radix we should always find H_PAGE_HASHPTE zero. Hence
1180 * the below will work for radix too
1181 */
1182 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm,
1183 unsigned long addr, pmd_t *pmdp)
1184 {
1185 unsigned long old;
1186
1187 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
1188 return 0;
1189 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0);
1190 return ((old & _PAGE_ACCESSED) != 0);
1191 }
1192
1193 static inline int __pudp_test_and_clear_young(struct mm_struct *mm,
1194 unsigned long addr, pud_t *pudp)
1195 {
1196 unsigned long old;
1197
1198 if ((pud_raw(*pudp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
1199 return 0;
1200 old = pud_hugepage_update(mm, addr, pudp, _PAGE_ACCESSED, 0);
1201 return ((old & _PAGE_ACCESSED) != 0);
1202 }
1203
1204 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
1205 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
1206 pmd_t *pmdp)
1207 {
1208 if (pmd_write(*pmdp))
1209 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0);
1210 }
1211
1212 #define __HAVE_ARCH_PUDP_SET_WRPROTECT
1213 static inline void pudp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
1214 pud_t *pudp)
1215 {
1216 if (pud_write(*pudp))
1217 pud_hugepage_update(mm, addr, pudp, _PAGE_WRITE, 0);
1218 }
1219
1220 /*
1221 * Only returns true for a THP. False for pmd migration entry.
1222 * We also need to return true when we come across a pte that
1223 * in between a thp split. While splitting THP, we mark the pmd
1224 * invalid (pmdp_invalidate()) before we set it with pte page
1225 * address. A pmd_trans_huge() check against a pmd entry during that time
1226 * should return true.
1227 * We should not call this on a hugetlb entry. We should check for HugeTLB
1228 * entry using vma->vm_flags
1229 * The page table walk rule is explained in Documentation/mm/transhuge.rst
1230 */
1231 static inline int pmd_trans_huge(pmd_t pmd)
1232 {
1233 if (!pmd_present(pmd))
1234 return false;
1235
1236 if (radix_enabled())
1237 return radix__pmd_trans_huge(pmd);
1238 return hash__pmd_trans_huge(pmd);
1239 }
1240
1241 static inline int pud_trans_huge(pud_t pud)
1242 {
1243 if (!pud_present(pud))
1244 return false;
1245
1246 if (radix_enabled())
1247 return radix__pud_trans_huge(pud);
1248 return 0;
1249 }
1250
1251
1252 #define __HAVE_ARCH_PMD_SAME
1253 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
1254 {
1255 if (radix_enabled())
1256 return radix__pmd_same(pmd_a, pmd_b);
1257 return hash__pmd_same(pmd_a, pmd_b);
1258 }
1259
1260 #define pud_same pud_same
1261 static inline int pud_same(pud_t pud_a, pud_t pud_b)
1262 {
1263 if (radix_enabled())
1264 return radix__pud_same(pud_a, pud_b);
1265 return hash__pud_same(pud_a, pud_b);
1266 }
1267
1268
1269 static inline pmd_t __pmd_mkhuge(pmd_t pmd)
1270 {
1271 if (radix_enabled())
1272 return radix__pmd_mkhuge(pmd);
1273 return hash__pmd_mkhuge(pmd);
1274 }
1275
1276 static inline pud_t __pud_mkhuge(pud_t pud)
1277 {
1278 if (radix_enabled())
1279 return radix__pud_mkhuge(pud);
1280 BUG();
1281 return pud;
1282 }
1283
1284 /*
1285 * pfn_pmd return a pmd_t that can be used as pmd pte entry.
1286 */
1287 static inline pmd_t pmd_mkhuge(pmd_t pmd)
1288 {
1289 #ifdef CONFIG_DEBUG_VM
1290 if (radix_enabled())
1291 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)) == 0);
1292 else
1293 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)) !=
1294 cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE));
1295 #endif
1296 return pmd;
1297 }
1298
1299 static inline pud_t pud_mkhuge(pud_t pud)
1300 {
1301 #ifdef CONFIG_DEBUG_VM
1302 if (radix_enabled())
1303 WARN_ON((pud_raw(pud) & cpu_to_be64(_PAGE_PTE)) == 0);
1304 else
1305 WARN_ON(1);
1306 #endif
1307 return pud;
1308 }
1309
1310
1311 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
1312 extern int pmdp_set_access_flags(struct vm_area_struct *vma,
1313 unsigned long address, pmd_t *pmdp,
1314 pmd_t entry, int dirty);
1315 #define __HAVE_ARCH_PUDP_SET_ACCESS_FLAGS
1316 extern int pudp_set_access_flags(struct vm_area_struct *vma,
1317 unsigned long address, pud_t *pudp,
1318 pud_t entry, int dirty);
1319
1320 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1321 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1322 unsigned long address, pmd_t *pmdp);
1323 #define __HAVE_ARCH_PUDP_TEST_AND_CLEAR_YOUNG
1324 extern int pudp_test_and_clear_young(struct vm_area_struct *vma,
1325 unsigned long address, pud_t *pudp);
1326
1327
1328 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
1329 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
1330 unsigned long addr, pmd_t *pmdp)
1331 {
1332 if (radix_enabled())
1333 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp);
1334 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp);
1335 }
1336
1337 #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR
1338 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm,
1339 unsigned long addr, pud_t *pudp)
1340 {
1341 if (radix_enabled())
1342 return radix__pudp_huge_get_and_clear(mm, addr, pudp);
1343 BUG();
1344 return *pudp;
1345 }
1346
1347 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
1348 unsigned long address, pmd_t *pmdp)
1349 {
1350 if (radix_enabled())
1351 return radix__pmdp_collapse_flush(vma, address, pmdp);
1352 return hash__pmdp_collapse_flush(vma, address, pmdp);
1353 }
1354 #define pmdp_collapse_flush pmdp_collapse_flush
1355
1356 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL
1357 pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma,
1358 unsigned long addr,
1359 pmd_t *pmdp, int full);
1360
1361 #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL
1362 pud_t pudp_huge_get_and_clear_full(struct vm_area_struct *vma,
1363 unsigned long addr,
1364 pud_t *pudp, int full);
1365
1366 #define __HAVE_ARCH_PGTABLE_DEPOSIT
1367 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm,
1368 pmd_t *pmdp, pgtable_t pgtable)
1369 {
1370 if (radix_enabled())
1371 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
1372 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
1373 }
1374
1375 #define __HAVE_ARCH_PGTABLE_WITHDRAW
1376 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm,
1377 pmd_t *pmdp)
1378 {
1379 if (radix_enabled())
1380 return radix__pgtable_trans_huge_withdraw(mm, pmdp);
1381 return hash__pgtable_trans_huge_withdraw(mm, pmdp);
1382 }
1383
1384 #define __HAVE_ARCH_PMDP_INVALIDATE
1385 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
1386 pmd_t *pmdp);
1387
1388 #define pmd_move_must_withdraw pmd_move_must_withdraw
1389 struct spinlock;
1390 extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
1391 struct spinlock *old_pmd_ptl,
1392 struct vm_area_struct *vma);
1393 /*
1394 * Hash translation mode use the deposited table to store hash pte
1395 * slot information.
1396 */
1397 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit
1398 static inline bool arch_needs_pgtable_deposit(void)
1399 {
1400 if (radix_enabled())
1401 return false;
1402 return true;
1403 }
1404 extern void serialize_against_pte_lookup(struct mm_struct *mm);
1405
1406
1407 static inline pmd_t pmd_mkdevmap(pmd_t pmd)
1408 {
1409 if (radix_enabled())
1410 return radix__pmd_mkdevmap(pmd);
1411 return hash__pmd_mkdevmap(pmd);
1412 }
1413
1414 static inline pud_t pud_mkdevmap(pud_t pud)
1415 {
1416 if (radix_enabled())
1417 return radix__pud_mkdevmap(pud);
1418 BUG();
1419 return pud;
1420 }
1421
1422 static inline int pmd_devmap(pmd_t pmd)
1423 {
1424 return pte_devmap(pmd_pte(pmd));
1425 }
1426
1427 static inline int pud_devmap(pud_t pud)
1428 {
1429 return pte_devmap(pud_pte(pud));
1430 }
1431
1432 static inline int pgd_devmap(pgd_t pgd)
1433 {
1434 return 0;
1435 }
1436 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1437
1438 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1439 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *);
1440 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long,
1441 pte_t *, pte_t, pte_t);
1442
1443 /*
1444 * Returns true for a R -> RW upgrade of pte
1445 */
1446 static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val)
1447 {
1448 if (!(old_val & _PAGE_READ))
1449 return false;
1450
1451 if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE))
1452 return true;
1453
1454 return false;
1455 }
1456
1457 #endif /* __ASSEMBLY__ */
1458 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */
1459
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