1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * MPC5121 Prototypes and definitions
4 */
5
6 #ifndef __ASM_POWERPC_MPC5121_H__
7 #define __ASM_POWERPC_MPC5121_H__
8
9 /* MPC512x Reset module registers */
10 struct mpc512x_reset_module {
11 u32 rcwlr; /* Reset Configuration Word Low Register */
12 u32 rcwhr; /* Reset Configuration Word High Register */
13 u32 reserved1;
14 u32 reserved2;
15 u32 rsr; /* Reset Status Register */
16 u32 rmr; /* Reset Mode Register */
17 u32 rpr; /* Reset Protection Register */
18 u32 rcr; /* Reset Control Register */
19 u32 rcer; /* Reset Control Enable Register */
20 };
21
22 /*
23 * Clock Control Module
24 */
25 struct mpc512x_ccm {
26 u32 spmr; /* System PLL Mode Register */
27 u32 sccr1; /* System Clock Control Register 1 */
28 u32 sccr2; /* System Clock Control Register 2 */
29 u32 scfr1; /* System Clock Frequency Register 1 */
30 u32 scfr2; /* System Clock Frequency Register 2 */
31 u32 scfr2s; /* System Clock Frequency Shadow Register 2 */
32 u32 bcr; /* Bread Crumb Register */
33 u32 psc_ccr[12]; /* PSC Clock Control Registers */
34 u32 spccr; /* SPDIF Clock Control Register */
35 u32 cccr; /* CFM Clock Control Register */
36 u32 dccr; /* DIU Clock Control Register */
37 u32 mscan_ccr[4]; /* MSCAN Clock Control Registers */
38 u32 out_ccr[4]; /* OUT CLK Configure Registers */
39 u32 rsv0[2]; /* Reserved */
40 u32 scfr3; /* System Clock Frequency Register 3 */
41 u32 rsv1[3]; /* Reserved */
42 u32 spll_lock_cnt; /* System PLL Lock Counter */
43 u8 res[0x6c]; /* Reserved */
44 };
45
46 /*
47 * LPC Module
48 */
49 struct mpc512x_lpc {
50 u32 cs_cfg[8]; /* CS config */
51 u32 cs_ctrl; /* CS Control Register */
52 u32 cs_status; /* CS Status Register */
53 u32 burst_ctrl; /* CS Burst Control Register */
54 u32 deadcycle_ctrl; /* CS Deadcycle Control Register */
55 u32 holdcycle_ctrl; /* CS Holdcycle Control Register */
56 u32 alt; /* Address Latch Timing Register */
57 };
58
59 int mpc512x_cs_config(unsigned int cs, u32 val);
60
61 /*
62 * SCLPC Module (LPB FIFO)
63 */
64 struct mpc512x_lpbfifo {
65 u32 pkt_size; /* SCLPC Packet Size Register */
66 u32 start_addr; /* SCLPC Start Address Register */
67 u32 ctrl; /* SCLPC Control Register */
68 u32 enable; /* SCLPC Enable Register */
69 u32 reserved1;
70 u32 status; /* SCLPC Status Register */
71 u32 bytes_done; /* SCLPC Bytes Done Register */
72 u32 emb_sc; /* EMB Share Counter Register */
73 u32 emb_pc; /* EMB Pause Control Register */
74 u32 reserved2[7];
75 u32 data_word; /* LPC RX/TX FIFO Data Word Register */
76 u32 fifo_status; /* LPC RX/TX FIFO Status Register */
77 u32 fifo_ctrl; /* LPC RX/TX FIFO Control Register */
78 u32 fifo_alarm; /* LPC RX/TX FIFO Alarm Register */
79 };
80
81 #define MPC512X_SCLPC_START (1 << 31)
82 #define MPC512X_SCLPC_CS(x) (((x) & 0x7) << 24)
83 #define MPC512X_SCLPC_FLUSH (1 << 17)
84 #define MPC512X_SCLPC_READ (1 << 16)
85 #define MPC512X_SCLPC_DAI (1 << 8)
86 #define MPC512X_SCLPC_BPT(x) ((x) & 0x3f)
87 #define MPC512X_SCLPC_RESET (1 << 24)
88 #define MPC512X_SCLPC_FIFO_RESET (1 << 16)
89 #define MPC512X_SCLPC_ABORT_INT_ENABLE (1 << 9)
90 #define MPC512X_SCLPC_NORM_INT_ENABLE (1 << 8)
91 #define MPC512X_SCLPC_ENABLE (1 << 0)
92 #define MPC512X_SCLPC_SUCCESS (1 << 24)
93 #define MPC512X_SCLPC_FIFO_CTRL(x) (((x) & 0x7) << 24)
94 #define MPC512X_SCLPC_FIFO_ALARM(x) ((x) & 0x3ff)
95
96 enum lpb_dev_portsize {
97 LPB_DEV_PORTSIZE_UNDEFINED = 0,
98 LPB_DEV_PORTSIZE_1_BYTE = 1,
99 LPB_DEV_PORTSIZE_2_BYTES = 2,
100 LPB_DEV_PORTSIZE_4_BYTES = 4,
101 LPB_DEV_PORTSIZE_8_BYTES = 8
102 };
103
104 enum mpc512x_lpbfifo_req_dir {
105 MPC512X_LPBFIFO_REQ_DIR_READ,
106 MPC512X_LPBFIFO_REQ_DIR_WRITE
107 };
108
109 struct mpc512x_lpbfifo_request {
110 phys_addr_t dev_phys_addr; /* physical address of some device on LPB */
111 void *ram_virt_addr; /* virtual address of some region in RAM */
112 u32 size;
113 enum lpb_dev_portsize portsize;
114 enum mpc512x_lpbfifo_req_dir dir;
115 void (*callback)(struct mpc512x_lpbfifo_request *);
116 };
117
118 int mpc512x_lpbfifo_submit(struct mpc512x_lpbfifo_request *req);
119
120 #endif /* __ASM_POWERPC_MPC5121_H__ */
121
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