1 /*
2 * include/asm-ppc/mpc52xx_psc.h
3 *
4 * Definitions of consts/structs to drive the Freescale MPC52xx OnChip
5 * PSCs. Theses are shared between multiple drivers since a PSC can be
6 * UART, AC97, IR, I2S, ... So this header is in asm-ppc.
7 *
8 *
9 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
10 *
11 * Based/Extracted from some header of the 2.4 originally written by
12 * Dale Farnsworth <dfarnsworth@mvista.com>
13 *
14 * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
15 * Copyright (C) 2003 MontaVista, Software, Inc.
16 *
17 * This file is licensed under the terms of the GNU General Public License
18 * version 2. This program is licensed "as is" without any warranty of any
19 * kind, whether express or implied.
20 */
21
22 #ifndef __ASM_MPC52xx_PSC_H__
23 #define __ASM_MPC52xx_PSC_H__
24
25 #include <asm/types.h>
26
27 /* Max number of PSCs */
28 #ifdef CONFIG_PPC_MPC512x
29 #define MPC52xx_PSC_MAXNUM 12
30 #else
31 #define MPC52xx_PSC_MAXNUM 6
32 #endif
33
34 /* Programmable Serial Controller (PSC) status register bits */
35 #define MPC52xx_PSC_SR_UNEX_RX 0x0001
36 #define MPC52xx_PSC_SR_DATA_VAL 0x0002
37 #define MPC52xx_PSC_SR_DATA_OVR 0x0004
38 #define MPC52xx_PSC_SR_CMDSEND 0x0008
39 #define MPC52xx_PSC_SR_CDE 0x0080
40 #define MPC52xx_PSC_SR_RXRDY 0x0100
41 #define MPC52xx_PSC_SR_RXFULL 0x0200
42 #define MPC52xx_PSC_SR_TXRDY 0x0400
43 #define MPC52xx_PSC_SR_TXEMP 0x0800
44 #define MPC52xx_PSC_SR_OE 0x1000
45 #define MPC52xx_PSC_SR_PE 0x2000
46 #define MPC52xx_PSC_SR_FE 0x4000
47 #define MPC52xx_PSC_SR_RB 0x8000
48
49 /* PSC Command values */
50 #define MPC52xx_PSC_RX_ENABLE 0x0001
51 #define MPC52xx_PSC_RX_DISABLE 0x0002
52 #define MPC52xx_PSC_TX_ENABLE 0x0004
53 #define MPC52xx_PSC_TX_DISABLE 0x0008
54 #define MPC52xx_PSC_SEL_MODE_REG_1 0x0010
55 #define MPC52xx_PSC_RST_RX 0x0020
56 #define MPC52xx_PSC_RST_TX 0x0030
57 #define MPC52xx_PSC_RST_ERR_STAT 0x0040
58 #define MPC52xx_PSC_RST_BRK_CHG_INT 0x0050
59 #define MPC52xx_PSC_START_BRK 0x0060
60 #define MPC52xx_PSC_STOP_BRK 0x0070
61
62 /* PSC TxRx FIFO status bits */
63 #define MPC52xx_PSC_RXTX_FIFO_ERR 0x0040
64 #define MPC52xx_PSC_RXTX_FIFO_UF 0x0020
65 #define MPC52xx_PSC_RXTX_FIFO_OF 0x0010
66 #define MPC52xx_PSC_RXTX_FIFO_FR 0x0008
67 #define MPC52xx_PSC_RXTX_FIFO_FULL 0x0004
68 #define MPC52xx_PSC_RXTX_FIFO_ALARM 0x0002
69 #define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001
70
71 /* PSC interrupt status/mask bits */
72 #define MPC52xx_PSC_IMR_UNEX_RX_SLOT 0x0001
73 #define MPC52xx_PSC_IMR_DATA_VALID 0x0002
74 #define MPC52xx_PSC_IMR_DATA_OVR 0x0004
75 #define MPC52xx_PSC_IMR_CMD_SEND 0x0008
76 #define MPC52xx_PSC_IMR_ERROR 0x0040
77 #define MPC52xx_PSC_IMR_DEOF 0x0080
78 #define MPC52xx_PSC_IMR_TXRDY 0x0100
79 #define MPC52xx_PSC_IMR_RXRDY 0x0200
80 #define MPC52xx_PSC_IMR_DB 0x0400
81 #define MPC52xx_PSC_IMR_TXEMP 0x0800
82 #define MPC52xx_PSC_IMR_ORERR 0x1000
83 #define MPC52xx_PSC_IMR_IPC 0x8000
84
85 /* PSC input port change bits */
86 #define MPC52xx_PSC_CTS 0x01
87 #define MPC52xx_PSC_DCD 0x02
88 #define MPC52xx_PSC_D_CTS 0x10
89 #define MPC52xx_PSC_D_DCD 0x20
90
91 /* PSC acr bits */
92 #define MPC52xx_PSC_IEC_CTS 0x01
93 #define MPC52xx_PSC_IEC_DCD 0x02
94
95 /* PSC output port bits */
96 #define MPC52xx_PSC_OP_RTS 0x01
97 #define MPC52xx_PSC_OP_RES 0x02
98
99 /* PSC mode fields */
100 #define MPC52xx_PSC_MODE_5_BITS 0x00
101 #define MPC52xx_PSC_MODE_6_BITS 0x01
102 #define MPC52xx_PSC_MODE_7_BITS 0x02
103 #define MPC52xx_PSC_MODE_8_BITS 0x03
104 #define MPC52xx_PSC_MODE_BITS_MASK 0x03
105 #define MPC52xx_PSC_MODE_PAREVEN 0x00
106 #define MPC52xx_PSC_MODE_PARODD 0x04
107 #define MPC52xx_PSC_MODE_PARFORCE 0x08
108 #define MPC52xx_PSC_MODE_PARNONE 0x10
109 #define MPC52xx_PSC_MODE_ERR 0x20
110 #define MPC52xx_PSC_MODE_FFULL 0x40
111 #define MPC52xx_PSC_MODE_RXRTS 0x80
112
113 #define MPC52xx_PSC_MODE_ONE_STOP_5_BITS 0x00
114 #define MPC52xx_PSC_MODE_ONE_STOP 0x07
115 #define MPC52xx_PSC_MODE_TWO_STOP 0x0f
116 #define MPC52xx_PSC_MODE_TXCTS 0x10
117
118 #define MPC52xx_PSC_RFNUM_MASK 0x01ff
119
120 #define MPC52xx_PSC_SICR_DTS1 (1 << 29)
121 #define MPC52xx_PSC_SICR_SHDR (1 << 28)
122 #define MPC52xx_PSC_SICR_SIM_MASK (0xf << 24)
123 #define MPC52xx_PSC_SICR_SIM_UART (0x0 << 24)
124 #define MPC52xx_PSC_SICR_SIM_UART_DCD (0x8 << 24)
125 #define MPC52xx_PSC_SICR_SIM_CODEC_8 (0x1 << 24)
126 #define MPC52xx_PSC_SICR_SIM_CODEC_16 (0x2 << 24)
127 #define MPC52xx_PSC_SICR_SIM_AC97 (0x3 << 24)
128 #define MPC52xx_PSC_SICR_SIM_SIR (0x8 << 24)
129 #define MPC52xx_PSC_SICR_SIM_SIR_DCD (0xc << 24)
130 #define MPC52xx_PSC_SICR_SIM_MIR (0x5 << 24)
131 #define MPC52xx_PSC_SICR_SIM_FIR (0x6 << 24)
132 #define MPC52xx_PSC_SICR_SIM_CODEC_24 (0x7 << 24)
133 #define MPC52xx_PSC_SICR_SIM_CODEC_32 (0xf << 24)
134 #define MPC52xx_PSC_SICR_ACRB (0x8 << 24)
135 #define MPC52xx_PSC_SICR_AWR (1 << 30)
136 #define MPC52xx_PSC_SICR_GENCLK (1 << 23)
137 #define MPC52xx_PSC_SICR_I2S (1 << 22)
138 #define MPC52xx_PSC_SICR_CLKPOL (1 << 21)
139 #define MPC52xx_PSC_SICR_SYNCPOL (1 << 20)
140 #define MPC52xx_PSC_SICR_CELLSLAVE (1 << 19)
141 #define MPC52xx_PSC_SICR_CELL2XCLK (1 << 18)
142 #define MPC52xx_PSC_SICR_ESAI (1 << 17)
143 #define MPC52xx_PSC_SICR_ENAC97 (1 << 16)
144 #define MPC52xx_PSC_SICR_SPI (1 << 15)
145 #define MPC52xx_PSC_SICR_MSTR (1 << 14)
146 #define MPC52xx_PSC_SICR_CPOL (1 << 13)
147 #define MPC52xx_PSC_SICR_CPHA (1 << 12)
148 #define MPC52xx_PSC_SICR_USEEOF (1 << 11)
149 #define MPC52xx_PSC_SICR_DISABLEEOF (1 << 10)
150
151 /* Structure of the hardware registers */
152 struct mpc52xx_psc {
153 union {
154 u8 mode; /* PSC + 0x00 */
155 u8 mr2;
156 };
157 u8 reserved0[3];
158 union { /* PSC + 0x04 */
159 u16 status;
160 u16 clock_select;
161 } sr_csr;
162 #define mpc52xx_psc_status sr_csr.status
163 #define mpc52xx_psc_clock_select sr_csr.clock_select
164 u16 reserved1;
165 u8 command; /* PSC + 0x08 */
166 u8 reserved2[3];
167 union { /* PSC + 0x0c */
168 u8 buffer_8;
169 u16 buffer_16;
170 u32 buffer_32;
171 } buffer;
172 #define mpc52xx_psc_buffer_8 buffer.buffer_8
173 #define mpc52xx_psc_buffer_16 buffer.buffer_16
174 #define mpc52xx_psc_buffer_32 buffer.buffer_32
175 union { /* PSC + 0x10 */
176 u8 ipcr;
177 u8 acr;
178 } ipcr_acr;
179 #define mpc52xx_psc_ipcr ipcr_acr.ipcr
180 #define mpc52xx_psc_acr ipcr_acr.acr
181 u8 reserved3[3];
182 union { /* PSC + 0x14 */
183 u16 isr;
184 u16 imr;
185 } isr_imr;
186 #define mpc52xx_psc_isr isr_imr.isr
187 #define mpc52xx_psc_imr isr_imr.imr
188 u16 reserved4;
189 u8 ctur; /* PSC + 0x18 */
190 u8 reserved5[3];
191 u8 ctlr; /* PSC + 0x1c */
192 u8 reserved6[3];
193 /* BitClkDiv field of CCR is byte swapped in
194 * the hardware for mpc5200/b compatibility */
195 u32 ccr; /* PSC + 0x20 */
196 u32 ac97_slots; /* PSC + 0x24 */
197 u32 ac97_cmd; /* PSC + 0x28 */
198 u32 ac97_data; /* PSC + 0x2c */
199 u8 ivr; /* PSC + 0x30 */
200 u8 reserved8[3];
201 u8 ip; /* PSC + 0x34 */
202 u8 reserved9[3];
203 u8 op1; /* PSC + 0x38 */
204 u8 reserved10[3];
205 u8 op0; /* PSC + 0x3c */
206 u8 reserved11[3];
207 u32 sicr; /* PSC + 0x40 */
208 u8 ircr1; /* PSC + 0x44 */
209 u8 reserved13[3];
210 u8 ircr2; /* PSC + 0x44 */
211 u8 reserved14[3];
212 u8 irsdr; /* PSC + 0x4c */
213 u8 reserved15[3];
214 u8 irmdr; /* PSC + 0x50 */
215 u8 reserved16[3];
216 u8 irfdr; /* PSC + 0x54 */
217 u8 reserved17[3];
218 };
219
220 struct mpc52xx_psc_fifo {
221 u16 rfnum; /* PSC + 0x58 */
222 u16 reserved18;
223 u16 tfnum; /* PSC + 0x5c */
224 u16 reserved19;
225 u32 rfdata; /* PSC + 0x60 */
226 u16 rfstat; /* PSC + 0x64 */
227 u16 reserved20;
228 u8 rfcntl; /* PSC + 0x68 */
229 u8 reserved21[5];
230 u16 rfalarm; /* PSC + 0x6e */
231 u16 reserved22;
232 u16 rfrptr; /* PSC + 0x72 */
233 u16 reserved23;
234 u16 rfwptr; /* PSC + 0x76 */
235 u16 reserved24;
236 u16 rflrfptr; /* PSC + 0x7a */
237 u16 reserved25;
238 u16 rflwfptr; /* PSC + 0x7e */
239 u32 tfdata; /* PSC + 0x80 */
240 u16 tfstat; /* PSC + 0x84 */
241 u16 reserved26;
242 u8 tfcntl; /* PSC + 0x88 */
243 u8 reserved27[5];
244 u16 tfalarm; /* PSC + 0x8e */
245 u16 reserved28;
246 u16 tfrptr; /* PSC + 0x92 */
247 u16 reserved29;
248 u16 tfwptr; /* PSC + 0x96 */
249 u16 reserved30;
250 u16 tflrfptr; /* PSC + 0x9a */
251 u16 reserved31;
252 u16 tflwfptr; /* PSC + 0x9e */
253 };
254
255 #define MPC512x_PSC_FIFO_EOF 0x100
256 #define MPC512x_PSC_FIFO_RESET_SLICE 0x80
257 #define MPC512x_PSC_FIFO_ENABLE_SLICE 0x01
258 #define MPC512x_PSC_FIFO_ENABLE_DMA 0x04
259
260 #define MPC512x_PSC_FIFO_EMPTY 0x1
261 #define MPC512x_PSC_FIFO_FULL 0x2
262 #define MPC512x_PSC_FIFO_ALARM 0x4
263 #define MPC512x_PSC_FIFO_URERR 0x8
264
265 struct mpc512x_psc_fifo {
266 u32 reserved1[10];
267 u32 txcmd; /* PSC + 0x80 */
268 u32 txalarm; /* PSC + 0x84 */
269 u32 txsr; /* PSC + 0x88 */
270 u32 txisr; /* PSC + 0x8c */
271 u32 tximr; /* PSC + 0x90 */
272 u32 txcnt; /* PSC + 0x94 */
273 u32 txptr; /* PSC + 0x98 */
274 u32 txsz; /* PSC + 0x9c */
275 u32 reserved2[7];
276 union {
277 u8 txdata_8;
278 u16 txdata_16;
279 u32 txdata_32;
280 } txdata; /* PSC + 0xbc */
281 #define txdata_8 txdata.txdata_8
282 #define txdata_16 txdata.txdata_16
283 #define txdata_32 txdata.txdata_32
284 u32 rxcmd; /* PSC + 0xc0 */
285 u32 rxalarm; /* PSC + 0xc4 */
286 u32 rxsr; /* PSC + 0xc8 */
287 u32 rxisr; /* PSC + 0xcc */
288 u32 rximr; /* PSC + 0xd0 */
289 u32 rxcnt; /* PSC + 0xd4 */
290 u32 rxptr; /* PSC + 0xd8 */
291 u32 rxsz; /* PSC + 0xdc */
292 u32 reserved3[7];
293 union {
294 u8 rxdata_8;
295 u16 rxdata_16;
296 u32 rxdata_32;
297 } rxdata; /* PSC + 0xfc */
298 #define rxdata_8 rxdata.rxdata_8
299 #define rxdata_16 rxdata.rxdata_16
300 #define rxdata_32 rxdata.rxdata_32
301 };
302
303 struct mpc5125_psc {
304 u8 mr1; /* PSC + 0x00 */
305 u8 reserved0[3];
306 u8 mr2; /* PSC + 0x04 */
307 u8 reserved1[3];
308 struct {
309 u16 status; /* PSC + 0x08 */
310 u8 reserved2[2];
311 u8 clock_select; /* PSC + 0x0c */
312 u8 reserved3[3];
313 } sr_csr;
314 u8 command; /* PSC + 0x10 */
315 u8 reserved4[3];
316 union { /* PSC + 0x14 */
317 u8 buffer_8;
318 u16 buffer_16;
319 u32 buffer_32;
320 } buffer;
321 struct {
322 u8 ipcr; /* PSC + 0x18 */
323 u8 reserved5[3];
324 u8 acr; /* PSC + 0x1c */
325 u8 reserved6[3];
326 } ipcr_acr;
327 struct {
328 u16 isr; /* PSC + 0x20 */
329 u8 reserved7[2];
330 u16 imr; /* PSC + 0x24 */
331 u8 reserved8[2];
332 } isr_imr;
333 u8 ctur; /* PSC + 0x28 */
334 u8 reserved9[3];
335 u8 ctlr; /* PSC + 0x2c */
336 u8 reserved10[3];
337 u32 ccr; /* PSC + 0x30 */
338 u32 ac97slots; /* PSC + 0x34 */
339 u32 ac97cmd; /* PSC + 0x38 */
340 u32 ac97data; /* PSC + 0x3c */
341 u8 reserved11[4];
342 u8 ip; /* PSC + 0x44 */
343 u8 reserved12[3];
344 u8 op1; /* PSC + 0x48 */
345 u8 reserved13[3];
346 u8 op0; /* PSC + 0x4c */
347 u8 reserved14[3];
348 u32 sicr; /* PSC + 0x50 */
349 u8 reserved15[4]; /* make eq. sizeof(mpc52xx_psc) */
350 };
351
352 #endif /* __ASM_MPC52xx_PSC_H__ */
353
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