1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_MMU_44X_H_
3 #define _ASM_POWERPC_MMU_44X_H_
4 /*
5 * PPC440 support
6 */
7
8 #include <asm/asm-const.h>
9
10 #define PPC44x_MMUCR_TID 0x000000ff
11 #define PPC44x_MMUCR_STS 0x00010000
12
13 #define PPC44x_TLB_PAGEID 0
14 #define PPC44x_TLB_XLAT 1
15 #define PPC44x_TLB_ATTRIB 2
16
17 /* Page identification fields */
18 #define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */
19 #define PPC44x_TLB_VALID 0x00000200 /* Valid flag */
20 #define PPC44x_TLB_TS 0x00000100 /* Translation address space */
21 #define PPC44x_TLB_1K 0x00000000 /* Page sizes */
22 #define PPC44x_TLB_4K 0x00000010
23 #define PPC44x_TLB_16K 0x00000020
24 #define PPC44x_TLB_64K 0x00000030
25 #define PPC44x_TLB_256K 0x00000040
26 #define PPC44x_TLB_1M 0x00000050
27 #define PPC44x_TLB_16M 0x00000070
28 #define PPC44x_TLB_256M 0x00000090
29
30 /* Translation fields */
31 #define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */
32 #define PPC44x_TLB_ERPN_MASK 0x0000000f
33
34 /* Storage attribute and access control fields */
35 #define PPC44x_TLB_ATTR_MASK 0x0000ff80
36 #define PPC44x_TLB_U0 0x00008000 /* User 0 */
37 #define PPC44x_TLB_U1 0x00004000 /* User 1 */
38 #define PPC44x_TLB_U2 0x00002000 /* User 2 */
39 #define PPC44x_TLB_U3 0x00001000 /* User 3 */
40 #define PPC44x_TLB_W 0x00000800 /* Caching is write-through */
41 #define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */
42 #define PPC44x_TLB_M 0x00000200 /* Memory is coherent */
43 #define PPC44x_TLB_G 0x00000100 /* Memory is guarded */
44 #define PPC44x_TLB_E 0x00000080 /* Memory is little endian */
45
46 #define PPC44x_TLB_PERM_MASK 0x0000003f
47 #define PPC44x_TLB_UX 0x00000020 /* User execution */
48 #define PPC44x_TLB_UW 0x00000010 /* User write */
49 #define PPC44x_TLB_UR 0x00000008 /* User read */
50 #define PPC44x_TLB_SX 0x00000004 /* Super execution */
51 #define PPC44x_TLB_SW 0x00000002 /* Super write */
52 #define PPC44x_TLB_SR 0x00000001 /* Super read */
53
54 /* Number of TLB entries */
55 #define PPC44x_TLB_SIZE 64
56
57 /* 47x bits */
58 #define PPC47x_MMUCR_TID 0x0000ffff
59 #define PPC47x_MMUCR_STS 0x00010000
60
61 /* Page identification fields */
62 #define PPC47x_TLB0_EPN_MASK 0xfffff000 /* Effective Page Number */
63 #define PPC47x_TLB0_VALID 0x00000800 /* Valid flag */
64 #define PPC47x_TLB0_TS 0x00000400 /* Translation address space */
65 #define PPC47x_TLB0_4K 0x00000000
66 #define PPC47x_TLB0_16K 0x00000010
67 #define PPC47x_TLB0_64K 0x00000030
68 #define PPC47x_TLB0_1M 0x00000070
69 #define PPC47x_TLB0_16M 0x000000f0
70 #define PPC47x_TLB0_256M 0x000001f0
71 #define PPC47x_TLB0_1G 0x000003f0
72 #define PPC47x_TLB0_BOLTED_R 0x00000008 /* tlbre only */
73
74 /* Translation fields */
75 #define PPC47x_TLB1_RPN_MASK 0xfffff000 /* Real Page Number */
76 #define PPC47x_TLB1_ERPN_MASK 0x000003ff
77
78 /* Storage attribute and access control fields */
79 #define PPC47x_TLB2_ATTR_MASK 0x0003ff80
80 #define PPC47x_TLB2_IL1I 0x00020000 /* Memory is guarded */
81 #define PPC47x_TLB2_IL1D 0x00010000 /* Memory is guarded */
82 #define PPC47x_TLB2_U0 0x00008000 /* User 0 */
83 #define PPC47x_TLB2_U1 0x00004000 /* User 1 */
84 #define PPC47x_TLB2_U2 0x00002000 /* User 2 */
85 #define PPC47x_TLB2_U3 0x00001000 /* User 3 */
86 #define PPC47x_TLB2_W 0x00000800 /* Caching is write-through */
87 #define PPC47x_TLB2_I 0x00000400 /* Caching is inhibited */
88 #define PPC47x_TLB2_M 0x00000200 /* Memory is coherent */
89 #define PPC47x_TLB2_G 0x00000100 /* Memory is guarded */
90 #define PPC47x_TLB2_E 0x00000080 /* Memory is little endian */
91 #define PPC47x_TLB2_PERM_MASK 0x0000003f
92 #define PPC47x_TLB2_UX 0x00000020 /* User execution */
93 #define PPC47x_TLB2_UW 0x00000010 /* User write */
94 #define PPC47x_TLB2_UR 0x00000008 /* User read */
95 #define PPC47x_TLB2_SX 0x00000004 /* Super execution */
96 #define PPC47x_TLB2_SW 0x00000002 /* Super write */
97 #define PPC47x_TLB2_SR 0x00000001 /* Super read */
98 #define PPC47x_TLB2_U_RWX (PPC47x_TLB2_UX|PPC47x_TLB2_UW|PPC47x_TLB2_UR)
99 #define PPC47x_TLB2_S_RWX (PPC47x_TLB2_SX|PPC47x_TLB2_SW|PPC47x_TLB2_SR)
100 #define PPC47x_TLB2_S_RW (PPC47x_TLB2_SW | PPC47x_TLB2_SR)
101 #define PPC47x_TLB2_IMG (PPC47x_TLB2_I | PPC47x_TLB2_M | PPC47x_TLB2_G)
102
103 #ifndef __ASSEMBLY__
104
105 extern unsigned int tlb_44x_hwater;
106 extern unsigned int tlb_44x_index;
107
108 typedef struct {
109 unsigned int id;
110 unsigned int active;
111 void __user *vdso;
112 } mm_context_t;
113
114 /* patch sites */
115 extern s32 patch__tlb_44x_hwater_D, patch__tlb_44x_hwater_I;
116
117 #endif /* !__ASSEMBLY__ */
118
119 #ifndef CONFIG_PPC_EARLY_DEBUG_44x
120 #define PPC44x_EARLY_TLBS 1
121 #else
122 #define PPC44x_EARLY_TLBS 2
123 #define PPC44x_EARLY_DEBUG_VIRTADDR (ASM_CONST(0xf0000000) \
124 | (ASM_CONST(CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW) & 0xffff))
125 #endif
126
127 /* Size of the TLBs used for pinning in lowmem */
128 #define PPC_PIN_SIZE (1 << 28) /* 256M */
129
130 #if defined(CONFIG_PPC_4K_PAGES)
131 #define PPC44x_TLBE_SIZE PPC44x_TLB_4K
132 #define PPC47x_TLBE_SIZE PPC47x_TLB0_4K
133 #define mmu_virtual_psize MMU_PAGE_4K
134 #elif defined(CONFIG_PPC_16K_PAGES)
135 #define PPC44x_TLBE_SIZE PPC44x_TLB_16K
136 #define PPC47x_TLBE_SIZE PPC47x_TLB0_16K
137 #define mmu_virtual_psize MMU_PAGE_16K
138 #elif defined(CONFIG_PPC_64K_PAGES)
139 #define PPC44x_TLBE_SIZE PPC44x_TLB_64K
140 #define PPC47x_TLBE_SIZE PPC47x_TLB0_64K
141 #define mmu_virtual_psize MMU_PAGE_64K
142 #elif defined(CONFIG_PPC_256K_PAGES)
143 #define PPC44x_TLBE_SIZE PPC44x_TLB_256K
144 #define mmu_virtual_psize MMU_PAGE_256K
145 #else
146 #error "Unsupported PAGE_SIZE"
147 #endif
148
149 #define mmu_linear_psize MMU_PAGE_256M
150
151 #define PPC44x_PGD_OFF_SHIFT (32 - PGDIR_SHIFT + PGD_T_LOG2)
152 #define PPC44x_PGD_OFF_MASK_BIT (PGDIR_SHIFT - PGD_T_LOG2)
153 #define PPC44x_PTE_ADD_SHIFT (32 - PGDIR_SHIFT + PTE_SHIFT + PTE_T_LOG2)
154 #define PPC44x_PTE_ADD_MASK_BIT (32 - PTE_T_LOG2 - PTE_SHIFT)
155
156 #endif /* _ASM_POWERPC_MMU_44X_H_ */
157
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