1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_PAGE_32_H
3 #define _ASM_POWERPC_PAGE_32_H
4
5 #include <asm/cache.h>
6
7 #if defined(CONFIG_PHYSICAL_ALIGN) && (CONFIG_PHYSICAL_START != 0)
8 #if (CONFIG_PHYSICAL_START % CONFIG_PHYSICAL_ALIGN) != 0
9 #error "CONFIG_PHYSICAL_START must be a multiple of CONFIG_PHYSICAL_ALIGN"
10 #endif
11 #endif
12
13 #define VM_DATA_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS32
14
15 #if defined(CONFIG_PPC_256K_PAGES) || \
16 (defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES))
17 #define PTE_SHIFT (PAGE_SHIFT - PTE_T_LOG2 - 2) /* 1/4 of a page */
18 #else
19 #define PTE_SHIFT (PAGE_SHIFT - PTE_T_LOG2) /* full page */
20 #endif
21
22 #ifndef __ASSEMBLY__
23 /*
24 * The basic type of a PTE - 64 bits for those CPUs with > 32 bit
25 * physical addressing.
26 */
27 #ifdef CONFIG_PTE_64BIT
28 typedef unsigned long long pte_basic_t;
29 #else
30 typedef unsigned long pte_basic_t;
31 #endif
32
33 #include <asm/bug.h>
34
35 /*
36 * Clear page using the dcbz instruction, which doesn't cause any
37 * memory traffic (except to write out any cache lines which get
38 * displaced). This only works on cacheable memory.
39 */
40 static inline void clear_page(void *addr)
41 {
42 unsigned int i;
43
44 WARN_ON((unsigned long)addr & (L1_CACHE_BYTES - 1));
45
46 for (i = 0; i < PAGE_SIZE / L1_CACHE_BYTES; i++, addr += L1_CACHE_BYTES)
47 dcbz(addr);
48 }
49 extern void copy_page(void *to, void *from);
50
51 #include <asm-generic/getorder.h>
52
53 #define PGD_T_LOG2 (__builtin_ffs(sizeof(pgd_t)) - 1)
54 #define PTE_T_LOG2 (__builtin_ffs(sizeof(pte_t)) - 1)
55
56 #endif /* __ASSEMBLY__ */
57
58 #endif /* _ASM_POWERPC_PAGE_32_H */
59
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