1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Security related feature bit definitions.
4 *
5 * Copyright 2018, Michael Ellerman, IBM Corporation.
6 */
7
8 #ifndef _ASM_POWERPC_SECURITY_FEATURES_H
9 #define _ASM_POWERPC_SECURITY_FEATURES_H
10
11
12 extern u64 powerpc_security_features;
13 extern bool rfi_flush;
14
15 /* These are bit flags */
16 enum stf_barrier_type {
17 STF_BARRIER_NONE = 0x1,
18 STF_BARRIER_FALLBACK = 0x2,
19 STF_BARRIER_EIEIO = 0x4,
20 STF_BARRIER_SYNC_ORI = 0x8,
21 };
22
23 void setup_stf_barrier(void);
24 void do_stf_barrier_fixups(enum stf_barrier_type types);
25 void setup_count_cache_flush(void);
26
27 static inline void security_ftr_set(u64 feature)
28 {
29 powerpc_security_features |= feature;
30 }
31
32 static inline void security_ftr_clear(u64 feature)
33 {
34 powerpc_security_features &= ~feature;
35 }
36
37 static inline bool security_ftr_enabled(u64 feature)
38 {
39 return !!(powerpc_security_features & feature);
40 }
41
42 #ifdef CONFIG_PPC_BOOK3S_64
43 enum stf_barrier_type stf_barrier_type_get(void);
44 #else
45 static inline enum stf_barrier_type stf_barrier_type_get(void) { return STF_BARRIER_NONE; }
46 #endif
47
48 // Features indicating support for Spectre/Meltdown mitigations
49
50 // The L1-D cache can be flushed with ori r30,r30,0
51 #define SEC_FTR_L1D_FLUSH_ORI30 0x0000000000000001ull
52
53 // The L1-D cache can be flushed with mtspr 882,r0 (aka SPRN_TRIG2)
54 #define SEC_FTR_L1D_FLUSH_TRIG2 0x0000000000000002ull
55
56 // ori r31,r31,0 acts as a speculation barrier
57 #define SEC_FTR_SPEC_BAR_ORI31 0x0000000000000004ull
58
59 // Speculation past bctr is disabled
60 #define SEC_FTR_BCCTRL_SERIALISED 0x0000000000000008ull
61
62 // Entries in L1-D are private to a SMT thread
63 #define SEC_FTR_L1D_THREAD_PRIV 0x0000000000000010ull
64
65 // Indirect branch prediction cache disabled
66 #define SEC_FTR_COUNT_CACHE_DISABLED 0x0000000000000020ull
67
68 // bcctr 2,0,0 triggers a hardware assisted count cache flush
69 #define SEC_FTR_BCCTR_FLUSH_ASSIST 0x0000000000000800ull
70
71 // bcctr 2,0,0 triggers a hardware assisted link stack flush
72 #define SEC_FTR_BCCTR_LINK_FLUSH_ASSIST 0x0000000000002000ull
73
74 // Features indicating need for Spectre/Meltdown mitigations
75
76 // The L1-D cache should be flushed on MSR[HV] 1->0 transition (hypervisor to guest)
77 #define SEC_FTR_L1D_FLUSH_HV 0x0000000000000040ull
78
79 // The L1-D cache should be flushed on MSR[PR] 0->1 transition (kernel to userspace)
80 #define SEC_FTR_L1D_FLUSH_PR 0x0000000000000080ull
81
82 // A speculation barrier should be used for bounds checks (Spectre variant 1)
83 #define SEC_FTR_BNDS_CHK_SPEC_BAR 0x0000000000000100ull
84
85 // Firmware configuration indicates user favours security over performance
86 #define SEC_FTR_FAVOUR_SECURITY 0x0000000000000200ull
87
88 // Software required to flush count cache on context switch
89 #define SEC_FTR_FLUSH_COUNT_CACHE 0x0000000000000400ull
90
91 // Software required to flush link stack on context switch
92 #define SEC_FTR_FLUSH_LINK_STACK 0x0000000000001000ull
93
94 // The L1-D cache should be flushed when entering the kernel
95 #define SEC_FTR_L1D_FLUSH_ENTRY 0x0000000000004000ull
96
97 // The L1-D cache should be flushed after user accesses from the kernel
98 #define SEC_FTR_L1D_FLUSH_UACCESS 0x0000000000008000ull
99
100 // The STF flush should be executed on privilege state switch
101 #define SEC_FTR_STF_BARRIER 0x0000000000010000ull
102
103 // Features enabled by default
104 #define SEC_FTR_DEFAULT \
105 (SEC_FTR_L1D_FLUSH_HV | \
106 SEC_FTR_L1D_FLUSH_PR | \
107 SEC_FTR_BNDS_CHK_SPEC_BAR | \
108 SEC_FTR_L1D_FLUSH_ENTRY | \
109 SEC_FTR_L1D_FLUSH_UACCESS | \
110 SEC_FTR_STF_BARRIER | \
111 SEC_FTR_FAVOUR_SECURITY)
112
113 #endif /* _ASM_POWERPC_SECURITY_FEATURES_H */
114
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