1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Derived from "arch/i386/kernel/process.c"
4 * Copyright (C) 1995 Linus Torvalds
5 *
6 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
7 * Paul Mackerras (paulus@cs.anu.edu.au)
8 *
9 * PowerPC version
10 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
11 */
12
13 #include <linux/errno.h>
14 #include <linux/sched.h>
15 #include <linux/sched/debug.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/task_stack.h>
18 #include <linux/kernel.h>
19 #include <linux/mm.h>
20 #include <linux/smp.h>
21 #include <linux/stddef.h>
22 #include <linux/unistd.h>
23 #include <linux/ptrace.h>
24 #include <linux/slab.h>
25 #include <linux/user.h>
26 #include <linux/elf.h>
27 #include <linux/prctl.h>
28 #include <linux/init_task.h>
29 #include <linux/export.h>
30 #include <linux/kallsyms.h>
31 #include <linux/mqueue.h>
32 #include <linux/hardirq.h>
33 #include <linux/utsname.h>
34 #include <linux/ftrace.h>
35 #include <linux/kernel_stat.h>
36 #include <linux/personality.h>
37 #include <linux/hw_breakpoint.h>
38 #include <linux/uaccess.h>
39 #include <linux/pkeys.h>
40 #include <linux/seq_buf.h>
41
42 #include <asm/interrupt.h>
43 #include <asm/io.h>
44 #include <asm/processor.h>
45 #include <asm/mmu.h>
46 #include <asm/machdep.h>
47 #include <asm/time.h>
48 #include <asm/runlatch.h>
49 #include <asm/syscalls.h>
50 #include <asm/switch_to.h>
51 #include <asm/tm.h>
52 #include <asm/debug.h>
53 #ifdef CONFIG_PPC64
54 #include <asm/firmware.h>
55 #include <asm/hw_irq.h>
56 #endif
57 #include <asm/code-patching.h>
58 #include <asm/exec.h>
59 #include <asm/livepatch.h>
60 #include <asm/cpu_has_feature.h>
61 #include <asm/asm-prototypes.h>
62 #include <asm/stacktrace.h>
63 #include <asm/hw_breakpoint.h>
64
65 #include <linux/kprobes.h>
66 #include <linux/kdebug.h>
67
68 /* Transactional Memory debug */
69 #ifdef TM_DEBUG_SW
70 #define TM_DEBUG(x...) printk(KERN_INFO x)
71 #else
72 #define TM_DEBUG(x...) do { } while(0)
73 #endif
74
75 extern unsigned long _get_SP(void);
76
77 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
78 /*
79 * Are we running in "Suspend disabled" mode? If so we have to block any
80 * sigreturn that would get us into suspended state, and we also warn in some
81 * other paths that we should never reach with suspend disabled.
82 */
83 bool tm_suspend_disabled __ro_after_init = false;
84
85 static void check_if_tm_restore_required(struct task_struct *tsk)
86 {
87 /*
88 * If we are saving the current thread's registers, and the
89 * thread is in a transactional state, set the TIF_RESTORE_TM
90 * bit so that we know to restore the registers before
91 * returning to userspace.
92 */
93 if (tsk == current && tsk->thread.regs &&
94 MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
95 !test_thread_flag(TIF_RESTORE_TM)) {
96 regs_set_return_msr(&tsk->thread.ckpt_regs,
97 tsk->thread.regs->msr);
98 set_thread_flag(TIF_RESTORE_TM);
99 }
100 }
101
102 #else
103 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
104 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
105
106 bool strict_msr_control;
107 EXPORT_SYMBOL(strict_msr_control);
108
109 static int __init enable_strict_msr_control(char *str)
110 {
111 strict_msr_control = true;
112 pr_info("Enabling strict facility control\n");
113
114 return 0;
115 }
116 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
117
118 /* notrace because it's called by restore_math */
119 unsigned long notrace msr_check_and_set(unsigned long bits)
120 {
121 unsigned long oldmsr = mfmsr();
122 unsigned long newmsr;
123
124 newmsr = oldmsr | bits;
125
126 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
127 newmsr |= MSR_VSX;
128
129 if (oldmsr != newmsr)
130 newmsr = mtmsr_isync_irqsafe(newmsr);
131
132 return newmsr;
133 }
134 EXPORT_SYMBOL_GPL(msr_check_and_set);
135
136 /* notrace because it's called by restore_math */
137 void notrace __msr_check_and_clear(unsigned long bits)
138 {
139 unsigned long oldmsr = mfmsr();
140 unsigned long newmsr;
141
142 newmsr = oldmsr & ~bits;
143
144 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
145 newmsr &= ~MSR_VSX;
146
147 if (oldmsr != newmsr)
148 mtmsr_isync_irqsafe(newmsr);
149 }
150 EXPORT_SYMBOL(__msr_check_and_clear);
151
152 #ifdef CONFIG_PPC_FPU
153 static void __giveup_fpu(struct task_struct *tsk)
154 {
155 unsigned long msr;
156
157 save_fpu(tsk);
158 msr = tsk->thread.regs->msr;
159 msr &= ~(MSR_FP|MSR_FE0|MSR_FE1);
160 if (cpu_has_feature(CPU_FTR_VSX))
161 msr &= ~MSR_VSX;
162 regs_set_return_msr(tsk->thread.regs, msr);
163 }
164
165 void giveup_fpu(struct task_struct *tsk)
166 {
167 check_if_tm_restore_required(tsk);
168
169 msr_check_and_set(MSR_FP);
170 __giveup_fpu(tsk);
171 msr_check_and_clear(MSR_FP);
172 }
173 EXPORT_SYMBOL(giveup_fpu);
174
175 /*
176 * Make sure the floating-point register state in the
177 * the thread_struct is up to date for task tsk.
178 */
179 void flush_fp_to_thread(struct task_struct *tsk)
180 {
181 if (tsk->thread.regs) {
182 /*
183 * We need to disable preemption here because if we didn't,
184 * another process could get scheduled after the regs->msr
185 * test but before we have finished saving the FP registers
186 * to the thread_struct. That process could take over the
187 * FPU, and then when we get scheduled again we would store
188 * bogus values for the remaining FP registers.
189 */
190 preempt_disable();
191 if (tsk->thread.regs->msr & MSR_FP) {
192 /*
193 * This should only ever be called for current or
194 * for a stopped child process. Since we save away
195 * the FP register state on context switch,
196 * there is something wrong if a stopped child appears
197 * to still have its FP state in the CPU registers.
198 */
199 BUG_ON(tsk != current);
200 giveup_fpu(tsk);
201 }
202 preempt_enable();
203 }
204 }
205 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
206
207 void enable_kernel_fp(void)
208 {
209 unsigned long cpumsr;
210
211 WARN_ON(preemptible());
212
213 cpumsr = msr_check_and_set(MSR_FP);
214
215 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
216 check_if_tm_restore_required(current);
217 /*
218 * If a thread has already been reclaimed then the
219 * checkpointed registers are on the CPU but have definitely
220 * been saved by the reclaim code. Don't need to and *cannot*
221 * giveup as this would save to the 'live' structure not the
222 * checkpointed structure.
223 */
224 if (!MSR_TM_ACTIVE(cpumsr) &&
225 MSR_TM_ACTIVE(current->thread.regs->msr))
226 return;
227 __giveup_fpu(current);
228 }
229 }
230 EXPORT_SYMBOL(enable_kernel_fp);
231 #else
232 static inline void __giveup_fpu(struct task_struct *tsk) { }
233 #endif /* CONFIG_PPC_FPU */
234
235 #ifdef CONFIG_ALTIVEC
236 static void __giveup_altivec(struct task_struct *tsk)
237 {
238 unsigned long msr;
239
240 save_altivec(tsk);
241 msr = tsk->thread.regs->msr;
242 msr &= ~MSR_VEC;
243 if (cpu_has_feature(CPU_FTR_VSX))
244 msr &= ~MSR_VSX;
245 regs_set_return_msr(tsk->thread.regs, msr);
246 }
247
248 void giveup_altivec(struct task_struct *tsk)
249 {
250 check_if_tm_restore_required(tsk);
251
252 msr_check_and_set(MSR_VEC);
253 __giveup_altivec(tsk);
254 msr_check_and_clear(MSR_VEC);
255 }
256 EXPORT_SYMBOL(giveup_altivec);
257
258 void enable_kernel_altivec(void)
259 {
260 unsigned long cpumsr;
261
262 WARN_ON(preemptible());
263
264 cpumsr = msr_check_and_set(MSR_VEC);
265
266 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
267 check_if_tm_restore_required(current);
268 /*
269 * If a thread has already been reclaimed then the
270 * checkpointed registers are on the CPU but have definitely
271 * been saved by the reclaim code. Don't need to and *cannot*
272 * giveup as this would save to the 'live' structure not the
273 * checkpointed structure.
274 */
275 if (!MSR_TM_ACTIVE(cpumsr) &&
276 MSR_TM_ACTIVE(current->thread.regs->msr))
277 return;
278 __giveup_altivec(current);
279 }
280 }
281 EXPORT_SYMBOL(enable_kernel_altivec);
282
283 /*
284 * Make sure the VMX/Altivec register state in the
285 * the thread_struct is up to date for task tsk.
286 */
287 void flush_altivec_to_thread(struct task_struct *tsk)
288 {
289 if (tsk->thread.regs) {
290 preempt_disable();
291 if (tsk->thread.regs->msr & MSR_VEC) {
292 BUG_ON(tsk != current);
293 giveup_altivec(tsk);
294 }
295 preempt_enable();
296 }
297 }
298 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
299 #endif /* CONFIG_ALTIVEC */
300
301 #ifdef CONFIG_VSX
302 static void __giveup_vsx(struct task_struct *tsk)
303 {
304 unsigned long msr = tsk->thread.regs->msr;
305
306 /*
307 * We should never be setting MSR_VSX without also setting
308 * MSR_FP and MSR_VEC
309 */
310 WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC)));
311
312 /* __giveup_fpu will clear MSR_VSX */
313 if (msr & MSR_FP)
314 __giveup_fpu(tsk);
315 if (msr & MSR_VEC)
316 __giveup_altivec(tsk);
317 }
318
319 static void giveup_vsx(struct task_struct *tsk)
320 {
321 check_if_tm_restore_required(tsk);
322
323 msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
324 __giveup_vsx(tsk);
325 msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
326 }
327
328 void enable_kernel_vsx(void)
329 {
330 unsigned long cpumsr;
331
332 WARN_ON(preemptible());
333
334 cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
335
336 if (current->thread.regs &&
337 (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) {
338 check_if_tm_restore_required(current);
339 /*
340 * If a thread has already been reclaimed then the
341 * checkpointed registers are on the CPU but have definitely
342 * been saved by the reclaim code. Don't need to and *cannot*
343 * giveup as this would save to the 'live' structure not the
344 * checkpointed structure.
345 */
346 if (!MSR_TM_ACTIVE(cpumsr) &&
347 MSR_TM_ACTIVE(current->thread.regs->msr))
348 return;
349 __giveup_vsx(current);
350 }
351 }
352 EXPORT_SYMBOL(enable_kernel_vsx);
353
354 void flush_vsx_to_thread(struct task_struct *tsk)
355 {
356 if (tsk->thread.regs) {
357 preempt_disable();
358 if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) {
359 BUG_ON(tsk != current);
360 giveup_vsx(tsk);
361 }
362 preempt_enable();
363 }
364 }
365 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
366 #endif /* CONFIG_VSX */
367
368 #ifdef CONFIG_SPE
369 void giveup_spe(struct task_struct *tsk)
370 {
371 check_if_tm_restore_required(tsk);
372
373 msr_check_and_set(MSR_SPE);
374 __giveup_spe(tsk);
375 msr_check_and_clear(MSR_SPE);
376 }
377 EXPORT_SYMBOL(giveup_spe);
378
379 void enable_kernel_spe(void)
380 {
381 WARN_ON(preemptible());
382
383 msr_check_and_set(MSR_SPE);
384
385 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
386 check_if_tm_restore_required(current);
387 __giveup_spe(current);
388 }
389 }
390 EXPORT_SYMBOL(enable_kernel_spe);
391
392 void flush_spe_to_thread(struct task_struct *tsk)
393 {
394 if (tsk->thread.regs) {
395 preempt_disable();
396 if (tsk->thread.regs->msr & MSR_SPE) {
397 BUG_ON(tsk != current);
398 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
399 giveup_spe(tsk);
400 }
401 preempt_enable();
402 }
403 }
404 #endif /* CONFIG_SPE */
405
406 static unsigned long msr_all_available;
407
408 static int __init init_msr_all_available(void)
409 {
410 if (IS_ENABLED(CONFIG_PPC_FPU))
411 msr_all_available |= MSR_FP;
412 if (cpu_has_feature(CPU_FTR_ALTIVEC))
413 msr_all_available |= MSR_VEC;
414 if (cpu_has_feature(CPU_FTR_VSX))
415 msr_all_available |= MSR_VSX;
416 if (cpu_has_feature(CPU_FTR_SPE))
417 msr_all_available |= MSR_SPE;
418
419 return 0;
420 }
421 early_initcall(init_msr_all_available);
422
423 void giveup_all(struct task_struct *tsk)
424 {
425 unsigned long usermsr;
426
427 if (!tsk->thread.regs)
428 return;
429
430 check_if_tm_restore_required(tsk);
431
432 usermsr = tsk->thread.regs->msr;
433
434 if ((usermsr & msr_all_available) == 0)
435 return;
436
437 msr_check_and_set(msr_all_available);
438
439 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
440
441 if (usermsr & MSR_FP)
442 __giveup_fpu(tsk);
443 if (usermsr & MSR_VEC)
444 __giveup_altivec(tsk);
445 if (usermsr & MSR_SPE)
446 __giveup_spe(tsk);
447
448 msr_check_and_clear(msr_all_available);
449 }
450 EXPORT_SYMBOL(giveup_all);
451
452 #ifdef CONFIG_PPC_BOOK3S_64
453 #ifdef CONFIG_PPC_FPU
454 static bool should_restore_fp(void)
455 {
456 if (current->thread.load_fp) {
457 current->thread.load_fp++;
458 return true;
459 }
460 return false;
461 }
462
463 static void do_restore_fp(void)
464 {
465 load_fp_state(¤t->thread.fp_state);
466 }
467 #else
468 static bool should_restore_fp(void) { return false; }
469 static void do_restore_fp(void) { }
470 #endif /* CONFIG_PPC_FPU */
471
472 #ifdef CONFIG_ALTIVEC
473 static bool should_restore_altivec(void)
474 {
475 if (cpu_has_feature(CPU_FTR_ALTIVEC) && (current->thread.load_vec)) {
476 current->thread.load_vec++;
477 return true;
478 }
479 return false;
480 }
481
482 static void do_restore_altivec(void)
483 {
484 load_vr_state(¤t->thread.vr_state);
485 current->thread.used_vr = 1;
486 }
487 #else
488 static bool should_restore_altivec(void) { return false; }
489 static void do_restore_altivec(void) { }
490 #endif /* CONFIG_ALTIVEC */
491
492 static bool should_restore_vsx(void)
493 {
494 if (cpu_has_feature(CPU_FTR_VSX))
495 return true;
496 return false;
497 }
498 #ifdef CONFIG_VSX
499 static void do_restore_vsx(void)
500 {
501 current->thread.used_vsr = 1;
502 }
503 #else
504 static void do_restore_vsx(void) { }
505 #endif /* CONFIG_VSX */
506
507 /*
508 * The exception exit path calls restore_math() with interrupts hard disabled
509 * but the soft irq state not "reconciled". ftrace code that calls
510 * local_irq_save/restore causes warnings.
511 *
512 * Rather than complicate the exit path, just don't trace restore_math. This
513 * could be done by having ftrace entry code check for this un-reconciled
514 * condition where MSR[EE]=0 and PACA_IRQ_HARD_DIS is not set, and
515 * temporarily fix it up for the duration of the ftrace call.
516 */
517 void notrace restore_math(struct pt_regs *regs)
518 {
519 unsigned long msr;
520 unsigned long new_msr = 0;
521
522 msr = regs->msr;
523
524 /*
525 * new_msr tracks the facilities that are to be restored. Only reload
526 * if the bit is not set in the user MSR (if it is set, the registers
527 * are live for the user thread).
528 */
529 if ((!(msr & MSR_FP)) && should_restore_fp())
530 new_msr |= MSR_FP;
531
532 if ((!(msr & MSR_VEC)) && should_restore_altivec())
533 new_msr |= MSR_VEC;
534
535 if ((!(msr & MSR_VSX)) && should_restore_vsx()) {
536 if (((msr | new_msr) & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC))
537 new_msr |= MSR_VSX;
538 }
539
540 if (new_msr) {
541 unsigned long fpexc_mode = 0;
542
543 msr_check_and_set(new_msr);
544
545 if (new_msr & MSR_FP) {
546 do_restore_fp();
547
548 // This also covers VSX, because VSX implies FP
549 fpexc_mode = current->thread.fpexc_mode;
550 }
551
552 if (new_msr & MSR_VEC)
553 do_restore_altivec();
554
555 if (new_msr & MSR_VSX)
556 do_restore_vsx();
557
558 msr_check_and_clear(new_msr);
559
560 regs_set_return_msr(regs, regs->msr | new_msr | fpexc_mode);
561 }
562 }
563 #endif /* CONFIG_PPC_BOOK3S_64 */
564
565 static void save_all(struct task_struct *tsk)
566 {
567 unsigned long usermsr;
568
569 if (!tsk->thread.regs)
570 return;
571
572 usermsr = tsk->thread.regs->msr;
573
574 if ((usermsr & msr_all_available) == 0)
575 return;
576
577 msr_check_and_set(msr_all_available);
578
579 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
580
581 if (usermsr & MSR_FP)
582 save_fpu(tsk);
583
584 if (usermsr & MSR_VEC)
585 save_altivec(tsk);
586
587 if (usermsr & MSR_SPE)
588 __giveup_spe(tsk);
589
590 msr_check_and_clear(msr_all_available);
591 }
592
593 void flush_all_to_thread(struct task_struct *tsk)
594 {
595 if (tsk->thread.regs) {
596 preempt_disable();
597 BUG_ON(tsk != current);
598 #ifdef CONFIG_SPE
599 if (tsk->thread.regs->msr & MSR_SPE)
600 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
601 #endif
602 save_all(tsk);
603
604 preempt_enable();
605 }
606 }
607 EXPORT_SYMBOL(flush_all_to_thread);
608
609 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
610 void do_send_trap(struct pt_regs *regs, unsigned long address,
611 unsigned long error_code, int breakpt)
612 {
613 current->thread.trap_nr = TRAP_HWBKPT;
614 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
615 11, SIGSEGV) == NOTIFY_STOP)
616 return;
617
618 /* Deliver the signal to userspace */
619 force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */
620 (void __user *)address);
621 }
622 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
623
624 static void do_break_handler(struct pt_regs *regs)
625 {
626 struct arch_hw_breakpoint null_brk = {0};
627 struct arch_hw_breakpoint *info;
628 ppc_inst_t instr = ppc_inst(0);
629 int type = 0;
630 int size = 0;
631 unsigned long ea;
632 int i;
633
634 /*
635 * If underneath hw supports only one watchpoint, we know it
636 * caused exception. 8xx also falls into this category.
637 */
638 if (nr_wp_slots() == 1) {
639 __set_breakpoint(0, &null_brk);
640 current->thread.hw_brk[0] = null_brk;
641 current->thread.hw_brk[0].flags |= HW_BRK_FLAG_DISABLED;
642 return;
643 }
644
645 /* Otherwise find out which DAWR caused exception and disable it. */
646 wp_get_instr_detail(regs, &instr, &type, &size, &ea);
647
648 for (i = 0; i < nr_wp_slots(); i++) {
649 info = ¤t->thread.hw_brk[i];
650 if (!info->address)
651 continue;
652
653 if (wp_check_constraints(regs, instr, ea, type, size, info)) {
654 __set_breakpoint(i, &null_brk);
655 current->thread.hw_brk[i] = null_brk;
656 current->thread.hw_brk[i].flags |= HW_BRK_FLAG_DISABLED;
657 }
658 }
659 }
660
661 DEFINE_INTERRUPT_HANDLER(do_break)
662 {
663 current->thread.trap_nr = TRAP_HWBKPT;
664 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, regs->dsisr,
665 11, SIGSEGV) == NOTIFY_STOP)
666 return;
667
668 if (debugger_break_match(regs))
669 return;
670
671 /*
672 * We reach here only when watchpoint exception is generated by ptrace
673 * event (or hw is buggy!). Now if CONFIG_HAVE_HW_BREAKPOINT is set,
674 * watchpoint is already handled by hw_breakpoint_handler() so we don't
675 * have to do anything. But when CONFIG_HAVE_HW_BREAKPOINT is not set,
676 * we need to manually handle the watchpoint here.
677 */
678 if (!IS_ENABLED(CONFIG_HAVE_HW_BREAKPOINT))
679 do_break_handler(regs);
680
681 /* Deliver the signal to userspace */
682 force_sig_fault(SIGTRAP, TRAP_HWBKPT, (void __user *)regs->dar);
683 }
684 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
685
686 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk[HBP_NUM_MAX]);
687
688 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
689 /*
690 * Set the debug registers back to their default "safe" values.
691 */
692 static void set_debug_reg_defaults(struct thread_struct *thread)
693 {
694 thread->debug.iac1 = thread->debug.iac2 = 0;
695 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
696 thread->debug.iac3 = thread->debug.iac4 = 0;
697 #endif
698 thread->debug.dac1 = thread->debug.dac2 = 0;
699 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
700 thread->debug.dvc1 = thread->debug.dvc2 = 0;
701 #endif
702 thread->debug.dbcr0 = 0;
703 #ifdef CONFIG_BOOKE
704 /*
705 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
706 */
707 thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
708 DBCR1_IAC3US | DBCR1_IAC4US;
709 /*
710 * Force Data Address Compare User/Supervisor bits to be User-only
711 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
712 */
713 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
714 #else
715 thread->debug.dbcr1 = 0;
716 #endif
717 }
718
719 static void prime_debug_regs(struct debug_reg *debug)
720 {
721 /*
722 * We could have inherited MSR_DE from userspace, since
723 * it doesn't get cleared on exception entry. Make sure
724 * MSR_DE is clear before we enable any debug events.
725 */
726 mtmsr(mfmsr() & ~MSR_DE);
727
728 mtspr(SPRN_IAC1, debug->iac1);
729 mtspr(SPRN_IAC2, debug->iac2);
730 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
731 mtspr(SPRN_IAC3, debug->iac3);
732 mtspr(SPRN_IAC4, debug->iac4);
733 #endif
734 mtspr(SPRN_DAC1, debug->dac1);
735 mtspr(SPRN_DAC2, debug->dac2);
736 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
737 mtspr(SPRN_DVC1, debug->dvc1);
738 mtspr(SPRN_DVC2, debug->dvc2);
739 #endif
740 mtspr(SPRN_DBCR0, debug->dbcr0);
741 mtspr(SPRN_DBCR1, debug->dbcr1);
742 #ifdef CONFIG_BOOKE
743 mtspr(SPRN_DBCR2, debug->dbcr2);
744 #endif
745 }
746 /*
747 * Unless neither the old or new thread are making use of the
748 * debug registers, set the debug registers from the values
749 * stored in the new thread.
750 */
751 void switch_booke_debug_regs(struct debug_reg *new_debug)
752 {
753 if ((current->thread.debug.dbcr0 & DBCR0_IDM)
754 || (new_debug->dbcr0 & DBCR0_IDM))
755 prime_debug_regs(new_debug);
756 }
757 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
758 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
759 #ifndef CONFIG_HAVE_HW_BREAKPOINT
760 static void set_breakpoint(int i, struct arch_hw_breakpoint *brk)
761 {
762 preempt_disable();
763 __set_breakpoint(i, brk);
764 preempt_enable();
765 }
766
767 static void set_debug_reg_defaults(struct thread_struct *thread)
768 {
769 int i;
770 struct arch_hw_breakpoint null_brk = {0};
771
772 for (i = 0; i < nr_wp_slots(); i++) {
773 thread->hw_brk[i] = null_brk;
774 if (ppc_breakpoint_available())
775 set_breakpoint(i, &thread->hw_brk[i]);
776 }
777 }
778
779 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
780 struct arch_hw_breakpoint *b)
781 {
782 if (a->address != b->address)
783 return false;
784 if (a->type != b->type)
785 return false;
786 if (a->len != b->len)
787 return false;
788 /* no need to check hw_len. it's calculated from address and len */
789 return true;
790 }
791
792 static void switch_hw_breakpoint(struct task_struct *new)
793 {
794 int i;
795
796 for (i = 0; i < nr_wp_slots(); i++) {
797 if (likely(hw_brk_match(this_cpu_ptr(¤t_brk[i]),
798 &new->thread.hw_brk[i])))
799 continue;
800
801 __set_breakpoint(i, &new->thread.hw_brk[i]);
802 }
803 }
804 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
805 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
806
807 static inline int set_dabr(struct arch_hw_breakpoint *brk)
808 {
809 unsigned long dabr, dabrx;
810
811 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
812 dabrx = ((brk->type >> 3) & 0x7);
813
814 if (ppc_md.set_dabr)
815 return ppc_md.set_dabr(dabr, dabrx);
816
817 if (IS_ENABLED(CONFIG_PPC_ADV_DEBUG_REGS)) {
818 mtspr(SPRN_DAC1, dabr);
819 if (IS_ENABLED(CONFIG_PPC_47x))
820 isync();
821 return 0;
822 } else if (IS_ENABLED(CONFIG_PPC_BOOK3S)) {
823 mtspr(SPRN_DABR, dabr);
824 if (cpu_has_feature(CPU_FTR_DABRX))
825 mtspr(SPRN_DABRX, dabrx);
826 return 0;
827 } else {
828 return -EINVAL;
829 }
830 }
831
832 static inline int set_breakpoint_8xx(struct arch_hw_breakpoint *brk)
833 {
834 unsigned long lctrl1 = LCTRL1_CTE_GT | LCTRL1_CTF_LT | LCTRL1_CRWE_RW |
835 LCTRL1_CRWF_RW;
836 unsigned long lctrl2 = LCTRL2_LW0EN | LCTRL2_LW0LADC | LCTRL2_SLW0EN;
837 unsigned long start_addr = ALIGN_DOWN(brk->address, HW_BREAKPOINT_SIZE);
838 unsigned long end_addr = ALIGN(brk->address + brk->len, HW_BREAKPOINT_SIZE);
839
840 if (start_addr == 0)
841 lctrl2 |= LCTRL2_LW0LA_F;
842 else if (end_addr == 0)
843 lctrl2 |= LCTRL2_LW0LA_E;
844 else
845 lctrl2 |= LCTRL2_LW0LA_EandF;
846
847 mtspr(SPRN_LCTRL2, 0);
848
849 if ((brk->type & HW_BRK_TYPE_RDWR) == 0)
850 return 0;
851
852 if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ)
853 lctrl1 |= LCTRL1_CRWE_RO | LCTRL1_CRWF_RO;
854 if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE)
855 lctrl1 |= LCTRL1_CRWE_WO | LCTRL1_CRWF_WO;
856
857 mtspr(SPRN_CMPE, start_addr - 1);
858 mtspr(SPRN_CMPF, end_addr);
859 mtspr(SPRN_LCTRL1, lctrl1);
860 mtspr(SPRN_LCTRL2, lctrl2);
861
862 return 0;
863 }
864
865 static void set_hw_breakpoint(int nr, struct arch_hw_breakpoint *brk)
866 {
867 if (dawr_enabled())
868 // Power8 or later
869 set_dawr(nr, brk);
870 else if (IS_ENABLED(CONFIG_PPC_8xx))
871 set_breakpoint_8xx(brk);
872 else if (!cpu_has_feature(CPU_FTR_ARCH_207S))
873 // Power7 or earlier
874 set_dabr(brk);
875 else
876 // Shouldn't happen due to higher level checks
877 WARN_ON_ONCE(1);
878 }
879
880 void __set_breakpoint(int nr, struct arch_hw_breakpoint *brk)
881 {
882 memcpy(this_cpu_ptr(¤t_brk[nr]), brk, sizeof(*brk));
883 set_hw_breakpoint(nr, brk);
884 }
885
886 /* Check if we have DAWR or DABR hardware */
887 bool ppc_breakpoint_available(void)
888 {
889 if (dawr_enabled())
890 return true; /* POWER8 DAWR or POWER9 forced DAWR */
891 if (cpu_has_feature(CPU_FTR_ARCH_207S))
892 return false; /* POWER9 with DAWR disabled */
893 /* DABR: Everything but POWER8 and POWER9 */
894 return true;
895 }
896 EXPORT_SYMBOL_GPL(ppc_breakpoint_available);
897
898 /* Disable the breakpoint in hardware without touching current_brk[] */
899 void suspend_breakpoints(void)
900 {
901 struct arch_hw_breakpoint brk = {0};
902 int i;
903
904 if (!ppc_breakpoint_available())
905 return;
906
907 for (i = 0; i < nr_wp_slots(); i++)
908 set_hw_breakpoint(i, &brk);
909 }
910
911 /*
912 * Re-enable breakpoints suspended by suspend_breakpoints() in hardware
913 * from current_brk[]
914 */
915 void restore_breakpoints(void)
916 {
917 int i;
918
919 if (!ppc_breakpoint_available())
920 return;
921
922 for (i = 0; i < nr_wp_slots(); i++)
923 set_hw_breakpoint(i, this_cpu_ptr(¤t_brk[i]));
924 }
925
926 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
927
928 static inline bool tm_enabled(struct task_struct *tsk)
929 {
930 return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM);
931 }
932
933 static void tm_reclaim_thread(struct thread_struct *thr, uint8_t cause)
934 {
935 /*
936 * Use the current MSR TM suspended bit to track if we have
937 * checkpointed state outstanding.
938 * On signal delivery, we'd normally reclaim the checkpointed
939 * state to obtain stack pointer (see:get_tm_stackpointer()).
940 * This will then directly return to userspace without going
941 * through __switch_to(). However, if the stack frame is bad,
942 * we need to exit this thread which calls __switch_to() which
943 * will again attempt to reclaim the already saved tm state.
944 * Hence we need to check that we've not already reclaimed
945 * this state.
946 * We do this using the current MSR, rather tracking it in
947 * some specific thread_struct bit, as it has the additional
948 * benefit of checking for a potential TM bad thing exception.
949 */
950 if (!MSR_TM_SUSPENDED(mfmsr()))
951 return;
952
953 giveup_all(container_of(thr, struct task_struct, thread));
954
955 tm_reclaim(thr, cause);
956
957 /*
958 * If we are in a transaction and FP is off then we can't have
959 * used FP inside that transaction. Hence the checkpointed
960 * state is the same as the live state. We need to copy the
961 * live state to the checkpointed state so that when the
962 * transaction is restored, the checkpointed state is correct
963 * and the aborted transaction sees the correct state. We use
964 * ckpt_regs.msr here as that's what tm_reclaim will use to
965 * determine if it's going to write the checkpointed state or
966 * not. So either this will write the checkpointed registers,
967 * or reclaim will. Similarly for VMX.
968 */
969 if ((thr->ckpt_regs.msr & MSR_FP) == 0)
970 memcpy(&thr->ckfp_state, &thr->fp_state,
971 sizeof(struct thread_fp_state));
972 if ((thr->ckpt_regs.msr & MSR_VEC) == 0)
973 memcpy(&thr->ckvr_state, &thr->vr_state,
974 sizeof(struct thread_vr_state));
975 }
976
977 void tm_reclaim_current(uint8_t cause)
978 {
979 tm_enable();
980 tm_reclaim_thread(¤t->thread, cause);
981 }
982
983 static inline void tm_reclaim_task(struct task_struct *tsk)
984 {
985 /* We have to work out if we're switching from/to a task that's in the
986 * middle of a transaction.
987 *
988 * In switching we need to maintain a 2nd register state as
989 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
990 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
991 * ckvr_state
992 *
993 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
994 */
995 struct thread_struct *thr = &tsk->thread;
996
997 if (!thr->regs)
998 return;
999
1000 if (!MSR_TM_ACTIVE(thr->regs->msr))
1001 goto out_and_saveregs;
1002
1003 WARN_ON(tm_suspend_disabled);
1004
1005 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
1006 "ccr=%lx, msr=%lx, trap=%lx)\n",
1007 tsk->pid, thr->regs->nip,
1008 thr->regs->ccr, thr->regs->msr,
1009 thr->regs->trap);
1010
1011 tm_reclaim_thread(thr, TM_CAUSE_RESCHED);
1012
1013 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
1014 tsk->pid);
1015
1016 out_and_saveregs:
1017 /* Always save the regs here, even if a transaction's not active.
1018 * This context-switches a thread's TM info SPRs. We do it here to
1019 * be consistent with the restore path (in recheckpoint) which
1020 * cannot happen later in _switch().
1021 */
1022 tm_save_sprs(thr);
1023 }
1024
1025 extern void __tm_recheckpoint(struct thread_struct *thread);
1026
1027 void tm_recheckpoint(struct thread_struct *thread)
1028 {
1029 unsigned long flags;
1030
1031 if (!(thread->regs->msr & MSR_TM))
1032 return;
1033
1034 /* We really can't be interrupted here as the TEXASR registers can't
1035 * change and later in the trecheckpoint code, we have a userspace R1.
1036 * So let's hard disable over this region.
1037 */
1038 local_irq_save(flags);
1039 hard_irq_disable();
1040
1041 /* The TM SPRs are restored here, so that TEXASR.FS can be set
1042 * before the trecheckpoint and no explosion occurs.
1043 */
1044 tm_restore_sprs(thread);
1045
1046 __tm_recheckpoint(thread);
1047
1048 local_irq_restore(flags);
1049 }
1050
1051 static inline void tm_recheckpoint_new_task(struct task_struct *new)
1052 {
1053 if (!cpu_has_feature(CPU_FTR_TM))
1054 return;
1055
1056 /* Recheckpoint the registers of the thread we're about to switch to.
1057 *
1058 * If the task was using FP, we non-lazily reload both the original and
1059 * the speculative FP register states. This is because the kernel
1060 * doesn't see if/when a TM rollback occurs, so if we take an FP
1061 * unavailable later, we are unable to determine which set of FP regs
1062 * need to be restored.
1063 */
1064 if (!tm_enabled(new))
1065 return;
1066
1067 if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
1068 tm_restore_sprs(&new->thread);
1069 return;
1070 }
1071 /* Recheckpoint to restore original checkpointed register state. */
1072 TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n",
1073 new->pid, new->thread.regs->msr);
1074
1075 tm_recheckpoint(&new->thread);
1076
1077 /*
1078 * The checkpointed state has been restored but the live state has
1079 * not, ensure all the math functionality is turned off to trigger
1080 * restore_math() to reload.
1081 */
1082 new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
1083
1084 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
1085 "(kernel msr 0x%lx)\n",
1086 new->pid, mfmsr());
1087 }
1088
1089 static inline void __switch_to_tm(struct task_struct *prev,
1090 struct task_struct *new)
1091 {
1092 if (cpu_has_feature(CPU_FTR_TM)) {
1093 if (tm_enabled(prev) || tm_enabled(new))
1094 tm_enable();
1095
1096 if (tm_enabled(prev)) {
1097 prev->thread.load_tm++;
1098 tm_reclaim_task(prev);
1099 if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
1100 prev->thread.regs->msr &= ~MSR_TM;
1101 }
1102
1103 tm_recheckpoint_new_task(new);
1104 }
1105 }
1106
1107 /*
1108 * This is called if we are on the way out to userspace and the
1109 * TIF_RESTORE_TM flag is set. It checks if we need to reload
1110 * FP and/or vector state and does so if necessary.
1111 * If userspace is inside a transaction (whether active or
1112 * suspended) and FP/VMX/VSX instructions have ever been enabled
1113 * inside that transaction, then we have to keep them enabled
1114 * and keep the FP/VMX/VSX state loaded while ever the transaction
1115 * continues. The reason is that if we didn't, and subsequently
1116 * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1117 * we don't know whether it's the same transaction, and thus we
1118 * don't know which of the checkpointed state and the transactional
1119 * state to use.
1120 */
1121 void restore_tm_state(struct pt_regs *regs)
1122 {
1123 unsigned long msr_diff;
1124
1125 /*
1126 * This is the only moment we should clear TIF_RESTORE_TM as
1127 * it is here that ckpt_regs.msr and pt_regs.msr become the same
1128 * again, anything else could lead to an incorrect ckpt_msr being
1129 * saved and therefore incorrect signal contexts.
1130 */
1131 clear_thread_flag(TIF_RESTORE_TM);
1132 if (!MSR_TM_ACTIVE(regs->msr))
1133 return;
1134
1135 msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
1136 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
1137
1138 /* Ensure that restore_math() will restore */
1139 if (msr_diff & MSR_FP)
1140 current->thread.load_fp = 1;
1141 #ifdef CONFIG_ALTIVEC
1142 if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1143 current->thread.load_vec = 1;
1144 #endif
1145 restore_math(regs);
1146
1147 regs_set_return_msr(regs, regs->msr | msr_diff);
1148 }
1149
1150 #else /* !CONFIG_PPC_TRANSACTIONAL_MEM */
1151 #define tm_recheckpoint_new_task(new)
1152 #define __switch_to_tm(prev, new)
1153 void tm_reclaim_current(uint8_t cause) {}
1154 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1155
1156 static inline void save_sprs(struct thread_struct *t)
1157 {
1158 #ifdef CONFIG_ALTIVEC
1159 if (cpu_has_feature(CPU_FTR_ALTIVEC))
1160 t->vrsave = mfspr(SPRN_VRSAVE);
1161 #endif
1162 #ifdef CONFIG_SPE
1163 if (cpu_has_feature(CPU_FTR_SPE))
1164 t->spefscr = mfspr(SPRN_SPEFSCR);
1165 #endif
1166 #ifdef CONFIG_PPC_BOOK3S_64
1167 if (cpu_has_feature(CPU_FTR_DSCR))
1168 t->dscr = mfspr(SPRN_DSCR);
1169
1170 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1171 t->bescr = mfspr(SPRN_BESCR);
1172 t->ebbhr = mfspr(SPRN_EBBHR);
1173 t->ebbrr = mfspr(SPRN_EBBRR);
1174
1175 t->fscr = mfspr(SPRN_FSCR);
1176
1177 /*
1178 * Note that the TAR is not available for use in the kernel.
1179 * (To provide this, the TAR should be backed up/restored on
1180 * exception entry/exit instead, and be in pt_regs. FIXME,
1181 * this should be in pt_regs anyway (for debug).)
1182 */
1183 t->tar = mfspr(SPRN_TAR);
1184 }
1185
1186 if (cpu_has_feature(CPU_FTR_DEXCR_NPHIE))
1187 t->hashkeyr = mfspr(SPRN_HASHKEYR);
1188
1189 if (cpu_has_feature(CPU_FTR_ARCH_31))
1190 t->dexcr = mfspr(SPRN_DEXCR);
1191 #endif
1192 }
1193
1194 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
1195 void kvmppc_save_user_regs(void)
1196 {
1197 unsigned long usermsr;
1198
1199 if (!current->thread.regs)
1200 return;
1201
1202 usermsr = current->thread.regs->msr;
1203
1204 /* Caller has enabled FP/VEC/VSX/TM in MSR */
1205 if (usermsr & MSR_FP)
1206 __giveup_fpu(current);
1207 if (usermsr & MSR_VEC)
1208 __giveup_altivec(current);
1209
1210 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1211 if (usermsr & MSR_TM) {
1212 current->thread.tm_tfhar = mfspr(SPRN_TFHAR);
1213 current->thread.tm_tfiar = mfspr(SPRN_TFIAR);
1214 current->thread.tm_texasr = mfspr(SPRN_TEXASR);
1215 current->thread.regs->msr &= ~MSR_TM;
1216 }
1217 #endif
1218 }
1219 EXPORT_SYMBOL_GPL(kvmppc_save_user_regs);
1220
1221 void kvmppc_save_current_sprs(void)
1222 {
1223 save_sprs(¤t->thread);
1224 }
1225 EXPORT_SYMBOL_GPL(kvmppc_save_current_sprs);
1226 #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
1227
1228 static inline void restore_sprs(struct thread_struct *old_thread,
1229 struct thread_struct *new_thread)
1230 {
1231 #ifdef CONFIG_ALTIVEC
1232 if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1233 old_thread->vrsave != new_thread->vrsave)
1234 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1235 #endif
1236 #ifdef CONFIG_SPE
1237 if (cpu_has_feature(CPU_FTR_SPE) &&
1238 old_thread->spefscr != new_thread->spefscr)
1239 mtspr(SPRN_SPEFSCR, new_thread->spefscr);
1240 #endif
1241 #ifdef CONFIG_PPC_BOOK3S_64
1242 if (cpu_has_feature(CPU_FTR_DSCR)) {
1243 u64 dscr = get_paca()->dscr_default;
1244 if (new_thread->dscr_inherit)
1245 dscr = new_thread->dscr;
1246
1247 if (old_thread->dscr != dscr)
1248 mtspr(SPRN_DSCR, dscr);
1249 }
1250
1251 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1252 if (old_thread->bescr != new_thread->bescr)
1253 mtspr(SPRN_BESCR, new_thread->bescr);
1254 if (old_thread->ebbhr != new_thread->ebbhr)
1255 mtspr(SPRN_EBBHR, new_thread->ebbhr);
1256 if (old_thread->ebbrr != new_thread->ebbrr)
1257 mtspr(SPRN_EBBRR, new_thread->ebbrr);
1258
1259 if (old_thread->fscr != new_thread->fscr)
1260 mtspr(SPRN_FSCR, new_thread->fscr);
1261
1262 if (old_thread->tar != new_thread->tar)
1263 mtspr(SPRN_TAR, new_thread->tar);
1264 }
1265
1266 if (cpu_has_feature(CPU_FTR_P9_TIDR) &&
1267 old_thread->tidr != new_thread->tidr)
1268 mtspr(SPRN_TIDR, new_thread->tidr);
1269
1270 if (cpu_has_feature(CPU_FTR_DEXCR_NPHIE) &&
1271 old_thread->hashkeyr != new_thread->hashkeyr)
1272 mtspr(SPRN_HASHKEYR, new_thread->hashkeyr);
1273
1274 if (cpu_has_feature(CPU_FTR_ARCH_31) &&
1275 old_thread->dexcr != new_thread->dexcr)
1276 mtspr(SPRN_DEXCR, new_thread->dexcr);
1277 #endif
1278
1279 }
1280
1281 struct task_struct *__switch_to(struct task_struct *prev,
1282 struct task_struct *new)
1283 {
1284 struct thread_struct *new_thread, *old_thread;
1285 struct task_struct *last;
1286 #ifdef CONFIG_PPC_64S_HASH_MMU
1287 struct ppc64_tlb_batch *batch;
1288 #endif
1289
1290 new_thread = &new->thread;
1291 old_thread = ¤t->thread;
1292
1293 WARN_ON(!irqs_disabled());
1294
1295 #ifdef CONFIG_PPC_64S_HASH_MMU
1296 batch = this_cpu_ptr(&ppc64_tlb_batch);
1297 if (batch->active) {
1298 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1299 if (batch->index)
1300 __flush_tlb_pending(batch);
1301 batch->active = 0;
1302 }
1303
1304 /*
1305 * On POWER9 the copy-paste buffer can only paste into
1306 * foreign real addresses, so unprivileged processes can not
1307 * see the data or use it in any way unless they have
1308 * foreign real mappings. If the new process has the foreign
1309 * real address mappings, we must issue a cp_abort to clear
1310 * any state and prevent snooping, corruption or a covert
1311 * channel. ISA v3.1 supports paste into local memory.
1312 */
1313 if (new->mm && (cpu_has_feature(CPU_FTR_ARCH_31) ||
1314 atomic_read(&new->mm->context.vas_windows)))
1315 asm volatile(PPC_CP_ABORT);
1316 #endif /* CONFIG_PPC_BOOK3S_64 */
1317
1318 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1319 switch_booke_debug_regs(&new->thread.debug);
1320 #else
1321 /*
1322 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1323 * schedule DABR
1324 */
1325 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1326 switch_hw_breakpoint(new);
1327 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1328 #endif
1329
1330 /*
1331 * We need to save SPRs before treclaim/trecheckpoint as these will
1332 * change a number of them.
1333 */
1334 save_sprs(&prev->thread);
1335
1336 /* Save FPU, Altivec, VSX and SPE state */
1337 giveup_all(prev);
1338
1339 __switch_to_tm(prev, new);
1340
1341 if (!radix_enabled()) {
1342 /*
1343 * We can't take a PMU exception inside _switch() since there
1344 * is a window where the kernel stack SLB and the kernel stack
1345 * are out of sync. Hard disable here.
1346 */
1347 hard_irq_disable();
1348 }
1349
1350 /*
1351 * Call restore_sprs() and set_return_regs_changed() before calling
1352 * _switch(). If we move it after _switch() then we miss out on calling
1353 * it for new tasks. The reason for this is we manually create a stack
1354 * frame for new tasks that directly returns through ret_from_fork() or
1355 * ret_from_kernel_thread(). See copy_thread() for details.
1356 */
1357 restore_sprs(old_thread, new_thread);
1358
1359 set_return_regs_changed(); /* _switch changes stack (and regs) */
1360
1361 if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64))
1362 kuap_assert_locked();
1363
1364 last = _switch(old_thread, new_thread);
1365
1366 /*
1367 * Nothing after _switch will be run for newly created tasks,
1368 * because they switch directly to ret_from_fork/ret_from_kernel_thread
1369 * etc. Code added here should have a comment explaining why that is
1370 * okay.
1371 */
1372
1373 #ifdef CONFIG_PPC_BOOK3S_64
1374 #ifdef CONFIG_PPC_64S_HASH_MMU
1375 /*
1376 * This applies to a process that was context switched while inside
1377 * arch_enter_lazy_mmu_mode(), to re-activate the batch that was
1378 * deactivated above, before _switch(). This will never be the case
1379 * for new tasks.
1380 */
1381 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1382 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1383 batch = this_cpu_ptr(&ppc64_tlb_batch);
1384 batch->active = 1;
1385 }
1386 #endif
1387
1388 /*
1389 * Math facilities are masked out of the child MSR in copy_thread.
1390 * A new task does not need to restore_math because it will
1391 * demand fault them.
1392 */
1393 if (current->thread.regs)
1394 restore_math(current->thread.regs);
1395 #endif /* CONFIG_PPC_BOOK3S_64 */
1396
1397 return last;
1398 }
1399
1400 #define NR_INSN_TO_PRINT 16
1401
1402 static void show_instructions(struct pt_regs *regs)
1403 {
1404 int i;
1405 unsigned long nip = regs->nip;
1406 unsigned long pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int));
1407
1408 printk("Code: ");
1409
1410 /*
1411 * If we were executing with the MMU off for instructions, adjust pc
1412 * rather than printing XXXXXXXX.
1413 */
1414 if (!IS_ENABLED(CONFIG_BOOKE) && !(regs->msr & MSR_IR)) {
1415 pc = (unsigned long)phys_to_virt(pc);
1416 nip = (unsigned long)phys_to_virt(regs->nip);
1417 }
1418
1419 for (i = 0; i < NR_INSN_TO_PRINT; i++) {
1420 int instr;
1421
1422 if (get_kernel_nofault(instr, (const void *)pc)) {
1423 pr_cont("XXXXXXXX ");
1424 } else {
1425 if (nip == pc)
1426 pr_cont("<%08x> ", instr);
1427 else
1428 pr_cont("%08x ", instr);
1429 }
1430
1431 pc += sizeof(int);
1432 }
1433
1434 pr_cont("\n");
1435 }
1436
1437 void show_user_instructions(struct pt_regs *regs)
1438 {
1439 unsigned long pc;
1440 int n = NR_INSN_TO_PRINT;
1441 struct seq_buf s;
1442 char buf[96]; /* enough for 8 times 9 + 2 chars */
1443
1444 pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int));
1445
1446 seq_buf_init(&s, buf, sizeof(buf));
1447
1448 while (n) {
1449 int i;
1450
1451 seq_buf_clear(&s);
1452
1453 for (i = 0; i < 8 && n; i++, n--, pc += sizeof(int)) {
1454 int instr;
1455
1456 if (copy_from_user_nofault(&instr, (void __user *)pc,
1457 sizeof(instr))) {
1458 seq_buf_printf(&s, "XXXXXXXX ");
1459 continue;
1460 }
1461 seq_buf_printf(&s, regs->nip == pc ? "<%08x> " : "%08x ", instr);
1462 }
1463
1464 if (!seq_buf_has_overflowed(&s))
1465 pr_info("%s[%d]: code: %s\n", current->comm,
1466 current->pid, s.buffer);
1467 }
1468 }
1469
1470 struct regbit {
1471 unsigned long bit;
1472 const char *name;
1473 };
1474
1475 static struct regbit msr_bits[] = {
1476 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1477 {MSR_SF, "SF"},
1478 {MSR_HV, "HV"},
1479 #endif
1480 {MSR_VEC, "VEC"},
1481 {MSR_VSX, "VSX"},
1482 #ifdef CONFIG_BOOKE
1483 {MSR_CE, "CE"},
1484 #endif
1485 {MSR_EE, "EE"},
1486 {MSR_PR, "PR"},
1487 {MSR_FP, "FP"},
1488 {MSR_ME, "ME"},
1489 #ifdef CONFIG_BOOKE
1490 {MSR_DE, "DE"},
1491 #else
1492 {MSR_SE, "SE"},
1493 {MSR_BE, "BE"},
1494 #endif
1495 {MSR_IR, "IR"},
1496 {MSR_DR, "DR"},
1497 {MSR_PMM, "PMM"},
1498 #ifndef CONFIG_BOOKE
1499 {MSR_RI, "RI"},
1500 {MSR_LE, "LE"},
1501 #endif
1502 {0, NULL}
1503 };
1504
1505 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1506 {
1507 const char *s = "";
1508
1509 for (; bits->bit; ++bits)
1510 if (val & bits->bit) {
1511 pr_cont("%s%s", s, bits->name);
1512 s = sep;
1513 }
1514 }
1515
1516 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1517 static struct regbit msr_tm_bits[] = {
1518 {MSR_TS_T, "T"},
1519 {MSR_TS_S, "S"},
1520 {MSR_TM, "E"},
1521 {0, NULL}
1522 };
1523
1524 static void print_tm_bits(unsigned long val)
1525 {
1526 /*
1527 * This only prints something if at least one of the TM bit is set.
1528 * Inside the TM[], the output means:
1529 * E: Enabled (bit 32)
1530 * S: Suspended (bit 33)
1531 * T: Transactional (bit 34)
1532 */
1533 if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1534 pr_cont(",TM[");
1535 print_bits(val, msr_tm_bits, "");
1536 pr_cont("]");
1537 }
1538 }
1539 #else
1540 static void print_tm_bits(unsigned long val) {}
1541 #endif
1542
1543 static void print_msr_bits(unsigned long val)
1544 {
1545 pr_cont("<");
1546 print_bits(val, msr_bits, ",");
1547 print_tm_bits(val);
1548 pr_cont(">");
1549 }
1550
1551 #ifdef CONFIG_PPC64
1552 #define REG "%016lx"
1553 #define REGS_PER_LINE 4
1554 #else
1555 #define REG "%08lx"
1556 #define REGS_PER_LINE 8
1557 #endif
1558
1559 static void __show_regs(struct pt_regs *regs)
1560 {
1561 int i, trap;
1562
1563 printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1564 regs->nip, regs->link, regs->ctr);
1565 printk("REGS: %px TRAP: %04lx %s (%s)\n",
1566 regs, regs->trap, print_tainted(), init_utsname()->release);
1567 printk("MSR: "REG" ", regs->msr);
1568 print_msr_bits(regs->msr);
1569 pr_cont(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
1570 trap = TRAP(regs);
1571 if (!trap_is_syscall(regs) && cpu_has_feature(CPU_FTR_CFAR))
1572 pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1573 if (trap == INTERRUPT_MACHINE_CHECK ||
1574 trap == INTERRUPT_DATA_STORAGE ||
1575 trap == INTERRUPT_ALIGNMENT) {
1576 if (IS_ENABLED(CONFIG_BOOKE))
1577 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dear, regs->esr);
1578 else
1579 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1580 }
1581
1582 #ifdef CONFIG_PPC64
1583 pr_cont("IRQMASK: %lx ", regs->softe);
1584 #endif
1585 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1586 if (MSR_TM_ACTIVE(regs->msr))
1587 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1588 #endif
1589
1590 for (i = 0; i < 32; i++) {
1591 if ((i % REGS_PER_LINE) == 0)
1592 pr_cont("\nGPR%02d: ", i);
1593 pr_cont(REG " ", regs->gpr[i]);
1594 }
1595 pr_cont("\n");
1596 /*
1597 * Lookup NIP late so we have the best change of getting the
1598 * above info out without failing
1599 */
1600 if (IS_ENABLED(CONFIG_KALLSYMS)) {
1601 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1602 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1603 }
1604 }
1605
1606 void show_regs(struct pt_regs *regs)
1607 {
1608 show_regs_print_info(KERN_DEFAULT);
1609 __show_regs(regs);
1610 show_stack(current, (unsigned long *) regs->gpr[1], KERN_DEFAULT);
1611 if (!user_mode(regs))
1612 show_instructions(regs);
1613 }
1614
1615 void flush_thread(void)
1616 {
1617 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1618 flush_ptrace_hw_breakpoint(current);
1619 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1620 set_debug_reg_defaults(¤t->thread);
1621 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1622 }
1623
1624 void arch_setup_new_exec(void)
1625 {
1626
1627 #ifdef CONFIG_PPC_BOOK3S_64
1628 if (!radix_enabled())
1629 hash__setup_new_exec();
1630 #endif
1631 /*
1632 * If we exec out of a kernel thread then thread.regs will not be
1633 * set. Do it now.
1634 */
1635 if (!current->thread.regs) {
1636 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1637 current->thread.regs = regs - 1;
1638 }
1639
1640 #ifdef CONFIG_PPC_MEM_KEYS
1641 current->thread.regs->amr = default_amr;
1642 current->thread.regs->iamr = default_iamr;
1643 #endif
1644
1645 #ifdef CONFIG_PPC_BOOK3S_64
1646 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
1647 current->thread.dexcr = current->thread.dexcr_onexec;
1648 mtspr(SPRN_DEXCR, current->thread.dexcr);
1649 }
1650 #endif /* CONFIG_PPC_BOOK3S_64 */
1651 }
1652
1653 #ifdef CONFIG_PPC64
1654 /*
1655 * Assign a TIDR (thread ID) for task @t and set it in the thread
1656 * structure. For now, we only support setting TIDR for 'current' task.
1657 *
1658 * Since the TID value is a truncated form of it PID, it is possible
1659 * (but unlikely) for 2 threads to have the same TID. In the unlikely event
1660 * that 2 threads share the same TID and are waiting, one of the following
1661 * cases will happen:
1662 *
1663 * 1. The correct thread is running, the wrong thread is not
1664 * In this situation, the correct thread is woken and proceeds to pass its
1665 * condition check.
1666 *
1667 * 2. Neither threads are running
1668 * In this situation, neither thread will be woken. When scheduled, the waiting
1669 * threads will execute either a wait, which will return immediately, followed
1670 * by a condition check, which will pass for the correct thread and fail
1671 * for the wrong thread, or they will execute the condition check immediately.
1672 *
1673 * 3. The wrong thread is running, the correct thread is not
1674 * The wrong thread will be woken, but will fail its condition check and
1675 * re-execute wait. The correct thread, when scheduled, will execute either
1676 * its condition check (which will pass), or wait, which returns immediately
1677 * when called the first time after the thread is scheduled, followed by its
1678 * condition check (which will pass).
1679 *
1680 * 4. Both threads are running
1681 * Both threads will be woken. The wrong thread will fail its condition check
1682 * and execute another wait, while the correct thread will pass its condition
1683 * check.
1684 *
1685 * @t: the task to set the thread ID for
1686 */
1687 int set_thread_tidr(struct task_struct *t)
1688 {
1689 if (!cpu_has_feature(CPU_FTR_P9_TIDR))
1690 return -EINVAL;
1691
1692 if (t != current)
1693 return -EINVAL;
1694
1695 if (t->thread.tidr)
1696 return 0;
1697
1698 t->thread.tidr = (u16)task_pid_nr(t);
1699 mtspr(SPRN_TIDR, t->thread.tidr);
1700
1701 return 0;
1702 }
1703 EXPORT_SYMBOL_GPL(set_thread_tidr);
1704
1705 #endif /* CONFIG_PPC64 */
1706
1707 /*
1708 * this gets called so that we can store coprocessor state into memory and
1709 * copy the current task into the new thread.
1710 */
1711 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1712 {
1713 flush_all_to_thread(src);
1714 /*
1715 * Flush TM state out so we can copy it. __switch_to_tm() does this
1716 * flush but it removes the checkpointed state from the current CPU and
1717 * transitions the CPU out of TM mode. Hence we need to call
1718 * tm_recheckpoint_new_task() (on the same task) to restore the
1719 * checkpointed state back and the TM mode.
1720 *
1721 * Can't pass dst because it isn't ready. Doesn't matter, passing
1722 * dst is only important for __switch_to()
1723 */
1724 __switch_to_tm(src, src);
1725
1726 *dst = *src;
1727
1728 clear_task_ebb(dst);
1729
1730 return 0;
1731 }
1732
1733 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1734 {
1735 #ifdef CONFIG_PPC_64S_HASH_MMU
1736 unsigned long sp_vsid;
1737 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1738
1739 if (radix_enabled())
1740 return;
1741
1742 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1743 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1744 << SLB_VSID_SHIFT_1T;
1745 else
1746 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1747 << SLB_VSID_SHIFT;
1748 sp_vsid |= SLB_VSID_KERNEL | llp;
1749 p->thread.ksp_vsid = sp_vsid;
1750 #endif
1751 }
1752
1753 /*
1754 * Copy a thread..
1755 */
1756
1757 /*
1758 * Copy architecture-specific thread state
1759 */
1760 int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
1761 {
1762 struct pt_regs *kregs; /* Switch frame regs */
1763 extern void ret_from_fork(void);
1764 extern void ret_from_fork_scv(void);
1765 extern void ret_from_kernel_user_thread(void);
1766 extern void start_kernel_thread(void);
1767 void (*f)(void);
1768 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1769 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1770 int i;
1771 #endif
1772
1773 klp_init_thread_info(p);
1774
1775 if (unlikely(p->flags & PF_KTHREAD)) {
1776 /* kernel thread */
1777
1778 /* Create initial minimum stack frame. */
1779 sp -= STACK_FRAME_MIN_SIZE;
1780 ((unsigned long *)sp)[0] = 0;
1781
1782 f = start_kernel_thread;
1783 p->thread.regs = NULL; /* no user register state */
1784 clear_tsk_compat_task(p);
1785 } else {
1786 /* user thread */
1787 struct pt_regs *childregs;
1788
1789 /* Create initial user return stack frame. */
1790 sp -= STACK_USER_INT_FRAME_SIZE;
1791 *(unsigned long *)(sp + STACK_INT_FRAME_MARKER) = STACK_FRAME_REGS_MARKER;
1792
1793 childregs = (struct pt_regs *)(sp + STACK_INT_FRAME_REGS);
1794
1795 if (unlikely(args->fn)) {
1796 /*
1797 * A user space thread, but it first runs a kernel
1798 * thread, and then returns as though it had called
1799 * execve rather than fork, so user regs will be
1800 * filled in (e.g., by kernel_execve()).
1801 */
1802 ((unsigned long *)sp)[0] = 0;
1803 memset(childregs, 0, sizeof(struct pt_regs));
1804 #ifdef CONFIG_PPC64
1805 childregs->softe = IRQS_ENABLED;
1806 #endif
1807 f = ret_from_kernel_user_thread;
1808 } else {
1809 struct pt_regs *regs = current_pt_regs();
1810 unsigned long clone_flags = args->flags;
1811 unsigned long usp = args->stack;
1812
1813 /* Copy registers */
1814 *childregs = *regs;
1815 if (usp)
1816 childregs->gpr[1] = usp;
1817 ((unsigned long *)sp)[0] = childregs->gpr[1];
1818 #ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG
1819 WARN_ON_ONCE(childregs->softe != IRQS_ENABLED);
1820 #endif
1821 if (clone_flags & CLONE_SETTLS) {
1822 unsigned long tls = args->tls;
1823
1824 if (!is_32bit_task())
1825 childregs->gpr[13] = tls;
1826 else
1827 childregs->gpr[2] = tls;
1828 }
1829
1830 if (trap_is_scv(regs))
1831 f = ret_from_fork_scv;
1832 else
1833 f = ret_from_fork;
1834 }
1835
1836 childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1837 p->thread.regs = childregs;
1838 }
1839
1840 /*
1841 * The way this works is that at some point in the future
1842 * some task will call _switch to switch to the new task.
1843 * That will pop off the stack frame created below and start
1844 * the new task running at ret_from_fork. The new task will
1845 * do some house keeping and then return from the fork or clone
1846 * system call, using the stack frame created above.
1847 */
1848 ((unsigned long *)sp)[STACK_FRAME_LR_SAVE] = (unsigned long)f;
1849 sp -= STACK_SWITCH_FRAME_SIZE;
1850 ((unsigned long *)sp)[0] = sp + STACK_SWITCH_FRAME_SIZE;
1851 kregs = (struct pt_regs *)(sp + STACK_SWITCH_FRAME_REGS);
1852 kregs->nip = ppc_function_entry(f);
1853 if (unlikely(args->fn)) {
1854 /*
1855 * Put kthread fn, arg parameters in non-volatile GPRs in the
1856 * switch frame so they are loaded by _switch before it returns
1857 * to ret_from_kernel_thread.
1858 */
1859 kregs->gpr[14] = ppc_function_entry((void *)args->fn);
1860 kregs->gpr[15] = (unsigned long)args->fn_arg;
1861 }
1862 p->thread.ksp = sp;
1863
1864 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1865 for (i = 0; i < nr_wp_slots(); i++)
1866 p->thread.ptrace_bps[i] = NULL;
1867 #endif
1868
1869 #ifdef CONFIG_PPC_FPU_REGS
1870 p->thread.fp_save_area = NULL;
1871 #endif
1872 #ifdef CONFIG_ALTIVEC
1873 p->thread.vr_save_area = NULL;
1874 #endif
1875 #if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP)
1876 p->thread.kuap = KUAP_NONE;
1877 #endif
1878 #if defined(CONFIG_BOOKE) && defined(CONFIG_PPC_KUAP)
1879 p->thread.pid = MMU_NO_CONTEXT;
1880 #endif
1881
1882 setup_ksp_vsid(p, sp);
1883
1884 #ifdef CONFIG_PPC64
1885 if (cpu_has_feature(CPU_FTR_DSCR)) {
1886 p->thread.dscr_inherit = current->thread.dscr_inherit;
1887 p->thread.dscr = mfspr(SPRN_DSCR);
1888 }
1889
1890 p->thread.tidr = 0;
1891 #endif
1892 #ifdef CONFIG_PPC_BOOK3S_64
1893 if (cpu_has_feature(CPU_FTR_DEXCR_NPHIE))
1894 p->thread.hashkeyr = current->thread.hashkeyr;
1895
1896 if (cpu_has_feature(CPU_FTR_ARCH_31))
1897 p->thread.dexcr = mfspr(SPRN_DEXCR);
1898 #endif
1899 return 0;
1900 }
1901
1902 void preload_new_slb_context(unsigned long start, unsigned long sp);
1903
1904 /*
1905 * Set up a thread for executing a new program
1906 */
1907 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1908 {
1909 #ifdef CONFIG_PPC64
1910 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1911
1912 if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && !radix_enabled())
1913 preload_new_slb_context(start, sp);
1914 #endif
1915
1916 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1917 /*
1918 * Clear any transactional state, we're exec()ing. The cause is
1919 * not important as there will never be a recheckpoint so it's not
1920 * user visible.
1921 */
1922 if (MSR_TM_SUSPENDED(mfmsr()))
1923 tm_reclaim_current(0);
1924 #endif
1925
1926 memset(®s->gpr[1], 0, sizeof(regs->gpr) - sizeof(regs->gpr[0]));
1927 regs->ctr = 0;
1928 regs->link = 0;
1929 regs->xer = 0;
1930 regs->ccr = 0;
1931 regs->gpr[1] = sp;
1932
1933 #ifdef CONFIG_PPC32
1934 regs->mq = 0;
1935 regs->nip = start;
1936 regs->msr = MSR_USER;
1937 #else
1938 if (!is_32bit_task()) {
1939 unsigned long entry;
1940
1941 if (is_elf2_task()) {
1942 /* Look ma, no function descriptors! */
1943 entry = start;
1944
1945 /*
1946 * Ulrich says:
1947 * The latest iteration of the ABI requires that when
1948 * calling a function (at its global entry point),
1949 * the caller must ensure r12 holds the entry point
1950 * address (so that the function can quickly
1951 * establish addressability).
1952 */
1953 regs->gpr[12] = start;
1954 /* Make sure that's restored on entry to userspace. */
1955 set_thread_flag(TIF_RESTOREALL);
1956 } else {
1957 unsigned long toc;
1958
1959 /* start is a relocated pointer to the function
1960 * descriptor for the elf _start routine. The first
1961 * entry in the function descriptor is the entry
1962 * address of _start and the second entry is the TOC
1963 * value we need to use.
1964 */
1965 __get_user(entry, (unsigned long __user *)start);
1966 __get_user(toc, (unsigned long __user *)start+1);
1967
1968 /* Check whether the e_entry function descriptor entries
1969 * need to be relocated before we can use them.
1970 */
1971 if (load_addr != 0) {
1972 entry += load_addr;
1973 toc += load_addr;
1974 }
1975 regs->gpr[2] = toc;
1976 }
1977 regs_set_return_ip(regs, entry);
1978 regs_set_return_msr(regs, MSR_USER64);
1979 } else {
1980 regs->gpr[2] = 0;
1981 regs_set_return_ip(regs, start);
1982 regs_set_return_msr(regs, MSR_USER32);
1983 }
1984
1985 #endif
1986 #ifdef CONFIG_VSX
1987 current->thread.used_vsr = 0;
1988 #endif
1989 current->thread.load_slb = 0;
1990 current->thread.load_fp = 0;
1991 #ifdef CONFIG_PPC_FPU_REGS
1992 memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state));
1993 current->thread.fp_save_area = NULL;
1994 #endif
1995 #ifdef CONFIG_ALTIVEC
1996 memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state));
1997 current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1998 current->thread.vr_save_area = NULL;
1999 current->thread.vrsave = 0;
2000 current->thread.used_vr = 0;
2001 current->thread.load_vec = 0;
2002 #endif /* CONFIG_ALTIVEC */
2003 #ifdef CONFIG_SPE
2004 memset(current->thread.evr, 0, sizeof(current->thread.evr));
2005 current->thread.acc = 0;
2006 current->thread.spefscr = 0;
2007 current->thread.used_spe = 0;
2008 #endif /* CONFIG_SPE */
2009 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2010 current->thread.tm_tfhar = 0;
2011 current->thread.tm_texasr = 0;
2012 current->thread.tm_tfiar = 0;
2013 current->thread.load_tm = 0;
2014 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
2015 #ifdef CONFIG_PPC_BOOK3S_64
2016 if (cpu_has_feature(CPU_FTR_DEXCR_NPHIE)) {
2017 current->thread.hashkeyr = get_random_long();
2018 mtspr(SPRN_HASHKEYR, current->thread.hashkeyr);
2019 }
2020 #endif /* CONFIG_PPC_BOOK3S_64 */
2021 }
2022 EXPORT_SYMBOL(start_thread);
2023
2024 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
2025 | PR_FP_EXC_RES | PR_FP_EXC_INV)
2026
2027 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
2028 {
2029 struct pt_regs *regs = tsk->thread.regs;
2030
2031 /* This is a bit hairy. If we are an SPE enabled processor
2032 * (have embedded fp) we store the IEEE exception enable flags in
2033 * fpexc_mode. fpexc_mode is also used for setting FP exception
2034 * mode (asyn, precise, disabled) for 'Classic' FP. */
2035 if (val & PR_FP_EXC_SW_ENABLE) {
2036 if (cpu_has_feature(CPU_FTR_SPE)) {
2037 /*
2038 * When the sticky exception bits are set
2039 * directly by userspace, it must call prctl
2040 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
2041 * in the existing prctl settings) or
2042 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
2043 * the bits being set). <fenv.h> functions
2044 * saving and restoring the whole
2045 * floating-point environment need to do so
2046 * anyway to restore the prctl settings from
2047 * the saved environment.
2048 */
2049 #ifdef CONFIG_SPE
2050 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
2051 tsk->thread.fpexc_mode = val &
2052 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
2053 #endif
2054 return 0;
2055 } else {
2056 return -EINVAL;
2057 }
2058 }
2059
2060 /* on a CONFIG_SPE this does not hurt us. The bits that
2061 * __pack_fe01 use do not overlap with bits used for
2062 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
2063 * on CONFIG_SPE implementations are reserved so writing to
2064 * them does not change anything */
2065 if (val > PR_FP_EXC_PRECISE)
2066 return -EINVAL;
2067 tsk->thread.fpexc_mode = __pack_fe01(val);
2068 if (regs != NULL && (regs->msr & MSR_FP) != 0) {
2069 regs_set_return_msr(regs, (regs->msr & ~(MSR_FE0|MSR_FE1))
2070 | tsk->thread.fpexc_mode);
2071 }
2072 return 0;
2073 }
2074
2075 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
2076 {
2077 unsigned int val = 0;
2078
2079 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) {
2080 if (cpu_has_feature(CPU_FTR_SPE)) {
2081 /*
2082 * When the sticky exception bits are set
2083 * directly by userspace, it must call prctl
2084 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
2085 * in the existing prctl settings) or
2086 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
2087 * the bits being set). <fenv.h> functions
2088 * saving and restoring the whole
2089 * floating-point environment need to do so
2090 * anyway to restore the prctl settings from
2091 * the saved environment.
2092 */
2093 #ifdef CONFIG_SPE
2094 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
2095 val = tsk->thread.fpexc_mode;
2096 #endif
2097 } else
2098 return -EINVAL;
2099 } else {
2100 val = __unpack_fe01(tsk->thread.fpexc_mode);
2101 }
2102 return put_user(val, (unsigned int __user *) adr);
2103 }
2104
2105 int set_endian(struct task_struct *tsk, unsigned int val)
2106 {
2107 struct pt_regs *regs = tsk->thread.regs;
2108
2109 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
2110 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
2111 return -EINVAL;
2112
2113 if (regs == NULL)
2114 return -EINVAL;
2115
2116 if (val == PR_ENDIAN_BIG)
2117 regs_set_return_msr(regs, regs->msr & ~MSR_LE);
2118 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
2119 regs_set_return_msr(regs, regs->msr | MSR_LE);
2120 else
2121 return -EINVAL;
2122
2123 return 0;
2124 }
2125
2126 int get_endian(struct task_struct *tsk, unsigned long adr)
2127 {
2128 struct pt_regs *regs = tsk->thread.regs;
2129 unsigned int val;
2130
2131 if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
2132 !cpu_has_feature(CPU_FTR_REAL_LE))
2133 return -EINVAL;
2134
2135 if (regs == NULL)
2136 return -EINVAL;
2137
2138 if (regs->msr & MSR_LE) {
2139 if (cpu_has_feature(CPU_FTR_REAL_LE))
2140 val = PR_ENDIAN_LITTLE;
2141 else
2142 val = PR_ENDIAN_PPC_LITTLE;
2143 } else
2144 val = PR_ENDIAN_BIG;
2145
2146 return put_user(val, (unsigned int __user *)adr);
2147 }
2148
2149 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
2150 {
2151 tsk->thread.align_ctl = val;
2152 return 0;
2153 }
2154
2155 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
2156 {
2157 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
2158 }
2159
2160 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
2161 unsigned long nbytes)
2162 {
2163 unsigned long stack_page;
2164 unsigned long cpu = task_cpu(p);
2165
2166 if (!hardirq_ctx[cpu] || !softirq_ctx[cpu])
2167 return 0;
2168
2169 stack_page = (unsigned long)hardirq_ctx[cpu];
2170 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2171 return 1;
2172
2173 stack_page = (unsigned long)softirq_ctx[cpu];
2174 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2175 return 1;
2176
2177 return 0;
2178 }
2179
2180 static inline int valid_emergency_stack(unsigned long sp, struct task_struct *p,
2181 unsigned long nbytes)
2182 {
2183 #ifdef CONFIG_PPC64
2184 unsigned long stack_page;
2185 unsigned long cpu = task_cpu(p);
2186
2187 if (!paca_ptrs)
2188 return 0;
2189
2190 if (!paca_ptrs[cpu]->emergency_sp)
2191 return 0;
2192
2193 # ifdef CONFIG_PPC_BOOK3S_64
2194 if (!paca_ptrs[cpu]->nmi_emergency_sp || !paca_ptrs[cpu]->mc_emergency_sp)
2195 return 0;
2196 #endif
2197
2198 stack_page = (unsigned long)paca_ptrs[cpu]->emergency_sp - THREAD_SIZE;
2199 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2200 return 1;
2201
2202 # ifdef CONFIG_PPC_BOOK3S_64
2203 stack_page = (unsigned long)paca_ptrs[cpu]->nmi_emergency_sp - THREAD_SIZE;
2204 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2205 return 1;
2206
2207 stack_page = (unsigned long)paca_ptrs[cpu]->mc_emergency_sp - THREAD_SIZE;
2208 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2209 return 1;
2210 # endif
2211 #endif
2212
2213 return 0;
2214 }
2215
2216 /*
2217 * validate the stack frame of a particular minimum size, used for when we are
2218 * looking at a certain object in the stack beyond the minimum.
2219 */
2220 int validate_sp_size(unsigned long sp, struct task_struct *p,
2221 unsigned long nbytes)
2222 {
2223 unsigned long stack_page = (unsigned long)task_stack_page(p);
2224
2225 if (sp < THREAD_SIZE)
2226 return 0;
2227
2228 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2229 return 1;
2230
2231 if (valid_irq_stack(sp, p, nbytes))
2232 return 1;
2233
2234 return valid_emergency_stack(sp, p, nbytes);
2235 }
2236
2237 int validate_sp(unsigned long sp, struct task_struct *p)
2238 {
2239 return validate_sp_size(sp, p, STACK_FRAME_MIN_SIZE);
2240 }
2241
2242 static unsigned long ___get_wchan(struct task_struct *p)
2243 {
2244 unsigned long ip, sp;
2245 int count = 0;
2246
2247 sp = p->thread.ksp;
2248 if (!validate_sp(sp, p))
2249 return 0;
2250
2251 do {
2252 sp = READ_ONCE_NOCHECK(*(unsigned long *)sp);
2253 if (!validate_sp(sp, p) || task_is_running(p))
2254 return 0;
2255 if (count > 0) {
2256 ip = READ_ONCE_NOCHECK(((unsigned long *)sp)[STACK_FRAME_LR_SAVE]);
2257 if (!in_sched_functions(ip))
2258 return ip;
2259 }
2260 } while (count++ < 16);
2261 return 0;
2262 }
2263
2264 unsigned long __get_wchan(struct task_struct *p)
2265 {
2266 unsigned long ret;
2267
2268 if (!try_get_task_stack(p))
2269 return 0;
2270
2271 ret = ___get_wchan(p);
2272
2273 put_task_stack(p);
2274
2275 return ret;
2276 }
2277
2278 static bool empty_user_regs(struct pt_regs *regs, struct task_struct *tsk)
2279 {
2280 unsigned long stack_page;
2281
2282 // A non-empty pt_regs should never have a zero MSR or TRAP value.
2283 if (regs->msr || regs->trap)
2284 return false;
2285
2286 // Check it sits at the very base of the stack
2287 stack_page = (unsigned long)task_stack_page(tsk);
2288 if ((unsigned long)(regs + 1) != stack_page + THREAD_SIZE)
2289 return false;
2290
2291 return true;
2292 }
2293
2294 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
2295
2296 void __no_sanitize_address show_stack(struct task_struct *tsk,
2297 unsigned long *stack,
2298 const char *loglvl)
2299 {
2300 unsigned long sp, ip, lr, newsp;
2301 int count = 0;
2302 int firstframe = 1;
2303 unsigned long ret_addr;
2304 int ftrace_idx = 0;
2305
2306 if (tsk == NULL)
2307 tsk = current;
2308
2309 if (!try_get_task_stack(tsk))
2310 return;
2311
2312 sp = (unsigned long) stack;
2313 if (sp == 0) {
2314 if (tsk == current)
2315 sp = current_stack_frame();
2316 else
2317 sp = tsk->thread.ksp;
2318 }
2319
2320 lr = 0;
2321 printk("%sCall Trace:\n", loglvl);
2322 do {
2323 if (!validate_sp(sp, tsk))
2324 break;
2325
2326 stack = (unsigned long *) sp;
2327 newsp = stack[0];
2328 ip = stack[STACK_FRAME_LR_SAVE];
2329 if (!firstframe || ip != lr) {
2330 printk("%s["REG"] ["REG"] %pS",
2331 loglvl, sp, ip, (void *)ip);
2332 ret_addr = ftrace_graph_ret_addr(current,
2333 &ftrace_idx, ip, stack);
2334 if (ret_addr != ip)
2335 pr_cont(" (%pS)", (void *)ret_addr);
2336 if (firstframe)
2337 pr_cont(" (unreliable)");
2338 pr_cont("\n");
2339 }
2340 firstframe = 0;
2341
2342 /*
2343 * See if this is an exception frame.
2344 * We look for the "regs" marker in the current frame.
2345 *
2346 * STACK_SWITCH_FRAME_SIZE being the smallest frame that
2347 * could hold a pt_regs, if that does not fit then it can't
2348 * have regs.
2349 */
2350 if (validate_sp_size(sp, tsk, STACK_SWITCH_FRAME_SIZE)
2351 && stack[STACK_INT_FRAME_MARKER_LONGS] == STACK_FRAME_REGS_MARKER) {
2352 struct pt_regs *regs = (struct pt_regs *)
2353 (sp + STACK_INT_FRAME_REGS);
2354
2355 lr = regs->link;
2356 printk("%s--- interrupt: %lx at %pS\n",
2357 loglvl, regs->trap, (void *)regs->nip);
2358
2359 // Detect the case of an empty pt_regs at the very base
2360 // of the stack and suppress showing it in full.
2361 if (!empty_user_regs(regs, tsk)) {
2362 __show_regs(regs);
2363 printk("%s--- interrupt: %lx\n", loglvl, regs->trap);
2364 }
2365
2366 firstframe = 1;
2367 }
2368
2369 sp = newsp;
2370 } while (count++ < kstack_depth_to_print);
2371
2372 put_task_stack(tsk);
2373 }
2374
2375 #ifdef CONFIG_PPC64
2376 /* Called with hard IRQs off */
2377 void notrace __ppc64_runlatch_on(void)
2378 {
2379 struct thread_info *ti = current_thread_info();
2380
2381 if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2382 /*
2383 * Least significant bit (RUN) is the only writable bit of
2384 * the CTRL register, so we can avoid mfspr. 2.06 is not the
2385 * earliest ISA where this is the case, but it's convenient.
2386 */
2387 mtspr(SPRN_CTRLT, CTRL_RUNLATCH);
2388 } else {
2389 unsigned long ctrl;
2390
2391 /*
2392 * Some architectures (e.g., Cell) have writable fields other
2393 * than RUN, so do the read-modify-write.
2394 */
2395 ctrl = mfspr(SPRN_CTRLF);
2396 ctrl |= CTRL_RUNLATCH;
2397 mtspr(SPRN_CTRLT, ctrl);
2398 }
2399
2400 ti->local_flags |= _TLF_RUNLATCH;
2401 }
2402
2403 /* Called with hard IRQs off */
2404 void notrace __ppc64_runlatch_off(void)
2405 {
2406 struct thread_info *ti = current_thread_info();
2407
2408 ti->local_flags &= ~_TLF_RUNLATCH;
2409
2410 if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2411 mtspr(SPRN_CTRLT, 0);
2412 } else {
2413 unsigned long ctrl;
2414
2415 ctrl = mfspr(SPRN_CTRLF);
2416 ctrl &= ~CTRL_RUNLATCH;
2417 mtspr(SPRN_CTRLT, ctrl);
2418 }
2419 }
2420 #endif /* CONFIG_PPC64 */
2421
2422 unsigned long arch_align_stack(unsigned long sp)
2423 {
2424 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
2425 sp -= get_random_u32_below(PAGE_SIZE);
2426 return sp & ~0xf;
2427 }
2428
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