1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Performance counter support for POWER10 processors. 4 * 5 * Copyright 2020 Madhavan Srinivasan, IBM Corporation. 6 * Copyright 2020 Athira Rajeev, IBM Corporation. 7 */ 8 9 /* 10 * Power10 event codes. 11 */ 12 EVENT(PM_CYC, 0x600f4); 13 EVENT(PM_DISP_STALL_CYC, 0x100f8); 14 EVENT(PM_EXEC_STALL, 0x30008); 15 EVENT(PM_INST_CMPL, 0x500fa); 16 EVENT(PM_BR_CMPL, 0x4d05e); 17 EVENT(PM_BR_MPRED_CMPL, 0x400f6); 18 EVENT(PM_BR_FIN, 0x2f04a); 19 EVENT(PM_MPRED_BR_FIN, 0x3e098); 20 EVENT(PM_LD_DEMAND_MISS_L1_FIN, 0x400f0); 21 22 /* All L1 D cache load references counted at finish, gated by reject */ 23 EVENT(PM_LD_REF_L1, 0x100fc); 24 /* Load Missed L1 */ 25 EVENT(PM_LD_MISS_L1, 0x3e054); 26 /* Store Missed L1 */ 27 EVENT(PM_ST_MISS_L1, 0x300f0); 28 /* L1 cache data prefetches */ 29 EVENT(PM_LD_PREFETCH_CACHE_LINE_MISS, 0x1002c); 30 /* Demand iCache Miss */ 31 EVENT(PM_L1_ICACHE_MISS, 0x200fc); 32 /* Instruction fetches from L1 */ 33 EVENT(PM_INST_FROM_L1, 0x04080); 34 /* Instruction Demand sectors wriittent into IL1 */ 35 EVENT(PM_INST_FROM_L1MISS, 0x03f00000001c040); 36 /* Instruction prefetch written into IL1 */ 37 EVENT(PM_IC_PREF_REQ, 0x040a0); 38 /* The data cache was reloaded from local core's L3 due to a demand load */ 39 EVENT(PM_DATA_FROM_L3, 0x01340000001c040); 40 /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */ 41 EVENT(PM_DATA_FROM_L3MISS, 0x300fe); 42 /* All successful D-side store dispatches for this thread */ 43 EVENT(PM_L2_ST, 0x010000046080); 44 /* All successful D-side store dispatches for this thread that were L2 Miss */ 45 EVENT(PM_L2_ST_MISS, 0x26880); 46 /* Total HW L3 prefetches(Load+store) */ 47 EVENT(PM_L3_PF_MISS_L3, 0x100000016080); 48 /* Data PTEG reload */ 49 EVENT(PM_DTLB_MISS, 0x300fc); 50 /* ITLB Reloaded */ 51 EVENT(PM_ITLB_MISS, 0x400fc); 52 53 EVENT(PM_CYC_ALT, 0x0001e); 54 EVENT(PM_INST_CMPL_ALT, 0x00002); 55 56 /* 57 * Memory Access Events 58 * 59 * Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0) 60 * To enable capturing of memory profiling, these MMCRA bits 61 * needs to be programmed and corresponding raw event format 62 * encoding. 63 * 64 * MMCRA bits encoding needed are 65 * SM (Sampling Mode) 66 * EM (Eligibility for Random Sampling) 67 * TECE (Threshold Event Counter Event) 68 * TS (Threshold Start Event) 69 * TE (Threshold End Event) 70 * 71 * Corresponding Raw Encoding bits: 72 * sample [EM,SM] 73 * thresh_sel (TECE) 74 * thresh start (TS) 75 * thresh end (TE) 76 */ 77 78 EVENT(MEM_LOADS, 0x35340401e0); 79 EVENT(MEM_STORES, 0x353c0401e0); 80
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