1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Performance counter support for POWER8 processors. 4 * 5 * Copyright 2014 Sukadev Bhattiprolu, IBM Corporation. 6 */ 7 8 /* 9 * Power8 event codes. 10 */ 11 EVENT(PM_CYC, 0x0001e) 12 EVENT(PM_GCT_NOSLOT_CYC, 0x100f8) 13 EVENT(PM_CMPLU_STALL, 0x4000a) 14 EVENT(PM_INST_CMPL, 0x00002) 15 EVENT(PM_BRU_FIN, 0x10068) 16 EVENT(PM_BR_MPRED_CMPL, 0x400f6) 17 18 /* All L1 D cache load references counted at finish, gated by reject */ 19 EVENT(PM_LD_REF_L1, 0x100ee) 20 /* Load Missed L1 */ 21 EVENT(PM_LD_MISS_L1, 0x3e054) 22 /* Store Missed L1 */ 23 EVENT(PM_ST_MISS_L1, 0x300f0) 24 /* L1 cache data prefetches */ 25 EVENT(PM_L1_PREF, 0x0d8b8) 26 /* Instruction fetches from L1 */ 27 EVENT(PM_INST_FROM_L1, 0x04080) 28 /* Demand iCache Miss */ 29 EVENT(PM_L1_ICACHE_MISS, 0x200fd) 30 /* Instruction Demand sectors wriittent into IL1 */ 31 EVENT(PM_L1_DEMAND_WRITE, 0x0408c) 32 /* Instruction prefetch written into IL1 */ 33 EVENT(PM_IC_PREF_WRITE, 0x0408e) 34 /* The data cache was reloaded from local core's L3 due to a demand load */ 35 EVENT(PM_DATA_FROM_L3, 0x4c042) 36 /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */ 37 EVENT(PM_DATA_FROM_L3MISS, 0x300fe) 38 /* All successful D-side store dispatches for this thread */ 39 EVENT(PM_L2_ST, 0x17080) 40 /* All successful D-side store dispatches for this thread that were L2 Miss */ 41 EVENT(PM_L2_ST_MISS, 0x17082) 42 /* Total HW L3 prefetches(Load+store) */ 43 EVENT(PM_L3_PREF_ALL, 0x4e052) 44 /* Data PTEG reload */ 45 EVENT(PM_DTLB_MISS, 0x300fc) 46 /* ITLB Reloaded */ 47 EVENT(PM_ITLB_MISS, 0x400fc) 48 /* Run_Instructions */ 49 EVENT(PM_RUN_INST_CMPL, 0x500fa) 50 /* Alternate event code for PM_RUN_INST_CMPL */ 51 EVENT(PM_RUN_INST_CMPL_ALT, 0x400fa) 52 /* Run_cycles */ 53 EVENT(PM_RUN_CYC, 0x600f4) 54 /* Alternate event code for Run_cycles */ 55 EVENT(PM_RUN_CYC_ALT, 0x200f4) 56 /* Marked store completed */ 57 EVENT(PM_MRK_ST_CMPL, 0x10134) 58 /* Alternate event code for Marked store completed */ 59 EVENT(PM_MRK_ST_CMPL_ALT, 0x301e2) 60 /* Marked two path branch */ 61 EVENT(PM_BR_MRK_2PATH, 0x10138) 62 /* Alternate event code for PM_BR_MRK_2PATH */ 63 EVENT(PM_BR_MRK_2PATH_ALT, 0x40138) 64 /* L3 castouts in Mepf state */ 65 EVENT(PM_L3_CO_MEPF, 0x18082) 66 /* Alternate event code for PM_L3_CO_MEPF */ 67 EVENT(PM_L3_CO_MEPF_ALT, 0x3e05e) 68 /* Data cache was reloaded from a location other than L2 due to a marked load */ 69 EVENT(PM_MRK_DATA_FROM_L2MISS, 0x1d14e) 70 /* Alternate event code for PM_MRK_DATA_FROM_L2MISS */ 71 EVENT(PM_MRK_DATA_FROM_L2MISS_ALT, 0x401e8) 72 /* Alternate event code for PM_CMPLU_STALL */ 73 EVENT(PM_CMPLU_STALL_ALT, 0x1e054) 74 /* Two path branch */ 75 EVENT(PM_BR_2PATH, 0x20036) 76 /* Alternate event code for PM_BR_2PATH */ 77 EVENT(PM_BR_2PATH_ALT, 0x40036) 78 /* # PPC Dispatched */ 79 EVENT(PM_INST_DISP, 0x200f2) 80 /* Alternate event code for PM_INST_DISP */ 81 EVENT(PM_INST_DISP_ALT, 0x300f2) 82 /* Marked filter Match */ 83 EVENT(PM_MRK_FILT_MATCH, 0x2013c) 84 /* Alternate event code for PM_MRK_FILT_MATCH */ 85 EVENT(PM_MRK_FILT_MATCH_ALT, 0x3012e) 86 /* Alternate event code for PM_LD_MISS_L1 */ 87 EVENT(PM_LD_MISS_L1_ALT, 0x400f0) 88 /* 89 * Memory Access Event -- mem_access 90 * Primary PMU event used here is PM_MRK_INST_CMPL, along with 91 * Random Load/Store Facility Sampling (RIS) in Random sampling mode (MMCRA[SM]). 92 */ 93 EVENT(MEM_ACCESS, 0x10401e0) 94
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