1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * MPC5200 General Purpose Timer device driver
4 *
5 * Copyright (c) 2009 Secret Lab Technologies Ltd.
6 * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
7 *
8 * This file is a driver for the General Purpose Timer (gpt) devices
9 * found on the MPC5200 SoC. Each timer has an IO pin which can be used
10 * for GPIO or can be used to raise interrupts. The timer function can
11 * be used independently from the IO pin, or it can be used to control
12 * output signals or measure input signals.
13 *
14 * This driver supports the GPIO and IRQ controller functions of the GPT
15 * device. Timer functions are not yet supported.
16 *
17 * The timer gpt0 can be used as watchdog (wdt). If the wdt mode is used,
18 * this prevents the use of any gpt0 gpt function (i.e. they will fail with
19 * -EBUSY). Thus, the safety wdt function always has precedence over the gpt
20 * function. If the kernel has been compiled with CONFIG_WATCHDOG_NOWAYOUT,
21 * this means that gpt0 is locked in wdt mode until the next reboot - this
22 * may be a requirement in safety applications.
23 *
24 * To use the GPIO function, the following two properties must be added
25 * to the device tree node for the gpt device (typically in the .dts file
26 * for the board):
27 * gpio-controller;
28 * #gpio-cells = < 2 >;
29 * This driver will register the GPIO pin if it finds the gpio-controller
30 * property in the device tree.
31 *
32 * To use the IRQ controller function, the following two properties must
33 * be added to the device tree node for the gpt device:
34 * interrupt-controller;
35 * #interrupt-cells = < 1 >;
36 * The IRQ controller binding only uses one cell to specify the interrupt,
37 * and the IRQ flags are encoded in the cell. A cell is not used to encode
38 * the IRQ number because the GPT only has a single IRQ source. For flags,
39 * a value of '1' means rising edge sensitive and '2' means falling edge.
40 *
41 * The GPIO and the IRQ controller functions can be used at the same time,
42 * but in this use case the IO line will only work as an input. Trying to
43 * use it as a GPIO output will not work.
44 *
45 * When using the GPIO line as an output, it can either be driven as normal
46 * IO, or it can be an Open Collector (OC) output. At the moment it is the
47 * responsibility of either the bootloader or the platform setup code to set
48 * the output mode. This driver does not change the output mode setting.
49 */
50
51 #include <linux/gpio/driver.h>
52 #include <linux/irq.h>
53 #include <linux/interrupt.h>
54 #include <linux/io.h>
55 #include <linux/list.h>
56 #include <linux/mutex.h>
57 #include <linux/of.h>
58 #include <linux/of_address.h>
59 #include <linux/of_irq.h>
60 #include <linux/platform_device.h>
61 #include <linux/kernel.h>
62 #include <linux/property.h>
63 #include <linux/slab.h>
64 #include <linux/fs.h>
65 #include <linux/watchdog.h>
66 #include <linux/miscdevice.h>
67 #include <linux/uaccess.h>
68 #include <linux/module.h>
69 #include <asm/div64.h>
70 #include <asm/mpc52xx.h>
71
72 MODULE_DESCRIPTION("Freescale MPC52xx gpt driver");
73 MODULE_AUTHOR("Sascha Hauer, Grant Likely, Albrecht Dreß");
74 MODULE_LICENSE("GPL");
75
76 /**
77 * struct mpc52xx_gpt - Private data structure for MPC52xx GPT driver
78 * @dev: pointer to device structure
79 * @regs: virtual address of GPT registers
80 * @lock: spinlock to coordinate between different functions.
81 * @gc: gpio_chip instance structure; used when GPIO is enabled
82 * @irqhost: Pointer to irq_domain instance; used when IRQ mode is supported
83 * @wdt_mode: only relevant for gpt0: bit 0 (MPC52xx_GPT_CAN_WDT) indicates
84 * if the gpt may be used as wdt, bit 1 (MPC52xx_GPT_IS_WDT) indicates
85 * if the timer is actively used as wdt which blocks gpt functions
86 */
87 struct mpc52xx_gpt_priv {
88 struct list_head list; /* List of all GPT devices */
89 struct device *dev;
90 struct mpc52xx_gpt __iomem *regs;
91 raw_spinlock_t lock;
92 struct irq_domain *irqhost;
93 u32 ipb_freq;
94 u8 wdt_mode;
95
96 #if defined(CONFIG_GPIOLIB)
97 struct gpio_chip gc;
98 #endif
99 };
100
101 LIST_HEAD(mpc52xx_gpt_list);
102 DEFINE_MUTEX(mpc52xx_gpt_list_mutex);
103
104 #define MPC52xx_GPT_MODE_MS_MASK (0x07)
105 #define MPC52xx_GPT_MODE_MS_IC (0x01)
106 #define MPC52xx_GPT_MODE_MS_OC (0x02)
107 #define MPC52xx_GPT_MODE_MS_PWM (0x03)
108 #define MPC52xx_GPT_MODE_MS_GPIO (0x04)
109
110 #define MPC52xx_GPT_MODE_GPIO_MASK (0x30)
111 #define MPC52xx_GPT_MODE_GPIO_OUT_LOW (0x20)
112 #define MPC52xx_GPT_MODE_GPIO_OUT_HIGH (0x30)
113
114 #define MPC52xx_GPT_MODE_COUNTER_ENABLE (0x1000)
115 #define MPC52xx_GPT_MODE_CONTINUOUS (0x0400)
116 #define MPC52xx_GPT_MODE_OPEN_DRAIN (0x0200)
117 #define MPC52xx_GPT_MODE_IRQ_EN (0x0100)
118 #define MPC52xx_GPT_MODE_WDT_EN (0x8000)
119
120 #define MPC52xx_GPT_MODE_ICT_MASK (0x030000)
121 #define MPC52xx_GPT_MODE_ICT_RISING (0x010000)
122 #define MPC52xx_GPT_MODE_ICT_FALLING (0x020000)
123 #define MPC52xx_GPT_MODE_ICT_TOGGLE (0x030000)
124
125 #define MPC52xx_GPT_MODE_WDT_PING (0xa5)
126
127 #define MPC52xx_GPT_STATUS_IRQMASK (0x000f)
128
129 #define MPC52xx_GPT_CAN_WDT (1 << 0)
130 #define MPC52xx_GPT_IS_WDT (1 << 1)
131
132
133 /* ---------------------------------------------------------------------
134 * Cascaded interrupt controller hooks
135 */
136
137 static void mpc52xx_gpt_irq_unmask(struct irq_data *d)
138 {
139 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
140 unsigned long flags;
141
142 raw_spin_lock_irqsave(&gpt->lock, flags);
143 setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
144 raw_spin_unlock_irqrestore(&gpt->lock, flags);
145 }
146
147 static void mpc52xx_gpt_irq_mask(struct irq_data *d)
148 {
149 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
150 unsigned long flags;
151
152 raw_spin_lock_irqsave(&gpt->lock, flags);
153 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
154 raw_spin_unlock_irqrestore(&gpt->lock, flags);
155 }
156
157 static void mpc52xx_gpt_irq_ack(struct irq_data *d)
158 {
159 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
160
161 out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK);
162 }
163
164 static int mpc52xx_gpt_irq_set_type(struct irq_data *d, unsigned int flow_type)
165 {
166 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
167 unsigned long flags;
168 u32 reg;
169
170 dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, d->irq, flow_type);
171
172 raw_spin_lock_irqsave(&gpt->lock, flags);
173 reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK;
174 if (flow_type & IRQF_TRIGGER_RISING)
175 reg |= MPC52xx_GPT_MODE_ICT_RISING;
176 if (flow_type & IRQF_TRIGGER_FALLING)
177 reg |= MPC52xx_GPT_MODE_ICT_FALLING;
178 out_be32(&gpt->regs->mode, reg);
179 raw_spin_unlock_irqrestore(&gpt->lock, flags);
180
181 return 0;
182 }
183
184 static struct irq_chip mpc52xx_gpt_irq_chip = {
185 .name = "MPC52xx GPT",
186 .irq_unmask = mpc52xx_gpt_irq_unmask,
187 .irq_mask = mpc52xx_gpt_irq_mask,
188 .irq_ack = mpc52xx_gpt_irq_ack,
189 .irq_set_type = mpc52xx_gpt_irq_set_type,
190 };
191
192 static void mpc52xx_gpt_irq_cascade(struct irq_desc *desc)
193 {
194 struct mpc52xx_gpt_priv *gpt = irq_desc_get_handler_data(desc);
195 u32 status;
196
197 status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK;
198 if (status)
199 generic_handle_domain_irq(gpt->irqhost, 0);
200 }
201
202 static int mpc52xx_gpt_irq_map(struct irq_domain *h, unsigned int virq,
203 irq_hw_number_t hw)
204 {
205 struct mpc52xx_gpt_priv *gpt = h->host_data;
206
207 dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq);
208 irq_set_chip_data(virq, gpt);
209 irq_set_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq);
210
211 return 0;
212 }
213
214 static int mpc52xx_gpt_irq_xlate(struct irq_domain *h, struct device_node *ct,
215 const u32 *intspec, unsigned int intsize,
216 irq_hw_number_t *out_hwirq,
217 unsigned int *out_flags)
218 {
219 struct mpc52xx_gpt_priv *gpt = h->host_data;
220
221 dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]);
222
223 if ((intsize < 1) || (intspec[0] > 3)) {
224 dev_err(gpt->dev, "bad irq specifier in %pOF\n", ct);
225 return -EINVAL;
226 }
227
228 *out_hwirq = 0; /* The GPT only has 1 IRQ line */
229 *out_flags = intspec[0];
230
231 return 0;
232 }
233
234 static const struct irq_domain_ops mpc52xx_gpt_irq_ops = {
235 .map = mpc52xx_gpt_irq_map,
236 .xlate = mpc52xx_gpt_irq_xlate,
237 };
238
239 static void
240 mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
241 {
242 int cascade_virq;
243 unsigned long flags;
244 u32 mode;
245
246 cascade_virq = irq_of_parse_and_map(node, 0);
247 if (!cascade_virq)
248 return;
249
250 gpt->irqhost = irq_domain_add_linear(node, 1, &mpc52xx_gpt_irq_ops, gpt);
251 if (!gpt->irqhost) {
252 dev_err(gpt->dev, "irq_domain_add_linear() failed\n");
253 return;
254 }
255
256 irq_set_handler_data(cascade_virq, gpt);
257 irq_set_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade);
258
259 /* If the GPT is currently disabled, then change it to be in Input
260 * Capture mode. If the mode is non-zero, then the pin could be
261 * already in use for something. */
262 raw_spin_lock_irqsave(&gpt->lock, flags);
263 mode = in_be32(&gpt->regs->mode);
264 if ((mode & MPC52xx_GPT_MODE_MS_MASK) == 0)
265 out_be32(&gpt->regs->mode, mode | MPC52xx_GPT_MODE_MS_IC);
266 raw_spin_unlock_irqrestore(&gpt->lock, flags);
267
268 dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq);
269 }
270
271
272 /* ---------------------------------------------------------------------
273 * GPIOLIB hooks
274 */
275 #if defined(CONFIG_GPIOLIB)
276 static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio)
277 {
278 struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);
279
280 return (in_be32(&gpt->regs->status) >> 8) & 1;
281 }
282
283 static void
284 mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int v)
285 {
286 struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);
287 unsigned long flags;
288 u32 r;
289
290 dev_dbg(gpt->dev, "%s: gpio:%d v:%d\n", __func__, gpio, v);
291 r = v ? MPC52xx_GPT_MODE_GPIO_OUT_HIGH : MPC52xx_GPT_MODE_GPIO_OUT_LOW;
292
293 raw_spin_lock_irqsave(&gpt->lock, flags);
294 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK, r);
295 raw_spin_unlock_irqrestore(&gpt->lock, flags);
296 }
297
298 static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
299 {
300 struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);
301 unsigned long flags;
302
303 dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio);
304
305 raw_spin_lock_irqsave(&gpt->lock, flags);
306 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK);
307 raw_spin_unlock_irqrestore(&gpt->lock, flags);
308
309 return 0;
310 }
311
312 static int
313 mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
314 {
315 mpc52xx_gpt_gpio_set(gc, gpio, val);
316 return 0;
317 }
318
319 static void mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt)
320 {
321 int rc;
322
323 /* Only setup GPIO if the device claims the GPT is a GPIO controller */
324 if (!device_property_present(gpt->dev, "gpio-controller"))
325 return;
326
327 gpt->gc.label = kasprintf(GFP_KERNEL, "%pfw", dev_fwnode(gpt->dev));
328 if (!gpt->gc.label) {
329 dev_err(gpt->dev, "out of memory\n");
330 return;
331 }
332
333 gpt->gc.ngpio = 1;
334 gpt->gc.direction_input = mpc52xx_gpt_gpio_dir_in;
335 gpt->gc.direction_output = mpc52xx_gpt_gpio_dir_out;
336 gpt->gc.get = mpc52xx_gpt_gpio_get;
337 gpt->gc.set = mpc52xx_gpt_gpio_set;
338 gpt->gc.base = -1;
339 gpt->gc.parent = gpt->dev;
340
341 /* Setup external pin in GPIO mode */
342 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK,
343 MPC52xx_GPT_MODE_MS_GPIO);
344
345 rc = gpiochip_add_data(&gpt->gc, gpt);
346 if (rc)
347 dev_err(gpt->dev, "gpiochip_add_data() failed; rc=%i\n", rc);
348
349 dev_dbg(gpt->dev, "%s() complete.\n", __func__);
350 }
351 #else /* defined(CONFIG_GPIOLIB) */
352 static void mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt) { }
353 #endif /* defined(CONFIG_GPIOLIB) */
354
355 /***********************************************************************
356 * Timer API
357 */
358
359 /**
360 * mpc52xx_gpt_from_irq - Return the GPT device associated with an IRQ number
361 * @irq: irq of timer.
362 */
363 struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq)
364 {
365 struct mpc52xx_gpt_priv *gpt;
366 struct list_head *pos;
367
368 /* Iterate over the list of timers looking for a matching device */
369 mutex_lock(&mpc52xx_gpt_list_mutex);
370 list_for_each(pos, &mpc52xx_gpt_list) {
371 gpt = container_of(pos, struct mpc52xx_gpt_priv, list);
372 if (gpt->irqhost && irq == irq_linear_revmap(gpt->irqhost, 0)) {
373 mutex_unlock(&mpc52xx_gpt_list_mutex);
374 return gpt;
375 }
376 }
377 mutex_unlock(&mpc52xx_gpt_list_mutex);
378
379 return NULL;
380 }
381 EXPORT_SYMBOL(mpc52xx_gpt_from_irq);
382
383 static int mpc52xx_gpt_do_start(struct mpc52xx_gpt_priv *gpt, u64 period,
384 int continuous, int as_wdt)
385 {
386 u32 clear, set;
387 u64 clocks;
388 u32 prescale;
389 unsigned long flags;
390
391 clear = MPC52xx_GPT_MODE_MS_MASK | MPC52xx_GPT_MODE_CONTINUOUS;
392 set = MPC52xx_GPT_MODE_MS_GPIO | MPC52xx_GPT_MODE_COUNTER_ENABLE;
393 if (as_wdt) {
394 clear |= MPC52xx_GPT_MODE_IRQ_EN;
395 set |= MPC52xx_GPT_MODE_WDT_EN;
396 } else if (continuous)
397 set |= MPC52xx_GPT_MODE_CONTINUOUS;
398
399 /* Determine the number of clocks in the requested period. 64 bit
400 * arithmetic is done here to preserve the precision until the value
401 * is scaled back down into the u32 range. Period is in 'ns', bus
402 * frequency is in Hz. */
403 clocks = period * (u64)gpt->ipb_freq;
404 do_div(clocks, 1000000000); /* Scale it down to ns range */
405
406 /* This device cannot handle a clock count greater than 32 bits */
407 if (clocks > 0xffffffff)
408 return -EINVAL;
409
410 /* Calculate the prescaler and count values from the clocks value.
411 * 'clocks' is the number of clock ticks in the period. The timer
412 * has 16 bit precision and a 16 bit prescaler. Prescaler is
413 * calculated by integer dividing the clocks by 0x10000 (shifting
414 * down 16 bits) to obtain the smallest possible divisor for clocks
415 * to get a 16 bit count value.
416 *
417 * Note: the prescale register is '1' based, not '' based. ie. a
418 * value of '1' means divide the clock by one. 0xffff divides the
419 * clock by 0xffff. '0x0000' does not divide by zero, but wraps
420 * around and divides by 0x10000. That is why prescale must be
421 * a u32 variable, not a u16, for this calculation. */
422 prescale = (clocks >> 16) + 1;
423 do_div(clocks, prescale);
424 if (clocks > 0xffff) {
425 pr_err("calculation error; prescale:%x clocks:%llx\n",
426 prescale, clocks);
427 return -EINVAL;
428 }
429
430 /* Set and enable the timer, reject an attempt to use a wdt as gpt */
431 raw_spin_lock_irqsave(&gpt->lock, flags);
432 if (as_wdt)
433 gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
434 else if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
435 raw_spin_unlock_irqrestore(&gpt->lock, flags);
436 return -EBUSY;
437 }
438 out_be32(&gpt->regs->count, prescale << 16 | clocks);
439 clrsetbits_be32(&gpt->regs->mode, clear, set);
440 raw_spin_unlock_irqrestore(&gpt->lock, flags);
441
442 return 0;
443 }
444
445 /**
446 * mpc52xx_gpt_start_timer - Set and enable the GPT timer
447 * @gpt: Pointer to gpt private data structure
448 * @period: period of timer in ns; max. ~130s @ 33MHz IPB clock
449 * @continuous: set to 1 to make timer continuous free running
450 *
451 * An interrupt will be generated every time the timer fires
452 */
453 int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
454 int continuous)
455 {
456 return mpc52xx_gpt_do_start(gpt, period, continuous, 0);
457 }
458 EXPORT_SYMBOL(mpc52xx_gpt_start_timer);
459
460 /**
461 * mpc52xx_gpt_stop_timer - Stop a gpt
462 * @gpt: Pointer to gpt private data structure
463 *
464 * Returns an error if attempting to stop a wdt
465 */
466 int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt)
467 {
468 unsigned long flags;
469
470 /* reject the operation if the timer is used as watchdog (gpt 0 only) */
471 raw_spin_lock_irqsave(&gpt->lock, flags);
472 if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
473 raw_spin_unlock_irqrestore(&gpt->lock, flags);
474 return -EBUSY;
475 }
476
477 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE);
478 raw_spin_unlock_irqrestore(&gpt->lock, flags);
479 return 0;
480 }
481 EXPORT_SYMBOL(mpc52xx_gpt_stop_timer);
482
483 /**
484 * mpc52xx_gpt_timer_period - Read the timer period
485 * @gpt: Pointer to gpt private data structure
486 *
487 * Returns the timer period in ns
488 */
489 u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt)
490 {
491 u64 period;
492 u64 prescale;
493 unsigned long flags;
494
495 raw_spin_lock_irqsave(&gpt->lock, flags);
496 period = in_be32(&gpt->regs->count);
497 raw_spin_unlock_irqrestore(&gpt->lock, flags);
498
499 prescale = period >> 16;
500 period &= 0xffff;
501 if (prescale == 0)
502 prescale = 0x10000;
503 period = period * prescale * 1000000000ULL;
504 do_div(period, gpt->ipb_freq);
505 return period;
506 }
507 EXPORT_SYMBOL(mpc52xx_gpt_timer_period);
508
509 #if defined(CONFIG_MPC5200_WDT)
510 /***********************************************************************
511 * Watchdog API for gpt0
512 */
513
514 #define WDT_IDENTITY "mpc52xx watchdog on GPT0"
515
516 /* wdt_is_active stores whether or not the /dev/watchdog device is opened */
517 static unsigned long wdt_is_active;
518
519 /* wdt-capable gpt */
520 static struct mpc52xx_gpt_priv *mpc52xx_gpt_wdt;
521
522 /* low-level wdt functions */
523 static inline void mpc52xx_gpt_wdt_ping(struct mpc52xx_gpt_priv *gpt_wdt)
524 {
525 unsigned long flags;
526
527 raw_spin_lock_irqsave(&gpt_wdt->lock, flags);
528 out_8((u8 *) &gpt_wdt->regs->mode, MPC52xx_GPT_MODE_WDT_PING);
529 raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags);
530 }
531
532 /* wdt misc device api */
533 static ssize_t mpc52xx_wdt_write(struct file *file, const char __user *data,
534 size_t len, loff_t *ppos)
535 {
536 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
537 mpc52xx_gpt_wdt_ping(gpt_wdt);
538 return 0;
539 }
540
541 static const struct watchdog_info mpc5200_wdt_info = {
542 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
543 .identity = WDT_IDENTITY,
544 };
545
546 static long mpc52xx_wdt_ioctl(struct file *file, unsigned int cmd,
547 unsigned long arg)
548 {
549 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
550 int __user *data = (int __user *)arg;
551 int timeout;
552 u64 real_timeout;
553 int ret = 0;
554
555 switch (cmd) {
556 case WDIOC_GETSUPPORT:
557 ret = copy_to_user(data, &mpc5200_wdt_info,
558 sizeof(mpc5200_wdt_info));
559 if (ret)
560 ret = -EFAULT;
561 break;
562
563 case WDIOC_GETSTATUS:
564 case WDIOC_GETBOOTSTATUS:
565 ret = put_user(0, data);
566 break;
567
568 case WDIOC_KEEPALIVE:
569 mpc52xx_gpt_wdt_ping(gpt_wdt);
570 break;
571
572 case WDIOC_SETTIMEOUT:
573 ret = get_user(timeout, data);
574 if (ret)
575 break;
576 real_timeout = (u64) timeout * 1000000000ULL;
577 ret = mpc52xx_gpt_do_start(gpt_wdt, real_timeout, 0, 1);
578 if (ret)
579 break;
580 /* fall through and return the timeout */
581 fallthrough;
582
583 case WDIOC_GETTIMEOUT:
584 /* we need to round here as to avoid e.g. the following
585 * situation:
586 * - timeout requested is 1 second;
587 * - real timeout @33MHz is 999997090ns
588 * - the int divide by 10^9 will return 0.
589 */
590 real_timeout =
591 mpc52xx_gpt_timer_period(gpt_wdt) + 500000000ULL;
592 do_div(real_timeout, 1000000000ULL);
593 timeout = (int) real_timeout;
594 ret = put_user(timeout, data);
595 break;
596
597 default:
598 ret = -ENOTTY;
599 }
600 return ret;
601 }
602
603 static int mpc52xx_wdt_open(struct inode *inode, struct file *file)
604 {
605 int ret;
606
607 /* sanity check */
608 if (!mpc52xx_gpt_wdt)
609 return -ENODEV;
610
611 /* /dev/watchdog can only be opened once */
612 if (test_and_set_bit(0, &wdt_is_active))
613 return -EBUSY;
614
615 /* Set and activate the watchdog with 30 seconds timeout */
616 ret = mpc52xx_gpt_do_start(mpc52xx_gpt_wdt, 30ULL * 1000000000ULL,
617 0, 1);
618 if (ret) {
619 clear_bit(0, &wdt_is_active);
620 return ret;
621 }
622
623 file->private_data = mpc52xx_gpt_wdt;
624 return stream_open(inode, file);
625 }
626
627 static int mpc52xx_wdt_release(struct inode *inode, struct file *file)
628 {
629 /* note: releasing the wdt in NOWAYOUT-mode does not stop it */
630 #if !defined(CONFIG_WATCHDOG_NOWAYOUT)
631 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
632 unsigned long flags;
633
634 raw_spin_lock_irqsave(&gpt_wdt->lock, flags);
635 clrbits32(&gpt_wdt->regs->mode,
636 MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN);
637 gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT;
638 raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags);
639 #endif
640 clear_bit(0, &wdt_is_active);
641 return 0;
642 }
643
644
645 static const struct file_operations mpc52xx_wdt_fops = {
646 .owner = THIS_MODULE,
647 .llseek = no_llseek,
648 .write = mpc52xx_wdt_write,
649 .unlocked_ioctl = mpc52xx_wdt_ioctl,
650 .compat_ioctl = compat_ptr_ioctl,
651 .open = mpc52xx_wdt_open,
652 .release = mpc52xx_wdt_release,
653 };
654
655 static struct miscdevice mpc52xx_wdt_miscdev = {
656 .minor = WATCHDOG_MINOR,
657 .name = "watchdog",
658 .fops = &mpc52xx_wdt_fops,
659 };
660
661 static int mpc52xx_gpt_wdt_init(void)
662 {
663 int err;
664
665 /* try to register the watchdog misc device */
666 err = misc_register(&mpc52xx_wdt_miscdev);
667 if (err)
668 pr_err("%s: cannot register watchdog device\n", WDT_IDENTITY);
669 else
670 pr_info("%s: watchdog device registered\n", WDT_IDENTITY);
671 return err;
672 }
673
674 static int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
675 const u32 *period)
676 {
677 u64 real_timeout;
678
679 /* remember the gpt for the wdt operation */
680 mpc52xx_gpt_wdt = gpt;
681
682 /* configure the wdt if the device tree contained a timeout */
683 if (!period || *period == 0)
684 return 0;
685
686 real_timeout = (u64) *period * 1000000000ULL;
687 if (mpc52xx_gpt_do_start(gpt, real_timeout, 0, 1))
688 dev_warn(gpt->dev, "starting as wdt failed\n");
689 else
690 dev_info(gpt->dev, "watchdog set to %us timeout\n", *period);
691 return 0;
692 }
693
694 #else
695
696 static int mpc52xx_gpt_wdt_init(void)
697 {
698 return 0;
699 }
700
701 static inline int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
702 const u32 *period)
703 {
704 return 0;
705 }
706
707 #endif /* CONFIG_MPC5200_WDT */
708
709 /* ---------------------------------------------------------------------
710 * of_platform bus binding code
711 */
712 static int mpc52xx_gpt_probe(struct platform_device *ofdev)
713 {
714 struct mpc52xx_gpt_priv *gpt;
715
716 gpt = devm_kzalloc(&ofdev->dev, sizeof *gpt, GFP_KERNEL);
717 if (!gpt)
718 return -ENOMEM;
719
720 raw_spin_lock_init(&gpt->lock);
721 gpt->dev = &ofdev->dev;
722 gpt->ipb_freq = mpc5xxx_get_bus_frequency(&ofdev->dev);
723 gpt->regs = of_iomap(ofdev->dev.of_node, 0);
724 if (!gpt->regs)
725 return -ENOMEM;
726
727 dev_set_drvdata(&ofdev->dev, gpt);
728
729 mpc52xx_gpt_gpio_setup(gpt);
730 mpc52xx_gpt_irq_setup(gpt, ofdev->dev.of_node);
731
732 mutex_lock(&mpc52xx_gpt_list_mutex);
733 list_add(&gpt->list, &mpc52xx_gpt_list);
734 mutex_unlock(&mpc52xx_gpt_list_mutex);
735
736 /* check if this device could be a watchdog */
737 if (of_property_read_bool(ofdev->dev.of_node, "fsl,has-wdt") ||
738 of_property_read_bool(ofdev->dev.of_node, "has-wdt")) {
739 const u32 *on_boot_wdt;
740
741 gpt->wdt_mode = MPC52xx_GPT_CAN_WDT;
742 on_boot_wdt = of_get_property(ofdev->dev.of_node,
743 "fsl,wdt-on-boot", NULL);
744 if (on_boot_wdt) {
745 dev_info(gpt->dev, "used as watchdog\n");
746 gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
747 } else
748 dev_info(gpt->dev, "can function as watchdog\n");
749 mpc52xx_gpt_wdt_setup(gpt, on_boot_wdt);
750 }
751
752 return 0;
753 }
754
755 static const struct of_device_id mpc52xx_gpt_match[] = {
756 { .compatible = "fsl,mpc5200-gpt", },
757
758 /* Depreciated compatible values; don't use for new dts files */
759 { .compatible = "fsl,mpc5200-gpt-gpio", },
760 { .compatible = "mpc5200-gpt", },
761 {}
762 };
763
764 static struct platform_driver mpc52xx_gpt_driver = {
765 .driver = {
766 .name = "mpc52xx-gpt",
767 .suppress_bind_attrs = true,
768 .of_match_table = mpc52xx_gpt_match,
769 },
770 .probe = mpc52xx_gpt_probe,
771 };
772
773 static int __init mpc52xx_gpt_init(void)
774 {
775 return platform_driver_register(&mpc52xx_gpt_driver);
776 }
777
778 /* Make sure GPIOs and IRQs get set up before anyone tries to use them */
779 subsys_initcall(mpc52xx_gpt_init);
780 device_initcall(mpc52xx_gpt_wdt_init);
781
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