1 /*
2 *
3 * Programmable Interrupt Controller functions for the Freescale MPC52xx.
4 *
5 * Copyright (C) 2008 Secret Lab Technologies Ltd.
6 * Copyright (C) 2006 bplan GmbH
7 * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
8 * Copyright (C) 2003 Montavista Software, Inc
9 *
10 * Based on the code from the 2.4 kernel by
11 * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 *
17 */
18
19 /*
20 * This is the device driver for the MPC5200 interrupt controller.
21 *
22 * hardware overview
23 * -----------------
24 * The MPC5200 interrupt controller groups the all interrupt sources into
25 * three groups called 'critical', 'main', and 'peripheral'. The critical
26 * group has 3 irqs, External IRQ0, slice timer 0 irq, and wake from deep
27 * sleep. Main group include the other 3 external IRQs, slice timer 1, RTC,
28 * gpios, and the general purpose timers. Peripheral group contains the
29 * remaining irq sources from all of the on-chip peripherals (PSCs, Ethernet,
30 * USB, DMA, etc).
31 *
32 * virqs
33 * -----
34 * The Linux IRQ subsystem requires that each irq source be assigned a
35 * system wide unique IRQ number starting at 1 (0 means no irq). Since
36 * systems can have multiple interrupt controllers, the virtual IRQ (virq)
37 * infrastructure lets each interrupt controller to define a local set
38 * of IRQ numbers and the virq infrastructure maps those numbers into
39 * a unique range of the global IRQ# space.
40 *
41 * To define a range of virq numbers for this controller, this driver first
42 * assigns a number to each of the irq groups (called the level 1 or L1
43 * value). Within each group individual irq sources are also assigned a
44 * number, as defined by the MPC5200 user guide, and refers to it as the
45 * level 2 or L2 value. The virq number is determined by shifting up the
46 * L1 value by MPC52xx_IRQ_L1_OFFSET and ORing it with the L2 value.
47 *
48 * For example, the TMR0 interrupt is irq 9 in the main group. The
49 * virq for TMR0 is calculated by ((1 << MPC52xx_IRQ_L1_OFFSET) | 9).
50 *
51 * The observant reader will also notice that this driver defines a 4th
52 * interrupt group called 'bestcomm'. The bestcomm group isn't physically
53 * part of the MPC5200 interrupt controller, but it is used here to assign
54 * a separate virq number for each bestcomm task (since any of the 16
55 * bestcomm tasks can cause the bestcomm interrupt to be raised). When a
56 * bestcomm interrupt occurs (peripheral group, irq 0) this driver determines
57 * which task needs servicing and returns the irq number for that task. This
58 * allows drivers which use bestcomm to define their own interrupt handlers.
59 *
60 * irq_chip structures
61 * -------------------
62 * For actually manipulating IRQs (masking, enabling, clearing, etc) this
63 * driver defines four separate 'irq_chip' structures, one for the main
64 * group, one for the peripherals group, one for the bestcomm group and one
65 * for external interrupts. The irq_chip structures provide the hooks needed
66 * to manipulate each IRQ source, and since each group is has a separate set
67 * of registers for controlling the irq, it makes sense to divide up the
68 * hooks along those lines.
69 *
70 * You'll notice that there is not an irq_chip for the critical group and
71 * you'll also notice that there is an irq_chip defined for external
72 * interrupts even though there is no external interrupt group. The reason
73 * for this is that the four external interrupts are all managed with the same
74 * register even though one of the external IRQs is in the critical group and
75 * the other three are in the main group. For this reason it makes sense for
76 * the 4 external irqs to be managed using a separate set of hooks. The
77 * reason there is no crit irq_chip is that of the 3 irqs in the critical
78 * group, only external interrupt is actually support at this time by this
79 * driver and since external interrupt is the only one used, it can just
80 * be directed to make use of the external irq irq_chip.
81 *
82 * device tree bindings
83 * --------------------
84 * The device tree bindings for this controller reflect the two level
85 * organization of irqs in the device. #interrupt-cells = <3> where the
86 * first cell is the group number [0..3], the second cell is the irq
87 * number in the group, and the third cell is the sense type (level/edge).
88 * For reference, the following is a list of the interrupt property values
89 * associated with external interrupt sources on the MPC5200 (just because
90 * it is non-obvious to determine what the interrupts property should be
91 * when reading the mpc5200 manual and it is a frequently asked question).
92 *
93 * External interrupts:
94 * <0 0 n> external irq0, n is sense (n=0: level high,
95 * <1 1 n> external irq1, n is sense n=1: edge rising,
96 * <1 2 n> external irq2, n is sense n=2: edge falling,
97 * <1 3 n> external irq3, n is sense n=3: level low)
98 */
99 #undef DEBUG
100
101 #include <linux/interrupt.h>
102 #include <linux/irq.h>
103 #include <linux/of.h>
104 #include <linux/of_address.h>
105 #include <linux/of_irq.h>
106 #include <asm/io.h>
107 #include <asm/mpc52xx.h>
108
109 /* HW IRQ mapping */
110 #define MPC52xx_IRQ_L1_CRIT (0)
111 #define MPC52xx_IRQ_L1_MAIN (1)
112 #define MPC52xx_IRQ_L1_PERP (2)
113 #define MPC52xx_IRQ_L1_SDMA (3)
114
115 #define MPC52xx_IRQ_L1_OFFSET (6)
116 #define MPC52xx_IRQ_L1_MASK (0x00c0)
117 #define MPC52xx_IRQ_L2_MASK (0x003f)
118
119 #define MPC52xx_IRQ_HIGHTESTHWIRQ (0xd0)
120
121
122 /* MPC5200 device tree match tables */
123 static const struct of_device_id mpc52xx_pic_ids[] __initconst = {
124 { .compatible = "fsl,mpc5200-pic", },
125 { .compatible = "mpc5200-pic", },
126 {}
127 };
128 static const struct of_device_id mpc52xx_sdma_ids[] __initconst = {
129 { .compatible = "fsl,mpc5200-bestcomm", },
130 { .compatible = "mpc5200-bestcomm", },
131 {}
132 };
133
134 static struct mpc52xx_intr __iomem *intr;
135 static struct mpc52xx_sdma __iomem *sdma;
136 static struct irq_domain *mpc52xx_irqhost = NULL;
137
138 static unsigned char mpc52xx_map_senses[4] = {
139 IRQ_TYPE_LEVEL_HIGH,
140 IRQ_TYPE_EDGE_RISING,
141 IRQ_TYPE_EDGE_FALLING,
142 IRQ_TYPE_LEVEL_LOW,
143 };
144
145 /* Utility functions */
146 static inline void io_be_setbit(u32 __iomem *addr, int bitno)
147 {
148 out_be32(addr, in_be32(addr) | (1 << bitno));
149 }
150
151 static inline void io_be_clrbit(u32 __iomem *addr, int bitno)
152 {
153 out_be32(addr, in_be32(addr) & ~(1 << bitno));
154 }
155
156 /*
157 * IRQ[0-3] interrupt irq_chip
158 */
159 static void mpc52xx_extirq_mask(struct irq_data *d)
160 {
161 int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
162 io_be_clrbit(&intr->ctrl, 11 - l2irq);
163 }
164
165 static void mpc52xx_extirq_unmask(struct irq_data *d)
166 {
167 int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
168 io_be_setbit(&intr->ctrl, 11 - l2irq);
169 }
170
171 static void mpc52xx_extirq_ack(struct irq_data *d)
172 {
173 int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
174 io_be_setbit(&intr->ctrl, 27-l2irq);
175 }
176
177 static int mpc52xx_extirq_set_type(struct irq_data *d, unsigned int flow_type)
178 {
179 u32 ctrl_reg, type;
180 int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
181 void *handler = handle_level_irq;
182
183 pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__,
184 (int) irqd_to_hwirq(d), l2irq, flow_type);
185
186 switch (flow_type) {
187 case IRQF_TRIGGER_HIGH: type = 0; break;
188 case IRQF_TRIGGER_RISING: type = 1; handler = handle_edge_irq; break;
189 case IRQF_TRIGGER_FALLING: type = 2; handler = handle_edge_irq; break;
190 case IRQF_TRIGGER_LOW: type = 3; break;
191 default:
192 type = 0;
193 }
194
195 ctrl_reg = in_be32(&intr->ctrl);
196 ctrl_reg &= ~(0x3 << (22 - (l2irq * 2)));
197 ctrl_reg |= (type << (22 - (l2irq * 2)));
198 out_be32(&intr->ctrl, ctrl_reg);
199
200 irq_set_handler_locked(d, handler);
201
202 return 0;
203 }
204
205 static struct irq_chip mpc52xx_extirq_irqchip = {
206 .name = "MPC52xx External",
207 .irq_mask = mpc52xx_extirq_mask,
208 .irq_unmask = mpc52xx_extirq_unmask,
209 .irq_ack = mpc52xx_extirq_ack,
210 .irq_set_type = mpc52xx_extirq_set_type,
211 };
212
213 /*
214 * Main interrupt irq_chip
215 */
216 static int mpc52xx_null_set_type(struct irq_data *d, unsigned int flow_type)
217 {
218 return 0; /* Do nothing so that the sense mask will get updated */
219 }
220
221 static void mpc52xx_main_mask(struct irq_data *d)
222 {
223 int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
224 io_be_setbit(&intr->main_mask, 16 - l2irq);
225 }
226
227 static void mpc52xx_main_unmask(struct irq_data *d)
228 {
229 int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
230 io_be_clrbit(&intr->main_mask, 16 - l2irq);
231 }
232
233 static struct irq_chip mpc52xx_main_irqchip = {
234 .name = "MPC52xx Main",
235 .irq_mask = mpc52xx_main_mask,
236 .irq_mask_ack = mpc52xx_main_mask,
237 .irq_unmask = mpc52xx_main_unmask,
238 .irq_set_type = mpc52xx_null_set_type,
239 };
240
241 /*
242 * Peripherals interrupt irq_chip
243 */
244 static void mpc52xx_periph_mask(struct irq_data *d)
245 {
246 int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
247 io_be_setbit(&intr->per_mask, 31 - l2irq);
248 }
249
250 static void mpc52xx_periph_unmask(struct irq_data *d)
251 {
252 int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
253 io_be_clrbit(&intr->per_mask, 31 - l2irq);
254 }
255
256 static struct irq_chip mpc52xx_periph_irqchip = {
257 .name = "MPC52xx Peripherals",
258 .irq_mask = mpc52xx_periph_mask,
259 .irq_mask_ack = mpc52xx_periph_mask,
260 .irq_unmask = mpc52xx_periph_unmask,
261 .irq_set_type = mpc52xx_null_set_type,
262 };
263
264 /*
265 * SDMA interrupt irq_chip
266 */
267 static void mpc52xx_sdma_mask(struct irq_data *d)
268 {
269 int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
270 io_be_setbit(&sdma->IntMask, l2irq);
271 }
272
273 static void mpc52xx_sdma_unmask(struct irq_data *d)
274 {
275 int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
276 io_be_clrbit(&sdma->IntMask, l2irq);
277 }
278
279 static void mpc52xx_sdma_ack(struct irq_data *d)
280 {
281 int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
282 out_be32(&sdma->IntPend, 1 << l2irq);
283 }
284
285 static struct irq_chip mpc52xx_sdma_irqchip = {
286 .name = "MPC52xx SDMA",
287 .irq_mask = mpc52xx_sdma_mask,
288 .irq_unmask = mpc52xx_sdma_unmask,
289 .irq_ack = mpc52xx_sdma_ack,
290 .irq_set_type = mpc52xx_null_set_type,
291 };
292
293 /**
294 * mpc52xx_is_extirq - Returns true if hwirq number is for an external IRQ
295 */
296 static int mpc52xx_is_extirq(int l1, int l2)
297 {
298 return ((l1 == 0) && (l2 == 0)) ||
299 ((l1 == 1) && (l2 >= 1) && (l2 <= 3));
300 }
301
302 /**
303 * mpc52xx_irqhost_xlate - translate virq# from device tree interrupts property
304 */
305 static int mpc52xx_irqhost_xlate(struct irq_domain *h, struct device_node *ct,
306 const u32 *intspec, unsigned int intsize,
307 irq_hw_number_t *out_hwirq,
308 unsigned int *out_flags)
309 {
310 int intrvect_l1;
311 int intrvect_l2;
312 int intrvect_type;
313 int intrvect_linux;
314
315 if (intsize != 3)
316 return -1;
317
318 intrvect_l1 = (int)intspec[0];
319 intrvect_l2 = (int)intspec[1];
320 intrvect_type = (int)intspec[2] & 0x3;
321
322 intrvect_linux = (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) &
323 MPC52xx_IRQ_L1_MASK;
324 intrvect_linux |= intrvect_l2 & MPC52xx_IRQ_L2_MASK;
325
326 *out_hwirq = intrvect_linux;
327 *out_flags = IRQ_TYPE_LEVEL_LOW;
328 if (mpc52xx_is_extirq(intrvect_l1, intrvect_l2))
329 *out_flags = mpc52xx_map_senses[intrvect_type];
330
331 pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1,
332 intrvect_l2);
333 return 0;
334 }
335
336 /**
337 * mpc52xx_irqhost_map - Hook to map from virq to an irq_chip structure
338 */
339 static int mpc52xx_irqhost_map(struct irq_domain *h, unsigned int virq,
340 irq_hw_number_t irq)
341 {
342 int l1irq;
343 int l2irq;
344 struct irq_chip *irqchip;
345 void *hndlr;
346 int type;
347 u32 reg;
348
349 l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
350 l2irq = irq & MPC52xx_IRQ_L2_MASK;
351
352 /*
353 * External IRQs are handled differently by the hardware so they are
354 * handled by a dedicated irq_chip structure.
355 */
356 if (mpc52xx_is_extirq(l1irq, l2irq)) {
357 reg = in_be32(&intr->ctrl);
358 type = mpc52xx_map_senses[(reg >> (22 - l2irq * 2)) & 0x3];
359 if ((type == IRQ_TYPE_EDGE_FALLING) ||
360 (type == IRQ_TYPE_EDGE_RISING))
361 hndlr = handle_edge_irq;
362 else
363 hndlr = handle_level_irq;
364
365 irq_set_chip_and_handler(virq, &mpc52xx_extirq_irqchip, hndlr);
366 pr_debug("%s: External IRQ%i virq=%x, hw=%x. type=%x\n",
367 __func__, l2irq, virq, (int)irq, type);
368 return 0;
369 }
370
371 /* It is an internal SOC irq. Choose the correct irq_chip */
372 switch (l1irq) {
373 case MPC52xx_IRQ_L1_MAIN: irqchip = &mpc52xx_main_irqchip; break;
374 case MPC52xx_IRQ_L1_PERP: irqchip = &mpc52xx_periph_irqchip; break;
375 case MPC52xx_IRQ_L1_SDMA: irqchip = &mpc52xx_sdma_irqchip; break;
376 case MPC52xx_IRQ_L1_CRIT:
377 pr_warn("%s: Critical IRQ #%d is unsupported! Nopping it.\n",
378 __func__, l2irq);
379 irq_set_chip(virq, &no_irq_chip);
380 return 0;
381 }
382
383 irq_set_chip_and_handler(virq, irqchip, handle_level_irq);
384 pr_debug("%s: virq=%x, l1=%i, l2=%i\n", __func__, virq, l1irq, l2irq);
385
386 return 0;
387 }
388
389 static const struct irq_domain_ops mpc52xx_irqhost_ops = {
390 .xlate = mpc52xx_irqhost_xlate,
391 .map = mpc52xx_irqhost_map,
392 };
393
394 /**
395 * mpc52xx_init_irq - Initialize and register with the virq subsystem
396 *
397 * Hook for setting up IRQs on an mpc5200 system. A pointer to this function
398 * is to be put into the machine definition structure.
399 *
400 * This function searches the device tree for an MPC5200 interrupt controller,
401 * initializes it, and registers it with the virq subsystem.
402 */
403 void __init mpc52xx_init_irq(void)
404 {
405 u32 intr_ctrl;
406 struct device_node *picnode;
407 struct device_node *np;
408
409 /* Remap the necessary zones */
410 picnode = of_find_matching_node(NULL, mpc52xx_pic_ids);
411 intr = of_iomap(picnode, 0);
412 if (!intr)
413 panic(__FILE__ ": find_and_map failed on 'mpc5200-pic'. "
414 "Check node !");
415
416 np = of_find_matching_node(NULL, mpc52xx_sdma_ids);
417 sdma = of_iomap(np, 0);
418 of_node_put(np);
419 if (!sdma)
420 panic(__FILE__ ": find_and_map failed on 'mpc5200-bestcomm'. "
421 "Check node !");
422
423 pr_debug("MPC5200 IRQ controller mapped to 0x%p\n", intr);
424
425 /* Disable all interrupt sources. */
426 out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
427 out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
428 out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
429 out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
430 intr_ctrl = in_be32(&intr->ctrl);
431 intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */
432 intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
433 0x00001000 | /* MEE master external enable */
434 0x00000000 | /* 0 means disable IRQ 0-3 */
435 0x00000001; /* CEb route critical normally */
436 out_be32(&intr->ctrl, intr_ctrl);
437
438 /* Zero a bunch of the priority settings. */
439 out_be32(&intr->per_pri1, 0);
440 out_be32(&intr->per_pri2, 0);
441 out_be32(&intr->per_pri3, 0);
442 out_be32(&intr->main_pri1, 0);
443 out_be32(&intr->main_pri2, 0);
444
445 /*
446 * As last step, add an irq host to translate the real
447 * hw irq information provided by the ofw to linux virq
448 */
449 mpc52xx_irqhost = irq_domain_add_linear(picnode,
450 MPC52xx_IRQ_HIGHTESTHWIRQ,
451 &mpc52xx_irqhost_ops, NULL);
452
453 if (!mpc52xx_irqhost)
454 panic(__FILE__ ": Cannot allocate the IRQ host\n");
455
456 irq_set_default_host(mpc52xx_irqhost);
457
458 pr_info("MPC52xx PIC is up and running!\n");
459 }
460
461 /**
462 * mpc52xx_get_irq - Get pending interrupt number hook function
463 *
464 * Called by the interrupt handler to determine what IRQ handler needs to be
465 * executed.
466 *
467 * Status of pending interrupts is determined by reading the encoded status
468 * register. The encoded status register has three fields; one for each of the
469 * types of interrupts defined by the controller - 'critical', 'main' and
470 * 'peripheral'. This function reads the status register and returns the IRQ
471 * number associated with the highest priority pending interrupt. 'Critical'
472 * interrupts have the highest priority, followed by 'main' interrupts, and
473 * then 'peripheral'.
474 *
475 * The mpc5200 interrupt controller can be configured to boost the priority
476 * of individual 'peripheral' interrupts. If this is the case then a special
477 * value will appear in either the crit or main fields indicating a high
478 * or medium priority peripheral irq has occurred.
479 *
480 * This function checks each of the 3 irq request fields and returns the
481 * first pending interrupt that it finds.
482 *
483 * This function also identifies a 4th type of interrupt; 'bestcomm'. Each
484 * bestcomm DMA task can raise the bestcomm peripheral interrupt. When this
485 * occurs at task-specific IRQ# is decoded so that each task can have its
486 * own IRQ handler.
487 */
488 unsigned int mpc52xx_get_irq(void)
489 {
490 u32 status;
491 int irq;
492
493 status = in_be32(&intr->enc_status);
494 if (status & 0x00000400) { /* critical */
495 irq = (status >> 8) & 0x3;
496 if (irq == 2) /* high priority peripheral */
497 goto peripheral;
498 irq |= (MPC52xx_IRQ_L1_CRIT << MPC52xx_IRQ_L1_OFFSET);
499 } else if (status & 0x00200000) { /* main */
500 irq = (status >> 16) & 0x1f;
501 if (irq == 4) /* low priority peripheral */
502 goto peripheral;
503 irq |= (MPC52xx_IRQ_L1_MAIN << MPC52xx_IRQ_L1_OFFSET);
504 } else if (status & 0x20000000) { /* peripheral */
505 peripheral:
506 irq = (status >> 24) & 0x1f;
507 if (irq == 0) { /* bestcomm */
508 status = in_be32(&sdma->IntPend);
509 irq = ffs(status) - 1;
510 irq |= (MPC52xx_IRQ_L1_SDMA << MPC52xx_IRQ_L1_OFFSET);
511 } else {
512 irq |= (MPC52xx_IRQ_L1_PERP << MPC52xx_IRQ_L1_OFFSET);
513 }
514 } else {
515 return 0;
516 }
517
518 return irq_linear_revmap(mpc52xx_irqhost, irq);
519 }
520
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