1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * GE IMP3A Board Setup
4 *
5 * Author Martyn Welch <martyn.welch@ge.com>
6 *
7 * Copyright 2010 GE Intelligent Platforms Embedded Systems, Inc.
8 *
9 * Based on: mpc85xx_ds.c (MPC85xx DS Board Setup)
10 * Copyright 2007 Freescale Semiconductor Inc.
11 */
12
13 #include <linux/stddef.h>
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/kdev_t.h>
17 #include <linux/delay.h>
18 #include <linux/seq_file.h>
19 #include <linux/interrupt.h>
20 #include <linux/of.h>
21 #include <linux/of_address.h>
22
23 #include <asm/time.h>
24 #include <asm/machdep.h>
25 #include <asm/pci-bridge.h>
26 #include <mm/mmu_decl.h>
27 #include <asm/udbg.h>
28 #include <asm/mpic.h>
29 #include <asm/swiotlb.h>
30 #include <asm/nvram.h>
31
32 #include <sysdev/fsl_soc.h>
33 #include <sysdev/fsl_pci.h>
34 #include "smp.h"
35
36 #include "mpc85xx.h"
37 #include <sysdev/ge/ge_pic.h>
38
39 void __iomem *imp3a_regs;
40
41 static void __init ge_imp3a_pic_init(void)
42 {
43 struct mpic *mpic;
44 struct device_node *np;
45 struct device_node *cascade_node = NULL;
46
47 if (of_machine_is_compatible("fsl,MPC8572DS-CAMP")) {
48 mpic = mpic_alloc(NULL, 0,
49 MPIC_NO_RESET |
50 MPIC_BIG_ENDIAN |
51 MPIC_SINGLE_DEST_CPU,
52 0, 256, " OpenPIC ");
53 } else {
54 mpic = mpic_alloc(NULL, 0,
55 MPIC_BIG_ENDIAN |
56 MPIC_SINGLE_DEST_CPU,
57 0, 256, " OpenPIC ");
58 }
59
60 BUG_ON(mpic == NULL);
61 mpic_init(mpic);
62 /*
63 * There is a simple interrupt handler in the main FPGA, this needs
64 * to be cascaded into the MPIC
65 */
66 for_each_node_by_type(np, "interrupt-controller")
67 if (of_device_is_compatible(np, "gef,fpga-pic-1.00")) {
68 cascade_node = np;
69 break;
70 }
71
72 if (cascade_node == NULL) {
73 printk(KERN_WARNING "IMP3A: No FPGA PIC\n");
74 return;
75 }
76
77 gef_pic_init(cascade_node);
78 of_node_put(cascade_node);
79 }
80
81 static void __init ge_imp3a_pci_assign_primary(void)
82 {
83 #ifdef CONFIG_PCI
84 struct device_node *np;
85 struct resource rsrc;
86
87 for_each_node_by_type(np, "pci") {
88 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
89 of_device_is_compatible(np, "fsl,mpc8548-pcie") ||
90 of_device_is_compatible(np, "fsl,p2020-pcie")) {
91 of_address_to_resource(np, 0, &rsrc);
92 if ((rsrc.start & 0xfffff) == 0x9000) {
93 of_node_put(fsl_pci_primary);
94 fsl_pci_primary = of_node_get(np);
95 }
96 }
97 }
98 #endif
99 }
100
101 /*
102 * Setup the architecture
103 */
104 static void __init ge_imp3a_setup_arch(void)
105 {
106 struct device_node *regs;
107
108 if (ppc_md.progress)
109 ppc_md.progress("ge_imp3a_setup_arch()", 0);
110
111 mpc85xx_smp_init();
112
113 ge_imp3a_pci_assign_primary();
114
115 swiotlb_detect_4g();
116
117 /* Remap basic board registers */
118 regs = of_find_compatible_node(NULL, NULL, "ge,imp3a-fpga-regs");
119 if (regs) {
120 imp3a_regs = of_iomap(regs, 0);
121 if (imp3a_regs == NULL)
122 printk(KERN_WARNING "Unable to map board registers\n");
123 of_node_put(regs);
124 }
125
126 #if defined(CONFIG_MMIO_NVRAM)
127 mmio_nvram_init();
128 #endif
129
130 printk(KERN_INFO "GE Intelligent Platforms IMP3A 3U cPCI SBC\n");
131 }
132
133 /* Return the PCB revision */
134 static unsigned int ge_imp3a_get_pcb_rev(void)
135 {
136 unsigned int reg;
137
138 reg = ioread16(imp3a_regs);
139 return (reg >> 8) & 0xff;
140 }
141
142 /* Return the board (software) revision */
143 static unsigned int ge_imp3a_get_board_rev(void)
144 {
145 unsigned int reg;
146
147 reg = ioread16(imp3a_regs + 0x2);
148 return reg & 0xff;
149 }
150
151 /* Return the FPGA revision */
152 static unsigned int ge_imp3a_get_fpga_rev(void)
153 {
154 unsigned int reg;
155
156 reg = ioread16(imp3a_regs + 0x2);
157 return (reg >> 8) & 0xff;
158 }
159
160 /* Return compactPCI Geographical Address */
161 static unsigned int ge_imp3a_get_cpci_geo_addr(void)
162 {
163 unsigned int reg;
164
165 reg = ioread16(imp3a_regs + 0x6);
166 return (reg & 0x0f00) >> 8;
167 }
168
169 /* Return compactPCI System Controller Status */
170 static unsigned int ge_imp3a_get_cpci_is_syscon(void)
171 {
172 unsigned int reg;
173
174 reg = ioread16(imp3a_regs + 0x6);
175 return reg & (1 << 12);
176 }
177
178 static void ge_imp3a_show_cpuinfo(struct seq_file *m)
179 {
180 seq_printf(m, "Vendor\t\t: GE Intelligent Platforms\n");
181
182 seq_printf(m, "Revision\t: %u%c\n", ge_imp3a_get_pcb_rev(),
183 ('A' + ge_imp3a_get_board_rev() - 1));
184
185 seq_printf(m, "FPGA Revision\t: %u\n", ge_imp3a_get_fpga_rev());
186
187 seq_printf(m, "cPCI geo. addr\t: %u\n", ge_imp3a_get_cpci_geo_addr());
188
189 seq_printf(m, "cPCI syscon\t: %s\n",
190 ge_imp3a_get_cpci_is_syscon() ? "yes" : "no");
191 }
192
193 machine_arch_initcall(ge_imp3a, mpc85xx_common_publish_devices);
194
195 define_machine(ge_imp3a) {
196 .name = "GE_IMP3A",
197 .compatible = "ge,IMP3A",
198 .setup_arch = ge_imp3a_setup_arch,
199 .init_IRQ = ge_imp3a_pic_init,
200 .show_cpuinfo = ge_imp3a_show_cpuinfo,
201 #ifdef CONFIG_PCI
202 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
203 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
204 #endif
205 .get_irq = mpic_get_irq,
206 .progress = udbg_progress,
207 };
208
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