1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Support for PCI bridges found on Power Macintoshes.
4 *
5 * Copyright (C) 2003-2005 Benjamin Herrenschmuidt (benh@kernel.crashing.org)
6 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/delay.h>
12 #include <linux/string.h>
13 #include <linux/init.h>
14 #include <linux/irq.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/of_pci.h>
18
19 #include <asm/sections.h>
20 #include <asm/io.h>
21 #include <asm/pci-bridge.h>
22 #include <asm/machdep.h>
23 #include <asm/pmac_feature.h>
24 #include <asm/grackle.h>
25 #include <asm/ppc-pci.h>
26
27 #include "pmac.h"
28
29 #undef DEBUG
30
31 #ifdef DEBUG
32 #define DBG(x...) printk(x)
33 #else
34 #define DBG(x...)
35 #endif
36
37 /* XXX Could be per-controller, but I don't think we risk anything by
38 * assuming we won't have both UniNorth and Bandit */
39 static int has_uninorth;
40 #ifdef CONFIG_PPC64
41 static struct pci_controller *u3_agp;
42 #else
43 static int has_second_ohare;
44 #endif /* CONFIG_PPC64 */
45
46 extern int pcibios_assign_bus_offset;
47
48 struct device_node *k2_skiplist[2];
49
50 /*
51 * Magic constants for enabling cache coherency in the bandit/PSX bridge.
52 */
53 #define BANDIT_DEVID_2 8
54 #define BANDIT_REVID 3
55
56 #define BANDIT_DEVNUM 11
57 #define BANDIT_MAGIC 0x50
58 #define BANDIT_COHERENT 0x40
59
60 static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
61 {
62 for (; node; node = node->sibling) {
63 const int * bus_range;
64 const unsigned int *class_code;
65 int len;
66
67 /* For PCI<->PCI bridges or CardBus bridges, we go down */
68 class_code = of_get_property(node, "class-code", NULL);
69 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
70 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
71 continue;
72 bus_range = of_get_property(node, "bus-range", &len);
73 if (bus_range != NULL && len > 2 * sizeof(int)) {
74 if (bus_range[1] > higher)
75 higher = bus_range[1];
76 }
77 higher = fixup_one_level_bus_range(node->child, higher);
78 }
79 return higher;
80 }
81
82 /* This routine fixes the "bus-range" property of all bridges in the
83 * system since they tend to have their "last" member wrong on macs
84 *
85 * Note that the bus numbers manipulated here are OF bus numbers, they
86 * are not Linux bus numbers.
87 */
88 static void __init fixup_bus_range(struct device_node *bridge)
89 {
90 int *bus_range, len;
91 struct property *prop;
92
93 /* Lookup the "bus-range" property for the hose */
94 prop = of_find_property(bridge, "bus-range", &len);
95 if (prop == NULL || prop->length < 2 * sizeof(int))
96 return;
97
98 bus_range = prop->value;
99 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
100 }
101
102 /*
103 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers.
104 *
105 * The "Bandit" version is present in all early PCI PowerMacs,
106 * and up to the first ones using Grackle. Some machines may
107 * have 2 bandit controllers (2 PCI busses).
108 *
109 * "Chaos" is used in some "Bandit"-type machines as a bridge
110 * for the separate display bus. It is accessed the same
111 * way as bandit, but cannot be probed for devices. It therefore
112 * has its own config access functions.
113 *
114 * The "UniNorth" version is present in all Core99 machines
115 * (iBook, G4, new IMacs, and all the recent Apple machines).
116 * It contains 3 controllers in one ASIC.
117 *
118 * The U3 is the bridge used on G5 machines. It contains an
119 * AGP bus which is dealt with the old UniNorth access routines
120 * and a HyperTransport bus which uses its own set of access
121 * functions.
122 */
123
124 #define MACRISC_CFA0(devfn, off) \
125 ((1 << (unsigned int)PCI_SLOT(dev_fn)) \
126 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \
127 | (((unsigned int)(off)) & 0xFCUL))
128
129 #define MACRISC_CFA1(bus, devfn, off) \
130 ((((unsigned int)(bus)) << 16) \
131 |(((unsigned int)(devfn)) << 8) \
132 |(((unsigned int)(off)) & 0xFCUL) \
133 |1UL)
134
135 static void __iomem *macrisc_cfg_map_bus(struct pci_bus *bus,
136 unsigned int dev_fn,
137 int offset)
138 {
139 unsigned int caddr;
140 struct pci_controller *hose;
141
142 hose = pci_bus_to_host(bus);
143 if (hose == NULL)
144 return NULL;
145
146 if (bus->number == hose->first_busno) {
147 if (dev_fn < (11 << 3))
148 return NULL;
149 caddr = MACRISC_CFA0(dev_fn, offset);
150 } else
151 caddr = MACRISC_CFA1(bus->number, dev_fn, offset);
152
153 /* Uninorth will return garbage if we don't read back the value ! */
154 do {
155 out_le32(hose->cfg_addr, caddr);
156 } while (in_le32(hose->cfg_addr) != caddr);
157
158 offset &= has_uninorth ? 0x07 : 0x03;
159 return hose->cfg_data + offset;
160 }
161
162 static struct pci_ops macrisc_pci_ops =
163 {
164 .map_bus = macrisc_cfg_map_bus,
165 .read = pci_generic_config_read,
166 .write = pci_generic_config_write,
167 };
168
169 #ifdef CONFIG_PPC32
170 /*
171 * Verify that a specific (bus, dev_fn) exists on chaos
172 */
173 static void __iomem *chaos_map_bus(struct pci_bus *bus, unsigned int devfn,
174 int offset)
175 {
176 struct device_node *np;
177 const u32 *vendor, *device;
178
179 if (offset >= 0x100)
180 return NULL;
181 np = of_pci_find_child_device(bus->dev.of_node, devfn);
182 if (np == NULL)
183 return NULL;
184
185 vendor = of_get_property(np, "vendor-id", NULL);
186 device = of_get_property(np, "device-id", NULL);
187 if (vendor == NULL || device == NULL)
188 return NULL;
189
190 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10)
191 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24))
192 return NULL;
193
194 return macrisc_cfg_map_bus(bus, devfn, offset);
195 }
196
197 static struct pci_ops chaos_pci_ops =
198 {
199 .map_bus = chaos_map_bus,
200 .read = pci_generic_config_read,
201 .write = pci_generic_config_write,
202 };
203
204 static void __init setup_chaos(struct pci_controller *hose,
205 struct resource *addr)
206 {
207 /* assume a `chaos' bridge */
208 hose->ops = &chaos_pci_ops;
209 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
210 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
211 }
212 #endif /* CONFIG_PPC32 */
213
214 #ifdef CONFIG_PPC64
215 /*
216 * These versions of U3 HyperTransport config space access ops do not
217 * implement self-view of the HT host yet
218 */
219
220 /*
221 * This function deals with some "special cases" devices.
222 *
223 * 0 -> No special case
224 * 1 -> Skip the device but act as if the access was successful
225 * (return 0xff's on reads, eventually, cache config space
226 * accesses in a later version)
227 * -1 -> Hide the device (unsuccessful access)
228 */
229 static int u3_ht_skip_device(struct pci_controller *hose,
230 struct pci_bus *bus, unsigned int devfn)
231 {
232 struct device_node *busdn, *dn;
233 int i;
234
235 /* We only allow config cycles to devices that are in OF device-tree
236 * as we are apparently having some weird things going on with some
237 * revs of K2 on recent G5s, except for the host bridge itself, which
238 * is missing from the tree but we know we can probe.
239 */
240 if (bus->self)
241 busdn = pci_device_to_OF_node(bus->self);
242 else if (devfn == 0)
243 return 0;
244 else
245 busdn = hose->dn;
246 for (dn = busdn->child; dn; dn = dn->sibling)
247 if (PCI_DN(dn) && PCI_DN(dn)->devfn == devfn)
248 break;
249 if (dn == NULL)
250 return -1;
251
252 /*
253 * When a device in K2 is powered down, we die on config
254 * cycle accesses. Fix that here.
255 */
256 for (i=0; i<2; i++)
257 if (k2_skiplist[i] == dn)
258 return 1;
259
260 return 0;
261 }
262
263 #define U3_HT_CFA0(devfn, off) \
264 ((((unsigned int)devfn) << 8) | offset)
265 #define U3_HT_CFA1(bus, devfn, off) \
266 (U3_HT_CFA0(devfn, off) \
267 + (((unsigned int)bus) << 16) \
268 + 0x01000000UL)
269
270 static void __iomem *u3_ht_cfg_access(struct pci_controller *hose, u8 bus,
271 u8 devfn, u8 offset, int *swap)
272 {
273 *swap = 1;
274 if (bus == hose->first_busno) {
275 if (devfn != 0)
276 return hose->cfg_data + U3_HT_CFA0(devfn, offset);
277 *swap = 0;
278 return ((void __iomem *)hose->cfg_addr) + (offset << 2);
279 } else
280 return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset);
281 }
282
283 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
284 int offset, int len, u32 *val)
285 {
286 struct pci_controller *hose;
287 void __iomem *addr;
288 int swap;
289
290 hose = pci_bus_to_host(bus);
291 if (hose == NULL)
292 return PCIBIOS_DEVICE_NOT_FOUND;
293 if (offset >= 0x100)
294 return PCIBIOS_BAD_REGISTER_NUMBER;
295 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap);
296 if (!addr)
297 return PCIBIOS_DEVICE_NOT_FOUND;
298
299 switch (u3_ht_skip_device(hose, bus, devfn)) {
300 case 0:
301 break;
302 case 1:
303 switch (len) {
304 case 1:
305 *val = 0xff; break;
306 case 2:
307 *val = 0xffff; break;
308 default:
309 *val = 0xfffffffful; break;
310 }
311 return PCIBIOS_SUCCESSFUL;
312 default:
313 return PCIBIOS_DEVICE_NOT_FOUND;
314 }
315
316 /*
317 * Note: the caller has already checked that offset is
318 * suitably aligned and that len is 1, 2 or 4.
319 */
320 switch (len) {
321 case 1:
322 *val = in_8(addr);
323 break;
324 case 2:
325 *val = swap ? in_le16(addr) : in_be16(addr);
326 break;
327 default:
328 *val = swap ? in_le32(addr) : in_be32(addr);
329 break;
330 }
331 return PCIBIOS_SUCCESSFUL;
332 }
333
334 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
335 int offset, int len, u32 val)
336 {
337 struct pci_controller *hose;
338 void __iomem *addr;
339 int swap;
340
341 hose = pci_bus_to_host(bus);
342 if (hose == NULL)
343 return PCIBIOS_DEVICE_NOT_FOUND;
344 if (offset >= 0x100)
345 return PCIBIOS_BAD_REGISTER_NUMBER;
346 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap);
347 if (!addr)
348 return PCIBIOS_DEVICE_NOT_FOUND;
349
350 switch (u3_ht_skip_device(hose, bus, devfn)) {
351 case 0:
352 break;
353 case 1:
354 return PCIBIOS_SUCCESSFUL;
355 default:
356 return PCIBIOS_DEVICE_NOT_FOUND;
357 }
358
359 /*
360 * Note: the caller has already checked that offset is
361 * suitably aligned and that len is 1, 2 or 4.
362 */
363 switch (len) {
364 case 1:
365 out_8(addr, val);
366 break;
367 case 2:
368 swap ? out_le16(addr, val) : out_be16(addr, val);
369 break;
370 default:
371 swap ? out_le32(addr, val) : out_be32(addr, val);
372 break;
373 }
374 return PCIBIOS_SUCCESSFUL;
375 }
376
377 static struct pci_ops u3_ht_pci_ops =
378 {
379 .read = u3_ht_read_config,
380 .write = u3_ht_write_config,
381 };
382
383 #define U4_PCIE_CFA0(devfn, off) \
384 ((1 << ((unsigned int)PCI_SLOT(dev_fn))) \
385 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \
386 | ((((unsigned int)(off)) >> 8) << 28) \
387 | (((unsigned int)(off)) & 0xfcU))
388
389 #define U4_PCIE_CFA1(bus, devfn, off) \
390 ((((unsigned int)(bus)) << 16) \
391 |(((unsigned int)(devfn)) << 8) \
392 | ((((unsigned int)(off)) >> 8) << 28) \
393 |(((unsigned int)(off)) & 0xfcU) \
394 |1UL)
395
396 static void __iomem *u4_pcie_cfg_map_bus(struct pci_bus *bus,
397 unsigned int dev_fn,
398 int offset)
399 {
400 struct pci_controller *hose;
401 unsigned int caddr;
402
403 if (offset >= 0x1000)
404 return NULL;
405
406 hose = pci_bus_to_host(bus);
407 if (!hose)
408 return NULL;
409
410 if (bus->number == hose->first_busno) {
411 caddr = U4_PCIE_CFA0(dev_fn, offset);
412 } else
413 caddr = U4_PCIE_CFA1(bus->number, dev_fn, offset);
414
415 /* Uninorth will return garbage if we don't read back the value ! */
416 do {
417 out_le32(hose->cfg_addr, caddr);
418 } while (in_le32(hose->cfg_addr) != caddr);
419
420 offset &= 0x03;
421 return hose->cfg_data + offset;
422 }
423
424 static struct pci_ops u4_pcie_pci_ops =
425 {
426 .map_bus = u4_pcie_cfg_map_bus,
427 .read = pci_generic_config_read,
428 .write = pci_generic_config_write,
429 };
430
431 static void pmac_pci_fixup_u4_of_node(struct pci_dev *dev)
432 {
433 /* Apple's device-tree "hides" the root complex virtual P2P bridge
434 * on U4. However, Linux sees it, causing the PCI <-> OF matching
435 * code to fail to properly match devices below it. This works around
436 * it by setting the node of the bridge to point to the PHB node,
437 * which is not entirely correct but fixes the matching code and
438 * doesn't break anything else. It's also the simplest possible fix.
439 */
440 if (dev->dev.of_node == NULL)
441 dev->dev.of_node = pcibios_get_phb_of_node(dev->bus);
442 }
443 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, 0x5b, pmac_pci_fixup_u4_of_node);
444
445 #endif /* CONFIG_PPC64 */
446
447 #ifdef CONFIG_PPC32
448 /*
449 * For a bandit bridge, turn on cache coherency if necessary.
450 * N.B. we could clean this up using the hose ops directly.
451 */
452 static void __init init_bandit(struct pci_controller *bp)
453 {
454 unsigned int vendev, magic;
455 int rev;
456
457 /* read the word at offset 0 in config space for device 11 */
458 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID);
459 udelay(2);
460 vendev = in_le32(bp->cfg_data);
461 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) +
462 PCI_VENDOR_ID_APPLE) {
463 /* read the revision id */
464 out_le32(bp->cfg_addr,
465 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID);
466 udelay(2);
467 rev = in_8(bp->cfg_data);
468 if (rev != BANDIT_REVID)
469 printk(KERN_WARNING
470 "Unknown revision %d for bandit\n", rev);
471 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) {
472 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev);
473 return;
474 }
475
476 /* read the word at offset 0x50 */
477 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC);
478 udelay(2);
479 magic = in_le32(bp->cfg_data);
480 if ((magic & BANDIT_COHERENT) != 0)
481 return;
482 magic |= BANDIT_COHERENT;
483 udelay(2);
484 out_le32(bp->cfg_data, magic);
485 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n");
486 }
487
488 /*
489 * Tweak the PCI-PCI bridge chip on the blue & white G3s.
490 */
491 static void __init init_p2pbridge(void)
492 {
493 struct device_node *p2pbridge;
494 struct pci_controller* hose;
495 u8 bus, devfn;
496 u16 val;
497
498 /* XXX it would be better here to identify the specific
499 PCI-PCI bridge chip we have. */
500 p2pbridge = of_find_node_by_name(NULL, "pci-bridge");
501 if (p2pbridge == NULL || !of_node_name_eq(p2pbridge->parent, "pci"))
502 goto done;
503 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) {
504 DBG("Can't find PCI infos for PCI<->PCI bridge\n");
505 goto done;
506 }
507 /* Warning: At this point, we have not yet renumbered all busses.
508 * So we must use OF walking to find out hose
509 */
510 hose = pci_find_hose_for_OF_device(p2pbridge);
511 if (!hose) {
512 DBG("Can't find hose for PCI<->PCI bridge\n");
513 goto done;
514 }
515 if (early_read_config_word(hose, bus, devfn,
516 PCI_BRIDGE_CONTROL, &val) < 0) {
517 printk(KERN_ERR "init_p2pbridge: couldn't read bridge"
518 " control\n");
519 goto done;
520 }
521 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT;
522 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val);
523 done:
524 of_node_put(p2pbridge);
525 }
526
527 static void __init init_second_ohare(void)
528 {
529 struct device_node *np = of_find_node_by_name(NULL, "pci106b,7");
530 unsigned char bus, devfn;
531 unsigned short cmd;
532
533 if (np == NULL)
534 return;
535
536 /* This must run before we initialize the PICs since the second
537 * ohare hosts a PIC that will be accessed there.
538 */
539 if (pci_device_from_OF_node(np, &bus, &devfn) == 0) {
540 struct pci_controller* hose =
541 pci_find_hose_for_OF_device(np);
542 if (!hose) {
543 printk(KERN_ERR "Can't find PCI hose for OHare2 !\n");
544 of_node_put(np);
545 return;
546 }
547 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd);
548 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
549 cmd &= ~PCI_COMMAND_IO;
550 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd);
551 }
552 has_second_ohare = 1;
553 of_node_put(np);
554 }
555
556 /*
557 * Some Apple desktop machines have a NEC PD720100A USB2 controller
558 * on the motherboard. Open Firmware, on these, will disable the
559 * EHCI part of it so it behaves like a pair of OHCI's. This fixup
560 * code re-enables it ;)
561 */
562 static void __init fixup_nec_usb2(void)
563 {
564 struct device_node *nec;
565
566 for_each_node_by_name(nec, "usb") {
567 struct pci_controller *hose;
568 u32 data;
569 const u32 *prop;
570 u8 bus, devfn;
571
572 prop = of_get_property(nec, "vendor-id", NULL);
573 if (prop == NULL)
574 continue;
575 if (0x1033 != *prop)
576 continue;
577 prop = of_get_property(nec, "device-id", NULL);
578 if (prop == NULL)
579 continue;
580 if (0x0035 != *prop)
581 continue;
582 prop = of_get_property(nec, "reg", NULL);
583 if (prop == NULL)
584 continue;
585 devfn = (prop[0] >> 8) & 0xff;
586 bus = (prop[0] >> 16) & 0xff;
587 if (PCI_FUNC(devfn) != 0)
588 continue;
589 hose = pci_find_hose_for_OF_device(nec);
590 if (!hose)
591 continue;
592 early_read_config_dword(hose, bus, devfn, 0xe4, &data);
593 if (data & 1UL) {
594 printk("Found NEC PD720100A USB2 chip with disabled"
595 " EHCI, fixing up...\n");
596 data &= ~1UL;
597 early_write_config_dword(hose, bus, devfn, 0xe4, data);
598 }
599 }
600 }
601
602 static void __init setup_bandit(struct pci_controller *hose,
603 struct resource *addr)
604 {
605 hose->ops = ¯isc_pci_ops;
606 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
607 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
608 init_bandit(hose);
609 }
610
611 static int __init setup_uninorth(struct pci_controller *hose,
612 struct resource *addr)
613 {
614 pci_add_flags(PCI_REASSIGN_ALL_BUS);
615 has_uninorth = 1;
616 hose->ops = ¯isc_pci_ops;
617 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
618 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
619 /* We "know" that the bridge at f2000000 has the PCI slots. */
620 return addr->start == 0xf2000000;
621 }
622 #endif /* CONFIG_PPC32 */
623
624 #ifdef CONFIG_PPC64
625 static void __init setup_u3_agp(struct pci_controller* hose)
626 {
627 /* On G5, we move AGP up to high bus number so we don't need
628 * to reassign bus numbers for HT. If we ever have P2P bridges
629 * on AGP, we'll have to move pci_assign_all_busses to the
630 * pci_controller structure so we enable it for AGP and not for
631 * HT childs.
632 * We hard code the address because of the different size of
633 * the reg address cell, we shall fix that by killing struct
634 * reg_property and using some accessor functions instead
635 */
636 hose->first_busno = 0xf0;
637 hose->last_busno = 0xff;
638 has_uninorth = 1;
639 hose->ops = ¯isc_pci_ops;
640 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
641 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
642 u3_agp = hose;
643 }
644
645 static void __init setup_u4_pcie(struct pci_controller* hose)
646 {
647 /* We currently only implement the "non-atomic" config space, to
648 * be optimised later.
649 */
650 hose->ops = &u4_pcie_pci_ops;
651 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
652 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
653
654 /* The bus contains a bridge from root -> device, we need to
655 * make it visible on bus 0 so that we pick the right type
656 * of config cycles. If we didn't, we would have to force all
657 * config cycles to be type 1. So we override the "bus-range"
658 * property here
659 */
660 hose->first_busno = 0x00;
661 hose->last_busno = 0xff;
662 }
663
664 static void __init parse_region_decode(struct pci_controller *hose,
665 u32 decode)
666 {
667 unsigned long base, end, next = -1;
668 int i, cur = -1;
669
670 /* Iterate through all bits. We ignore the last bit as this region is
671 * reserved for the ROM among other niceties
672 */
673 for (i = 0; i < 31; i++) {
674 if ((decode & (0x80000000 >> i)) == 0)
675 continue;
676 if (i < 16) {
677 base = 0xf0000000 | (((u32)i) << 24);
678 end = base + 0x00ffffff;
679 } else {
680 base = ((u32)i-16) << 28;
681 end = base + 0x0fffffff;
682 }
683 if (base != next) {
684 if (++cur >= 3) {
685 printk(KERN_WARNING "PCI: Too many ranges !\n");
686 break;
687 }
688 hose->mem_resources[cur].flags = IORESOURCE_MEM;
689 hose->mem_resources[cur].name = hose->dn->full_name;
690 hose->mem_resources[cur].start = base;
691 hose->mem_resources[cur].end = end;
692 hose->mem_offset[cur] = 0;
693 DBG(" %d: 0x%08lx-0x%08lx\n", cur, base, end);
694 } else {
695 DBG(" : -0x%08lx\n", end);
696 hose->mem_resources[cur].end = end;
697 }
698 next = end + 1;
699 }
700 }
701
702 static void __init setup_u3_ht(struct pci_controller* hose)
703 {
704 struct device_node *np = hose->dn;
705 struct resource cfg_res, self_res;
706 u32 decode;
707
708 hose->ops = &u3_ht_pci_ops;
709
710 /* Get base addresses from OF tree
711 */
712 if (of_address_to_resource(np, 0, &cfg_res) ||
713 of_address_to_resource(np, 1, &self_res)) {
714 printk(KERN_ERR "PCI: Failed to get U3/U4 HT resources !\n");
715 return;
716 }
717
718 /* Map external cfg space access into cfg_data and self registers
719 * into cfg_addr
720 */
721 hose->cfg_data = ioremap(cfg_res.start, 0x02000000);
722 hose->cfg_addr = ioremap(self_res.start, resource_size(&self_res));
723
724 /*
725 * /ht node doesn't expose a "ranges" property, we read the register
726 * that controls the decoding logic and use that for memory regions.
727 * The IO region is hard coded since it is fixed in HW as well.
728 */
729 hose->io_base_phys = 0xf4000000;
730 hose->pci_io_size = 0x00400000;
731 hose->io_resource.name = np->full_name;
732 hose->io_resource.start = 0;
733 hose->io_resource.end = 0x003fffff;
734 hose->io_resource.flags = IORESOURCE_IO;
735 hose->first_busno = 0;
736 hose->last_busno = 0xef;
737
738 /* Note: fix offset when cfg_addr becomes a void * */
739 decode = in_be32(hose->cfg_addr + 0x80);
740
741 DBG("PCI: Apple HT bridge decode register: 0x%08x\n", decode);
742
743 /* NOTE: The decode register setup is a bit weird... region
744 * 0xf8000000 for example is marked as enabled in there while it's
745 & actually the memory controller registers.
746 * That means that we are incorrectly attributing it to HT.
747 *
748 * In a similar vein, region 0xf4000000 is actually the HT IO space but
749 * also marked as enabled in here and 0xf9000000 is used by some other
750 * internal bits of the northbridge.
751 *
752 * Unfortunately, we can't just mask out those bit as we would end
753 * up with more regions than we can cope (linux can only cope with
754 * 3 memory regions for a PHB at this stage).
755 *
756 * So for now, we just do a little hack. We happen to -know- that
757 * Apple firmware doesn't assign things below 0xfa000000 for that
758 * bridge anyway so we mask out all bits we don't want.
759 */
760 decode &= 0x003fffff;
761
762 /* Now parse the resulting bits and build resources */
763 parse_region_decode(hose, decode);
764 }
765 #endif /* CONFIG_PPC64 */
766
767 /*
768 * We assume that if we have a G3 powermac, we have one bridge called
769 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
770 * if we have one or more bandit or chaos bridges, we don't have a MPC106.
771 */
772 static int __init pmac_add_bridge(struct device_node *dev)
773 {
774 int len;
775 struct pci_controller *hose;
776 struct resource rsrc;
777 char *disp_name;
778 const int *bus_range;
779 int primary = 1;
780
781 DBG("Adding PCI host bridge %pOF\n", dev);
782
783 /* Fetch host bridge registers address */
784 of_address_to_resource(dev, 0, &rsrc);
785
786 /* Get bus range if any */
787 bus_range = of_get_property(dev, "bus-range", &len);
788 if (bus_range == NULL || len < 2 * sizeof(int)) {
789 printk(KERN_WARNING "Can't get bus-range for %pOF, assume"
790 " bus 0\n", dev);
791 }
792
793 hose = pcibios_alloc_controller(dev);
794 if (!hose)
795 return -ENOMEM;
796 hose->first_busno = bus_range ? bus_range[0] : 0;
797 hose->last_busno = bus_range ? bus_range[1] : 0xff;
798 hose->controller_ops = pmac_pci_controller_ops;
799
800 disp_name = NULL;
801
802 /* 64 bits only bridges */
803 #ifdef CONFIG_PPC64
804 if (of_device_is_compatible(dev, "u3-agp")) {
805 setup_u3_agp(hose);
806 disp_name = "U3-AGP";
807 primary = 0;
808 } else if (of_device_is_compatible(dev, "u3-ht")) {
809 setup_u3_ht(hose);
810 disp_name = "U3-HT";
811 primary = 1;
812 } else if (of_device_is_compatible(dev, "u4-pcie")) {
813 setup_u4_pcie(hose);
814 disp_name = "U4-PCIE";
815 primary = 0;
816 }
817 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number:"
818 " %d->%d\n", disp_name, hose->first_busno, hose->last_busno);
819 #endif /* CONFIG_PPC64 */
820
821 /* 32 bits only bridges */
822 #ifdef CONFIG_PPC32
823 if (of_device_is_compatible(dev, "uni-north")) {
824 primary = setup_uninorth(hose, &rsrc);
825 disp_name = "UniNorth";
826 } else if (of_node_name_eq(dev, "pci")) {
827 /* XXX assume this is a mpc106 (grackle) */
828 setup_grackle(hose);
829 disp_name = "Grackle (MPC106)";
830 } else if (of_node_name_eq(dev, "bandit")) {
831 setup_bandit(hose, &rsrc);
832 disp_name = "Bandit";
833 } else if (of_node_name_eq(dev, "chaos")) {
834 setup_chaos(hose, &rsrc);
835 disp_name = "Chaos";
836 primary = 0;
837 }
838 printk(KERN_INFO "Found %s PCI host bridge at 0x%016llx. "
839 "Firmware bus number: %d->%d\n",
840 disp_name, (unsigned long long)rsrc.start, hose->first_busno,
841 hose->last_busno);
842 #endif /* CONFIG_PPC32 */
843
844 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
845 hose, hose->cfg_addr, hose->cfg_data);
846
847 /* Interpret the "ranges" property */
848 /* This also maps the I/O region and sets isa_io/mem_base */
849 pci_process_bridge_OF_ranges(hose, dev, primary);
850
851 /* Fixup "bus-range" OF property */
852 fixup_bus_range(dev);
853
854 /* create pci_dn's for DT nodes under this PHB */
855 if (IS_ENABLED(CONFIG_PPC64))
856 pci_devs_phb_init_dynamic(hose);
857
858 return 0;
859 }
860
861 void pmac_pci_irq_fixup(struct pci_dev *dev)
862 {
863 #ifdef CONFIG_PPC32
864 /* Fixup interrupt for the modem/ethernet combo controller.
865 * on machines with a second ohare chip.
866 * The number in the device tree (27) is bogus (correct for
867 * the ethernet-only board but not the combo ethernet/modem
868 * board). The real interrupt is 28 on the second controller
869 * -> 28+32 = 60.
870 */
871 if (has_second_ohare &&
872 dev->vendor == PCI_VENDOR_ID_DEC &&
873 dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS) {
874 dev->irq = irq_create_mapping(NULL, 60);
875 irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW);
876 }
877 #endif /* CONFIG_PPC32 */
878 }
879
880 #ifdef CONFIG_PPC64
881 static int pmac_pci_root_bridge_prepare(struct pci_host_bridge *bridge)
882 {
883 struct pci_controller *hose = pci_bus_to_host(bridge->bus);
884 struct device_node *np, *child;
885
886 if (hose != u3_agp)
887 return 0;
888
889 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
890 * assume there is no P2P bridge on the AGP bus, which should be a
891 * safe assumptions for now. We should do something better in the
892 * future though
893 */
894 np = hose->dn;
895 PCI_DN(np)->busno = 0xf0;
896 for_each_child_of_node(np, child)
897 PCI_DN(child)->busno = 0xf0;
898
899 return 0;
900 }
901 #endif /* CONFIG_PPC64 */
902
903 void __init pmac_pci_init(void)
904 {
905 struct device_node *np, *root;
906 struct device_node *ht __maybe_unused = NULL;
907
908 pci_set_flags(PCI_CAN_SKIP_ISA_ALIGN);
909
910 root = of_find_node_by_path("/");
911 if (root == NULL) {
912 printk(KERN_CRIT "pmac_pci_init: can't find root "
913 "of device tree\n");
914 return;
915 }
916 for_each_child_of_node(root, np) {
917 if (of_node_name_eq(np, "bandit")
918 || of_node_name_eq(np, "chaos")
919 || of_node_name_eq(np, "pci")) {
920 if (pmac_add_bridge(np) == 0)
921 of_node_get(np);
922 }
923 if (of_node_name_eq(np, "ht")) {
924 of_node_get(np);
925 ht = np;
926 }
927 }
928 of_node_put(root);
929
930 #ifdef CONFIG_PPC64
931 /* Probe HT last as it relies on the agp resources to be already
932 * setup
933 */
934 if (ht && pmac_add_bridge(ht) != 0)
935 of_node_put(ht);
936
937 ppc_md.pcibios_root_bridge_prepare = pmac_pci_root_bridge_prepare;
938 /* pmac_check_ht_link(); */
939
940 #else /* CONFIG_PPC64 */
941 init_p2pbridge();
942 init_second_ohare();
943 fixup_nec_usb2();
944
945 /* We are still having some issues with the Xserve G4, enabling
946 * some offset between bus number and domains for now when we
947 * assign all busses should help for now
948 */
949 if (pci_has_flag(PCI_REASSIGN_ALL_BUS))
950 pcibios_assign_bus_offset = 0x10;
951 #endif
952 }
953
954 #ifdef CONFIG_PPC32
955 static bool pmac_pci_enable_device_hook(struct pci_dev *dev)
956 {
957 struct device_node* node;
958 int updatecfg = 0;
959 int uninorth_child;
960
961 node = pci_device_to_OF_node(dev);
962
963 /* We don't want to enable USB controllers absent from the OF tree
964 * (iBook second controller)
965 */
966 if (dev->vendor == PCI_VENDOR_ID_APPLE
967 && dev->class == PCI_CLASS_SERIAL_USB_OHCI
968 && !node) {
969 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n",
970 pci_name(dev));
971 return false;
972 }
973
974 if (!node)
975 return true;
976
977 uninorth_child = node->parent &&
978 of_device_is_compatible(node->parent, "uni-north");
979
980 /* Firewire & GMAC were disabled after PCI probe, the driver is
981 * claiming them, we must re-enable them now.
982 */
983 if (uninorth_child && of_node_name_eq(node, "firewire") &&
984 (of_device_is_compatible(node, "pci106b,18") ||
985 of_device_is_compatible(node, "pci106b,30") ||
986 of_device_is_compatible(node, "pci11c1,5811"))) {
987 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1);
988 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1);
989 updatecfg = 1;
990 }
991 if (uninorth_child && of_node_name_eq(node, "ethernet") &&
992 of_device_is_compatible(node, "gmac")) {
993 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1);
994 updatecfg = 1;
995 }
996
997 /*
998 * Fixup various header fields on 32 bits. We don't do that on
999 * 64 bits as some of these have strange values behind the HT
1000 * bridge and we must not, for example, enable MWI or set the
1001 * cache line size on them.
1002 */
1003 if (updatecfg) {
1004 u16 cmd;
1005
1006 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1007 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
1008 | PCI_COMMAND_INVALIDATE;
1009 pci_write_config_word(dev, PCI_COMMAND, cmd);
1010 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16);
1011
1012 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
1013 L1_CACHE_BYTES >> 2);
1014 }
1015
1016 return true;
1017 }
1018
1019 static void pmac_pci_fixup_ohci(struct pci_dev *dev)
1020 {
1021 struct device_node *node = pci_device_to_OF_node(dev);
1022
1023 /* We don't want to assign resources to USB controllers
1024 * absent from the OF tree (iBook second controller)
1025 */
1026 if (dev->class == PCI_CLASS_SERIAL_USB_OHCI && !node)
1027 dev->resource[0].flags = 0;
1028 }
1029 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, PCI_ANY_ID, pmac_pci_fixup_ohci);
1030
1031 /* We power down some devices after they have been probed. They'll
1032 * be powered back on later on
1033 */
1034 void __init pmac_pcibios_after_init(void)
1035 {
1036 struct device_node* nd;
1037
1038 for_each_node_by_name(nd, "firewire") {
1039 if (nd->parent && (of_device_is_compatible(nd, "pci106b,18") ||
1040 of_device_is_compatible(nd, "pci106b,30") ||
1041 of_device_is_compatible(nd, "pci11c1,5811"))
1042 && of_device_is_compatible(nd->parent, "uni-north")) {
1043 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0);
1044 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0);
1045 }
1046 }
1047 for_each_node_by_name(nd, "ethernet") {
1048 if (nd->parent && of_device_is_compatible(nd, "gmac")
1049 && of_device_is_compatible(nd->parent, "uni-north"))
1050 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0);
1051 }
1052 }
1053
1054 static void pmac_pci_fixup_cardbus(struct pci_dev *dev)
1055 {
1056 if (!machine_is(powermac))
1057 return;
1058 /*
1059 * Fix the interrupt routing on the various cardbus bridges
1060 * used on powerbooks
1061 */
1062 if (dev->vendor != PCI_VENDOR_ID_TI)
1063 return;
1064 if (dev->device == PCI_DEVICE_ID_TI_1130 ||
1065 dev->device == PCI_DEVICE_ID_TI_1131) {
1066 u8 val;
1067 /* Enable PCI interrupt */
1068 if (pci_read_config_byte(dev, 0x91, &val) == 0)
1069 pci_write_config_byte(dev, 0x91, val | 0x30);
1070 /* Disable ISA interrupt mode */
1071 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1072 pci_write_config_byte(dev, 0x92, val & ~0x06);
1073 }
1074 if (dev->device == PCI_DEVICE_ID_TI_1210 ||
1075 dev->device == PCI_DEVICE_ID_TI_1211 ||
1076 dev->device == PCI_DEVICE_ID_TI_1410 ||
1077 dev->device == PCI_DEVICE_ID_TI_1510) {
1078 u8 val;
1079 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA
1080 signal out the MFUNC0 pin */
1081 if (pci_read_config_byte(dev, 0x8c, &val) == 0)
1082 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2);
1083 /* Disable ISA interrupt mode */
1084 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1085 pci_write_config_byte(dev, 0x92, val & ~0x06);
1086 }
1087 }
1088
1089 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus);
1090
1091 static void pmac_pci_fixup_pciata(struct pci_dev *dev)
1092 {
1093 u8 progif = 0;
1094
1095 /*
1096 * On PowerMacs, we try to switch any PCI ATA controller to
1097 * fully native mode
1098 */
1099 if (!machine_is(powermac))
1100 return;
1101
1102 /* Some controllers don't have the class IDE */
1103 if (dev->vendor == PCI_VENDOR_ID_PROMISE)
1104 switch(dev->device) {
1105 case PCI_DEVICE_ID_PROMISE_20246:
1106 case PCI_DEVICE_ID_PROMISE_20262:
1107 case PCI_DEVICE_ID_PROMISE_20263:
1108 case PCI_DEVICE_ID_PROMISE_20265:
1109 case PCI_DEVICE_ID_PROMISE_20267:
1110 case PCI_DEVICE_ID_PROMISE_20268:
1111 case PCI_DEVICE_ID_PROMISE_20269:
1112 case PCI_DEVICE_ID_PROMISE_20270:
1113 case PCI_DEVICE_ID_PROMISE_20271:
1114 case PCI_DEVICE_ID_PROMISE_20275:
1115 case PCI_DEVICE_ID_PROMISE_20276:
1116 case PCI_DEVICE_ID_PROMISE_20277:
1117 goto good;
1118 }
1119 /* Others, check PCI class */
1120 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
1121 return;
1122 good:
1123 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1124 if ((progif & 5) != 5) {
1125 printk(KERN_INFO "PCI: %s Forcing PCI IDE into native mode\n",
1126 pci_name(dev));
1127 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
1128 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
1129 (progif & 5) != 5)
1130 printk(KERN_ERR "Rewrite of PROGIF failed !\n");
1131 else {
1132 /* Clear IO BARs, they will be reassigned */
1133 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
1134 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
1135 pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, 0);
1136 pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, 0);
1137 }
1138 }
1139 }
1140 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata);
1141 #endif /* CONFIG_PPC32 */
1142
1143 /*
1144 * Disable second function on K2-SATA, it's broken
1145 * and disable IO BARs on first one
1146 */
1147 static void fixup_k2_sata(struct pci_dev* dev)
1148 {
1149 int i;
1150 u16 cmd;
1151
1152 if (PCI_FUNC(dev->devfn) > 0) {
1153 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1154 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1155 pci_write_config_word(dev, PCI_COMMAND, cmd);
1156 for (i = 0; i < 6; i++) {
1157 dev->resource[i].start = dev->resource[i].end = 0;
1158 dev->resource[i].flags = 0;
1159 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i,
1160 0);
1161 }
1162 } else {
1163 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1164 cmd &= ~PCI_COMMAND_IO;
1165 pci_write_config_word(dev, PCI_COMMAND, cmd);
1166 for (i = 0; i < 5; i++) {
1167 dev->resource[i].start = dev->resource[i].end = 0;
1168 dev->resource[i].flags = 0;
1169 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i,
1170 0);
1171 }
1172 }
1173 }
1174 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata);
1175
1176 /*
1177 * On U4 (aka CPC945) the PCIe root complex "P2P" bridge resource ranges aren't
1178 * configured by the firmware. The bridge itself seems to ignore them but it
1179 * causes problems with Linux which then re-assigns devices below the bridge,
1180 * thus changing addresses of those devices from what was in the device-tree,
1181 * which sucks when those are video cards using offb
1182 *
1183 * We could just mark it transparent but I prefer fixing up the resources to
1184 * properly show what's going on here, as I have some doubts about having them
1185 * badly configured potentially being an issue for DMA.
1186 *
1187 * We leave PIO alone, it seems to be fine
1188 *
1189 * Oh and there's another funny bug. The OF properties advertize the region
1190 * 0xf1000000..0xf1ffffff as being forwarded as memory space. But that's
1191 * actually not true, this region is the memory mapped config space. So we
1192 * also need to filter it out or we'll map things in the wrong place.
1193 */
1194 static void fixup_u4_pcie(struct pci_dev* dev)
1195 {
1196 struct pci_controller *host = pci_bus_to_host(dev->bus);
1197 struct resource *region = NULL;
1198 u32 reg;
1199 int i;
1200
1201 /* Only do that on PowerMac */
1202 if (!machine_is(powermac))
1203 return;
1204
1205 /* Find the largest MMIO region */
1206 for (i = 0; i < 3; i++) {
1207 struct resource *r = &host->mem_resources[i];
1208 if (!(r->flags & IORESOURCE_MEM))
1209 continue;
1210 /* Skip the 0xf0xxxxxx..f2xxxxxx regions, we know they
1211 * are reserved by HW for other things
1212 */
1213 if (r->start >= 0xf0000000 && r->start < 0xf3000000)
1214 continue;
1215 if (!region || resource_size(r) > resource_size(region))
1216 region = r;
1217 }
1218 /* Nothing found, bail */
1219 if (!region)
1220 return;
1221
1222 /* Print things out */
1223 printk(KERN_INFO "PCI: Fixup U4 PCIe bridge range: %pR\n", region);
1224
1225 /* Fixup bridge config space. We know it's a Mac, resource aren't
1226 * offset so let's just blast them as-is. We also know that they
1227 * fit in 32 bits
1228 */
1229 reg = ((region->start >> 16) & 0xfff0) | (region->end & 0xfff00000);
1230 pci_write_config_dword(dev, PCI_MEMORY_BASE, reg);
1231 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0);
1232 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
1233 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0);
1234 }
1235 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_U4_PCIE, fixup_u4_pcie);
1236
1237 #ifdef CONFIG_PPC64
1238 static int pmac_pci_probe_mode(struct pci_bus *bus)
1239 {
1240 struct device_node *node = pci_bus_to_OF_node(bus);
1241
1242 /* We need to use normal PCI probing for the AGP bus,
1243 * since the device for the AGP bridge isn't in the tree.
1244 * Same for the PCIe host on U4 and the HT host bridge.
1245 */
1246 if (bus->self == NULL && (of_device_is_compatible(node, "u3-agp") ||
1247 of_device_is_compatible(node, "u4-pcie") ||
1248 of_device_is_compatible(node, "u3-ht")))
1249 return PCI_PROBE_NORMAL;
1250 return PCI_PROBE_DEVTREE;
1251 }
1252 #endif /* CONFIG_PPC64 */
1253
1254 struct pci_controller_ops pmac_pci_controller_ops = {
1255 #ifdef CONFIG_PPC64
1256 .probe_mode = pmac_pci_probe_mode,
1257 #endif
1258 #ifdef CONFIG_PPC32
1259 .enable_device_hook = pmac_pci_enable_device_hook,
1260 #endif
1261 };
1262
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