1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * PowerNV setup code.
4 *
5 * Copyright 2011 IBM Corp.
6 */
7
8 #undef DEBUG
9
10 #include <linux/cpu.h>
11 #include <linux/errno.h>
12 #include <linux/sched.h>
13 #include <linux/kernel.h>
14 #include <linux/tty.h>
15 #include <linux/reboot.h>
16 #include <linux/init.h>
17 #include <linux/console.h>
18 #include <linux/delay.h>
19 #include <linux/irq.h>
20 #include <linux/seq_buf.h>
21 #include <linux/seq_file.h>
22 #include <linux/of.h>
23 #include <linux/of_fdt.h>
24 #include <linux/interrupt.h>
25 #include <linux/bug.h>
26 #include <linux/pci.h>
27 #include <linux/cpufreq.h>
28 #include <linux/memblock.h>
29
30 #include <asm/machdep.h>
31 #include <asm/firmware.h>
32 #include <asm/xics.h>
33 #include <asm/xive.h>
34 #include <asm/opal.h>
35 #include <asm/kexec.h>
36 #include <asm/smp.h>
37 #include <asm/tm.h>
38 #include <asm/setup.h>
39 #include <asm/security_features.h>
40
41 #include "powernv.h"
42
43
44 static bool __init fw_feature_is(const char *state, const char *name,
45 struct device_node *fw_features)
46 {
47 struct device_node *np;
48 bool rc = false;
49
50 np = of_get_child_by_name(fw_features, name);
51 if (np) {
52 rc = of_property_read_bool(np, state);
53 of_node_put(np);
54 }
55
56 return rc;
57 }
58
59 static void __init init_fw_feat_flags(struct device_node *np)
60 {
61 if (fw_feature_is("enabled", "inst-spec-barrier-ori31,31,0", np))
62 security_ftr_set(SEC_FTR_SPEC_BAR_ORI31);
63
64 if (fw_feature_is("enabled", "fw-bcctrl-serialized", np))
65 security_ftr_set(SEC_FTR_BCCTRL_SERIALISED);
66
67 if (fw_feature_is("enabled", "inst-l1d-flush-ori30,30,0", np))
68 security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30);
69
70 if (fw_feature_is("enabled", "inst-l1d-flush-trig2", np))
71 security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2);
72
73 if (fw_feature_is("enabled", "fw-l1d-thread-split", np))
74 security_ftr_set(SEC_FTR_L1D_THREAD_PRIV);
75
76 if (fw_feature_is("enabled", "fw-count-cache-disabled", np))
77 security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED);
78
79 if (fw_feature_is("enabled", "fw-count-cache-flush-bcctr2,0,0", np))
80 security_ftr_set(SEC_FTR_BCCTR_FLUSH_ASSIST);
81
82 if (fw_feature_is("enabled", "needs-count-cache-flush-on-context-switch", np))
83 security_ftr_set(SEC_FTR_FLUSH_COUNT_CACHE);
84
85 /*
86 * The features below are enabled by default, so we instead look to see
87 * if firmware has *disabled* them, and clear them if so.
88 */
89 if (fw_feature_is("disabled", "speculation-policy-favor-security", np))
90 security_ftr_clear(SEC_FTR_FAVOUR_SECURITY);
91
92 if (fw_feature_is("disabled", "needs-l1d-flush-msr-pr-0-to-1", np))
93 security_ftr_clear(SEC_FTR_L1D_FLUSH_PR);
94
95 if (fw_feature_is("disabled", "needs-l1d-flush-msr-hv-1-to-0", np))
96 security_ftr_clear(SEC_FTR_L1D_FLUSH_HV);
97
98 if (fw_feature_is("disabled", "needs-spec-barrier-for-bound-checks", np))
99 security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR);
100
101 if (fw_feature_is("enabled", "no-need-l1d-flush-msr-pr-1-to-0", np))
102 security_ftr_clear(SEC_FTR_L1D_FLUSH_ENTRY);
103
104 if (fw_feature_is("enabled", "no-need-l1d-flush-kernel-on-user-access", np))
105 security_ftr_clear(SEC_FTR_L1D_FLUSH_UACCESS);
106
107 if (fw_feature_is("enabled", "no-need-store-drain-on-priv-state-switch", np))
108 security_ftr_clear(SEC_FTR_STF_BARRIER);
109 }
110
111 static void __init pnv_setup_security_mitigations(void)
112 {
113 struct device_node *np, *fw_features;
114 enum l1d_flush_type type;
115 bool enable;
116
117 /* Default to fallback in case fw-features are not available */
118 type = L1D_FLUSH_FALLBACK;
119
120 np = of_find_node_by_name(NULL, "ibm,opal");
121 fw_features = of_get_child_by_name(np, "fw-features");
122 of_node_put(np);
123
124 if (fw_features) {
125 init_fw_feat_flags(fw_features);
126 of_node_put(fw_features);
127
128 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2))
129 type = L1D_FLUSH_MTTRIG;
130
131 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30))
132 type = L1D_FLUSH_ORI;
133 }
134
135 /*
136 * The issues addressed by the entry and uaccess flush don't affect P7
137 * or P8, so on bare metal disable them explicitly in case firmware does
138 * not include the features to disable them. POWER9 and newer processors
139 * should have the appropriate firmware flags.
140 */
141 if (pvr_version_is(PVR_POWER7) || pvr_version_is(PVR_POWER7p) ||
142 pvr_version_is(PVR_POWER8E) || pvr_version_is(PVR_POWER8NVL) ||
143 pvr_version_is(PVR_POWER8)) {
144 security_ftr_clear(SEC_FTR_L1D_FLUSH_ENTRY);
145 security_ftr_clear(SEC_FTR_L1D_FLUSH_UACCESS);
146 }
147
148 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \
149 (security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR) || \
150 security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV));
151
152 setup_rfi_flush(type, enable);
153 setup_count_cache_flush();
154
155 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
156 security_ftr_enabled(SEC_FTR_L1D_FLUSH_ENTRY);
157 setup_entry_flush(enable);
158
159 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
160 security_ftr_enabled(SEC_FTR_L1D_FLUSH_UACCESS);
161 setup_uaccess_flush(enable);
162
163 setup_stf_barrier();
164 }
165
166 static void __init pnv_check_guarded_cores(void)
167 {
168 struct device_node *dn;
169 int bad_count = 0;
170
171 for_each_node_by_type(dn, "cpu") {
172 if (of_property_match_string(dn, "status", "bad") >= 0)
173 bad_count++;
174 }
175
176 if (bad_count) {
177 printk(" _ _______________\n");
178 pr_cont(" | | / \\\n");
179 pr_cont(" | | | WARNING! |\n");
180 pr_cont(" | | | |\n");
181 pr_cont(" | | | It looks like |\n");
182 pr_cont(" |_| | you have %*d |\n", 3, bad_count);
183 pr_cont(" _ | guarded cores |\n");
184 pr_cont(" (_) \\_______________/\n");
185 }
186 }
187
188 static void __init pnv_setup_arch(void)
189 {
190 set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT);
191
192 pnv_setup_security_mitigations();
193
194 /* Initialize SMP */
195 pnv_smp_init();
196
197 /* Setup RTC and NVRAM callbacks */
198 if (firmware_has_feature(FW_FEATURE_OPAL))
199 opal_nvram_init();
200
201 /* Enable NAP mode */
202 powersave_nap = 1;
203
204 pnv_check_guarded_cores();
205
206 /* XXX PMCS */
207
208 pnv_rng_init();
209 }
210
211 static void __init pnv_add_hw_description(void)
212 {
213 struct device_node *dn;
214 const char *s;
215
216 dn = of_find_node_by_path("/ibm,opal/firmware");
217 if (!dn)
218 return;
219
220 if (of_property_read_string(dn, "version", &s) == 0 ||
221 of_property_read_string(dn, "git-id", &s) == 0)
222 seq_buf_printf(&ppc_hw_desc, "opal:%s ", s);
223
224 if (of_property_read_string(dn, "mi-version", &s) == 0)
225 seq_buf_printf(&ppc_hw_desc, "mi:%s ", s);
226
227 of_node_put(dn);
228 }
229
230 static void __init pnv_init(void)
231 {
232 pnv_add_hw_description();
233
234 /*
235 * Initialize the LPC bus now so that legacy serial
236 * ports can be found on it
237 */
238 opal_lpc_init();
239
240 #ifdef CONFIG_HVC_OPAL
241 if (firmware_has_feature(FW_FEATURE_OPAL))
242 hvc_opal_init_early();
243 else
244 #endif
245 add_preferred_console("hvc", 0, NULL);
246
247 #ifdef CONFIG_PPC_64S_HASH_MMU
248 if (!radix_enabled()) {
249 size_t size = sizeof(struct slb_entry) * mmu_slb_size;
250 int i;
251
252 /* Allocate per cpu area to save old slb contents during MCE */
253 for_each_possible_cpu(i) {
254 paca_ptrs[i]->mce_faulty_slbs =
255 memblock_alloc_node(size,
256 __alignof__(struct slb_entry),
257 cpu_to_node(i));
258 }
259 }
260 #endif
261 }
262
263 static void __init pnv_init_IRQ(void)
264 {
265 /* Try using a XIVE if available, otherwise use a XICS */
266 if (!xive_native_init())
267 xics_init();
268
269 WARN_ON(!ppc_md.get_irq);
270 }
271
272 static void pnv_show_cpuinfo(struct seq_file *m)
273 {
274 struct device_node *root;
275 const char *model = "";
276
277 root = of_find_node_by_path("/");
278 if (root)
279 model = of_get_property(root, "model", NULL);
280 seq_printf(m, "machine\t\t: PowerNV %s\n", model);
281 if (firmware_has_feature(FW_FEATURE_OPAL))
282 seq_printf(m, "firmware\t: OPAL\n");
283 else
284 seq_printf(m, "firmware\t: BML\n");
285 of_node_put(root);
286 if (radix_enabled())
287 seq_printf(m, "MMU\t\t: Radix\n");
288 else
289 seq_printf(m, "MMU\t\t: Hash\n");
290 }
291
292 static void pnv_prepare_going_down(void)
293 {
294 /*
295 * Disable all notifiers from OPAL, we can't
296 * service interrupts anymore anyway
297 */
298 opal_event_shutdown();
299
300 /* Print flash update message if one is scheduled. */
301 opal_flash_update_print_message();
302
303 smp_send_stop();
304
305 hard_irq_disable();
306 }
307
308 static void __noreturn pnv_restart(char *cmd)
309 {
310 long rc;
311
312 pnv_prepare_going_down();
313
314 do {
315 if (!cmd || !strlen(cmd))
316 rc = opal_cec_reboot();
317 else if (strcmp(cmd, "full") == 0)
318 rc = opal_cec_reboot2(OPAL_REBOOT_FULL_IPL, NULL);
319 else if (strcmp(cmd, "mpipl") == 0)
320 rc = opal_cec_reboot2(OPAL_REBOOT_MPIPL, NULL);
321 else if (strcmp(cmd, "error") == 0)
322 rc = opal_cec_reboot2(OPAL_REBOOT_PLATFORM_ERROR, NULL);
323 else if (strcmp(cmd, "fast") == 0)
324 rc = opal_cec_reboot2(OPAL_REBOOT_FAST, NULL);
325 else
326 rc = OPAL_UNSUPPORTED;
327
328 if (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
329 /* Opal is busy wait for some time and retry */
330 opal_poll_events(NULL);
331 mdelay(10);
332
333 } else if (cmd && rc) {
334 /* Unknown error while issuing reboot */
335 if (rc == OPAL_UNSUPPORTED)
336 pr_err("Unsupported '%s' reboot.\n", cmd);
337 else
338 pr_err("Unable to issue '%s' reboot. Err=%ld\n",
339 cmd, rc);
340 pr_info("Forcing a cec-reboot\n");
341 cmd = NULL;
342 rc = OPAL_BUSY;
343
344 } else if (rc != OPAL_SUCCESS) {
345 /* Unknown error while issuing cec-reboot */
346 pr_err("Unable to reboot. Err=%ld\n", rc);
347 }
348
349 } while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT);
350
351 for (;;)
352 opal_poll_events(NULL);
353 }
354
355 static void __noreturn pnv_power_off(void)
356 {
357 long rc = OPAL_BUSY;
358
359 pnv_prepare_going_down();
360
361 while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
362 rc = opal_cec_power_down(0);
363 if (rc == OPAL_BUSY_EVENT)
364 opal_poll_events(NULL);
365 else
366 mdelay(10);
367 }
368 for (;;)
369 opal_poll_events(NULL);
370 }
371
372 static void __noreturn pnv_halt(void)
373 {
374 pnv_power_off();
375 }
376
377 static void pnv_progress(char *s, unsigned short hex)
378 {
379 }
380
381 static void pnv_shutdown(void)
382 {
383 /* Let the PCI code clear up IODA tables */
384 pnv_pci_shutdown();
385
386 /*
387 * Stop OPAL activity: Unregister all OPAL interrupts so they
388 * don't fire up while we kexec and make sure all potentially
389 * DMA'ing ops are complete (such as dump retrieval).
390 */
391 opal_shutdown();
392 }
393
394 #ifdef CONFIG_KEXEC_CORE
395 static void pnv_kexec_wait_secondaries_down(void)
396 {
397 int my_cpu, i, notified = -1;
398
399 my_cpu = get_cpu();
400
401 for_each_online_cpu(i) {
402 uint8_t status;
403 int64_t rc, timeout = 1000;
404
405 if (i == my_cpu)
406 continue;
407
408 for (;;) {
409 rc = opal_query_cpu_status(get_hard_smp_processor_id(i),
410 &status);
411 if (rc != OPAL_SUCCESS || status != OPAL_THREAD_STARTED)
412 break;
413 barrier();
414 if (i != notified) {
415 printk(KERN_INFO "kexec: waiting for cpu %d "
416 "(physical %d) to enter OPAL\n",
417 i, paca_ptrs[i]->hw_cpu_id);
418 notified = i;
419 }
420
421 /*
422 * On crash secondaries might be unreachable or hung,
423 * so timeout if we've waited too long
424 * */
425 mdelay(1);
426 if (timeout-- == 0) {
427 printk(KERN_ERR "kexec: timed out waiting for "
428 "cpu %d (physical %d) to enter OPAL\n",
429 i, paca_ptrs[i]->hw_cpu_id);
430 break;
431 }
432 }
433 }
434 }
435
436 static void pnv_kexec_cpu_down(int crash_shutdown, int secondary)
437 {
438 u64 reinit_flags;
439
440 if (xive_enabled())
441 xive_teardown_cpu();
442 else
443 xics_kexec_teardown_cpu(secondary);
444
445 /* On OPAL, we return all CPUs to firmware */
446 if (!firmware_has_feature(FW_FEATURE_OPAL))
447 return;
448
449 if (secondary) {
450 /* Return secondary CPUs to firmware on OPAL v3 */
451 mb();
452 get_paca()->kexec_state = KEXEC_STATE_REAL_MODE;
453 mb();
454
455 /* Return the CPU to OPAL */
456 opal_return_cpu();
457 } else {
458 /* Primary waits for the secondaries to have reached OPAL */
459 pnv_kexec_wait_secondaries_down();
460
461 /* Switch XIVE back to emulation mode */
462 if (xive_enabled())
463 xive_shutdown();
464
465 /*
466 * We might be running as little-endian - now that interrupts
467 * are disabled, reset the HILE bit to big-endian so we don't
468 * take interrupts in the wrong endian later
469 *
470 * We reinit to enable both radix and hash on P9 to ensure
471 * the mode used by the next kernel is always supported.
472 */
473 reinit_flags = OPAL_REINIT_CPUS_HILE_BE;
474 if (cpu_has_feature(CPU_FTR_ARCH_300))
475 reinit_flags |= OPAL_REINIT_CPUS_MMU_RADIX |
476 OPAL_REINIT_CPUS_MMU_HASH;
477 opal_reinit_cpus(reinit_flags);
478 }
479 }
480 #endif /* CONFIG_KEXEC_CORE */
481
482 #ifdef CONFIG_MEMORY_HOTPLUG
483 static unsigned long pnv_memory_block_size(void)
484 {
485 return memory_block_size;
486 }
487 #endif
488
489 static void __init pnv_setup_machdep_opal(void)
490 {
491 ppc_md.get_boot_time = opal_get_boot_time;
492 ppc_md.restart = pnv_restart;
493 pm_power_off = pnv_power_off;
494 ppc_md.halt = pnv_halt;
495 /* ppc_md.system_reset_exception gets filled in by pnv_smp_init() */
496 ppc_md.machine_check_exception = opal_machine_check;
497 ppc_md.mce_check_early_recovery = opal_mce_check_early_recovery;
498 if (opal_check_token(OPAL_HANDLE_HMI2))
499 ppc_md.hmi_exception_early = opal_hmi_exception_early2;
500 else
501 ppc_md.hmi_exception_early = opal_hmi_exception_early;
502 ppc_md.handle_hmi_exception = opal_handle_hmi_exception;
503 }
504
505 static int __init pnv_probe(void)
506 {
507 if (firmware_has_feature(FW_FEATURE_OPAL))
508 pnv_setup_machdep_opal();
509
510 pr_debug("PowerNV detected !\n");
511
512 pnv_init();
513
514 return 1;
515 }
516
517 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
518 void __init pnv_tm_init(void)
519 {
520 if (!firmware_has_feature(FW_FEATURE_OPAL) ||
521 !pvr_version_is(PVR_POWER9) ||
522 early_cpu_has_feature(CPU_FTR_TM))
523 return;
524
525 if (opal_reinit_cpus(OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED) != OPAL_SUCCESS)
526 return;
527
528 pr_info("Enabling TM (Transactional Memory) with Suspend Disabled\n");
529 cur_cpu_spec->cpu_features |= CPU_FTR_TM;
530 /* Make sure "normal" HTM is off (it should be) */
531 cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_HTM;
532 /* Turn on no suspend mode, and HTM no SC */
533 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NO_SUSPEND | \
534 PPC_FEATURE2_HTM_NOSC;
535 tm_suspend_disabled = true;
536 }
537 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
538
539 /*
540 * Returns the cpu frequency for 'cpu' in Hz. This is used by
541 * /proc/cpuinfo
542 */
543 static unsigned long pnv_get_proc_freq(unsigned int cpu)
544 {
545 unsigned long ret_freq;
546
547 ret_freq = cpufreq_get(cpu) * 1000ul;
548
549 /*
550 * If the backend cpufreq driver does not exist,
551 * then fallback to old way of reporting the clockrate.
552 */
553 if (!ret_freq)
554 ret_freq = ppc_proc_freq;
555 return ret_freq;
556 }
557
558 static long pnv_machine_check_early(struct pt_regs *regs)
559 {
560 long handled = 0;
561
562 if (cur_cpu_spec && cur_cpu_spec->machine_check_early)
563 handled = cur_cpu_spec->machine_check_early(regs);
564
565 return handled;
566 }
567
568 define_machine(powernv) {
569 .name = "PowerNV",
570 .compatible = "ibm,powernv",
571 .probe = pnv_probe,
572 .setup_arch = pnv_setup_arch,
573 .init_IRQ = pnv_init_IRQ,
574 .show_cpuinfo = pnv_show_cpuinfo,
575 .get_proc_freq = pnv_get_proc_freq,
576 .discover_phbs = pnv_pci_init,
577 .progress = pnv_progress,
578 .machine_shutdown = pnv_shutdown,
579 .power_save = NULL,
580 .machine_check_early = pnv_machine_check_early,
581 #ifdef CONFIG_KEXEC_CORE
582 .kexec_cpu_down = pnv_kexec_cpu_down,
583 #endif
584 #ifdef CONFIG_MEMORY_HOTPLUG
585 .memory_block_size = pnv_memory_block_size,
586 #endif
587 };
588
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