1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2022 Microchip Technology Inc */
3
4 /dts-v1/;
5
6 #include "mpfs.dtsi"
7 #include "mpfs-sev-kit-fabric.dtsi"
8
9 / {
10 #address-cells = <2>;
11 #size-cells = <2>;
12 model = "Microchip PolarFire-SoC SEV Kit";
13 compatible = "microchip,mpfs-sev-kit", "microchip,mpfs";
14
15 aliases {
16 ethernet0 = &mac1;
17 serial0 = &mmuart0;
18 serial1 = &mmuart1;
19 serial2 = &mmuart2;
20 serial3 = &mmuart3;
21 serial4 = &mmuart4;
22 };
23
24 chosen {
25 stdout-path = "serial1:115200n8";
26 };
27
28 reserved-memory {
29 #address-cells = <2>;
30 #size-cells = <2>;
31 ranges;
32
33 fabricbuf0ddrc: buffer@80000000 {
34 compatible = "shared-dma-pool";
35 reg = <0x0 0x80000000 0x0 0x2000000>;
36 };
37
38 fabricbuf1ddrnc: buffer@c4000000 {
39 compatible = "shared-dma-pool";
40 reg = <0x0 0xc4000000 0x0 0x4000000>;
41 };
42
43 fabricbuf2ddrncwcb: buffer@d4000000 {
44 compatible = "shared-dma-pool";
45 reg = <0x0 0xd4000000 0x0 0x4000000>;
46 };
47 };
48
49 ddrc_cache: memory@1000000000 {
50 device_type = "memory";
51 reg = <0x10 0x0 0x0 0x76000000>;
52 };
53 };
54
55 &i2c0 {
56 status = "okay";
57 };
58
59 &gpio2 {
60 interrupts = <53>, <53>, <53>, <53>,
61 <53>, <53>, <53>, <53>,
62 <53>, <53>, <53>, <53>,
63 <53>, <53>, <53>, <53>,
64 <53>, <53>, <53>, <53>,
65 <53>, <53>, <53>, <53>,
66 <53>, <53>, <53>, <53>,
67 <53>, <53>, <53>, <53>;
68 status = "okay";
69 };
70
71 &mac0 {
72 status = "okay";
73 phy-mode = "sgmii";
74 phy-handle = <&phy0>;
75 phy1: ethernet-phy@9 {
76 reg = <9>;
77 };
78 phy0: ethernet-phy@8 {
79 reg = <8>;
80 };
81 };
82
83 &mac1 {
84 status = "okay";
85 phy-mode = "sgmii";
86 phy-handle = <&phy1>;
87 };
88
89 &mbox {
90 status = "okay";
91 };
92
93 &mmc {
94 status = "okay";
95 bus-width = <4>;
96 disable-wp;
97 cap-sd-highspeed;
98 cap-mmc-highspeed;
99 mmc-ddr-1_8v;
100 mmc-hs200-1_8v;
101 sd-uhs-sdr12;
102 sd-uhs-sdr25;
103 sd-uhs-sdr50;
104 sd-uhs-sdr104;
105 };
106
107 &mmuart1 {
108 status = "okay";
109 };
110
111 &mmuart2 {
112 status = "okay";
113 };
114
115 &mmuart3 {
116 status = "okay";
117 };
118
119 &mmuart4 {
120 status = "okay";
121 };
122
123 &refclk {
124 clock-frequency = <125000000>;
125 };
126
127 &rtc {
128 status = "okay";
129 };
130
131 &syscontroller {
132 status = "okay";
133 };
134
135 &usb {
136 status = "okay";
137 dr_mode = "otg";
138 };
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