1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /*
3 * Device Tree Source for the RZ/Five SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8 #include <dt-bindings/interrupt-controller/irq.h>
9
10 #define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
11
12 #include <arm64/renesas/r9a07g043.dtsi>
13
14 / {
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <12000000>;
19
20 cpu0: cpu@0 {
21 compatible = "andestech,ax45mp", "riscv";
22 device_type = "cpu";
23 #cooling-cells = <2>;
24 reg = <0x0>;
25 status = "okay";
26 riscv,isa = "rv64imafdc";
27 riscv,isa-base = "rv64i";
28 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
29 "zicntr", "zicsr", "zifencei",
30 "zihpm", "xandespmu";
31 mmu-type = "riscv,sv39";
32 i-cache-size = <0x8000>;
33 i-cache-line-size = <0x40>;
34 d-cache-size = <0x8000>;
35 d-cache-line-size = <0x40>;
36 next-level-cache = <&l2cache>;
37 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
38 operating-points-v2 = <&cluster0_opp>;
39
40 cpu0_intc: interrupt-controller {
41 #interrupt-cells = <1>;
42 compatible = "andestech,cpu-intc", "riscv,cpu-intc";
43 interrupt-controller;
44 };
45 };
46 };
47 };
48
49 &pinctrl {
50 gpio-ranges = <&pinctrl 0 0 232>;
51 };
52
53 &soc {
54 dma-noncoherent;
55 interrupt-parent = <&plic>;
56
57 irqc: interrupt-controller@110a0000 {
58 compatible = "renesas,r9a07g043f-irqc";
59 reg = <0 0x110a0000 0 0x20000>;
60 #interrupt-cells = <2>;
61 #address-cells = <0>;
62 interrupt-controller;
63 interrupts = <32 IRQ_TYPE_LEVEL_HIGH>,
64 <33 IRQ_TYPE_LEVEL_HIGH>,
65 <34 IRQ_TYPE_LEVEL_HIGH>,
66 <35 IRQ_TYPE_LEVEL_HIGH>,
67 <36 IRQ_TYPE_LEVEL_HIGH>,
68 <37 IRQ_TYPE_LEVEL_HIGH>,
69 <38 IRQ_TYPE_LEVEL_HIGH>,
70 <39 IRQ_TYPE_LEVEL_HIGH>,
71 <40 IRQ_TYPE_LEVEL_HIGH>,
72 <476 IRQ_TYPE_LEVEL_HIGH>,
73 <477 IRQ_TYPE_LEVEL_HIGH>,
74 <478 IRQ_TYPE_LEVEL_HIGH>,
75 <479 IRQ_TYPE_LEVEL_HIGH>,
76 <480 IRQ_TYPE_LEVEL_HIGH>,
77 <481 IRQ_TYPE_LEVEL_HIGH>,
78 <482 IRQ_TYPE_LEVEL_HIGH>,
79 <483 IRQ_TYPE_LEVEL_HIGH>,
80 <484 IRQ_TYPE_LEVEL_HIGH>,
81 <485 IRQ_TYPE_LEVEL_HIGH>,
82 <486 IRQ_TYPE_LEVEL_HIGH>,
83 <487 IRQ_TYPE_LEVEL_HIGH>,
84 <488 IRQ_TYPE_LEVEL_HIGH>,
85 <489 IRQ_TYPE_LEVEL_HIGH>,
86 <490 IRQ_TYPE_LEVEL_HIGH>,
87 <491 IRQ_TYPE_LEVEL_HIGH>,
88 <492 IRQ_TYPE_LEVEL_HIGH>,
89 <493 IRQ_TYPE_LEVEL_HIGH>,
90 <494 IRQ_TYPE_LEVEL_HIGH>,
91 <495 IRQ_TYPE_LEVEL_HIGH>,
92 <496 IRQ_TYPE_LEVEL_HIGH>,
93 <497 IRQ_TYPE_LEVEL_HIGH>,
94 <498 IRQ_TYPE_LEVEL_HIGH>,
95 <499 IRQ_TYPE_LEVEL_HIGH>,
96 <500 IRQ_TYPE_LEVEL_HIGH>,
97 <501 IRQ_TYPE_LEVEL_HIGH>,
98 <502 IRQ_TYPE_LEVEL_HIGH>,
99 <503 IRQ_TYPE_LEVEL_HIGH>,
100 <504 IRQ_TYPE_LEVEL_HIGH>,
101 <505 IRQ_TYPE_LEVEL_HIGH>,
102 <506 IRQ_TYPE_LEVEL_HIGH>,
103 <507 IRQ_TYPE_LEVEL_HIGH>,
104 <57 IRQ_TYPE_LEVEL_HIGH>,
105 <66 IRQ_TYPE_EDGE_RISING>,
106 <67 IRQ_TYPE_EDGE_RISING>,
107 <68 IRQ_TYPE_EDGE_RISING>,
108 <69 IRQ_TYPE_EDGE_RISING>,
109 <70 IRQ_TYPE_EDGE_RISING>,
110 <71 IRQ_TYPE_EDGE_RISING>;
111 interrupt-names = "nmi",
112 "irq0", "irq1", "irq2", "irq3",
113 "irq4", "irq5", "irq6", "irq7",
114 "tint0", "tint1", "tint2", "tint3",
115 "tint4", "tint5", "tint6", "tint7",
116 "tint8", "tint9", "tint10", "tint11",
117 "tint12", "tint13", "tint14", "tint15",
118 "tint16", "tint17", "tint18", "tint19",
119 "tint20", "tint21", "tint22", "tint23",
120 "tint24", "tint25", "tint26", "tint27",
121 "tint28", "tint29", "tint30", "tint31",
122 "bus-err", "ec7tie1-0", "ec7tie2-0",
123 "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
124 "ec7tiovf-1";
125 clocks = <&cpg CPG_MOD R9A07G043_IAX45_CLK>,
126 <&cpg CPG_MOD R9A07G043_IAX45_PCLK>;
127 clock-names = "clk", "pclk";
128 power-domains = <&cpg>;
129 resets = <&cpg R9A07G043_IAX45_RESETN>;
130 };
131
132 plic: interrupt-controller@12c00000 {
133 compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
134 #interrupt-cells = <2>;
135 #address-cells = <0>;
136 riscv,ndev = <511>;
137 interrupt-controller;
138 reg = <0x0 0x12c00000 0 0x400000>;
139 clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
140 power-domains = <&cpg>;
141 resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
142 interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
143 };
144
145 l2cache: cache-controller@13400000 {
146 compatible = "andestech,ax45mp-cache", "cache";
147 reg = <0x0 0x13400000 0x0 0x100000>;
148 interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
149 cache-size = <0x40000>;
150 cache-line-size = <64>;
151 cache-sets = <1024>;
152 cache-unified;
153 cache-level = <2>;
154 };
155 };
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