1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3 * Copyright (C) 2024 Henry Bell <dmoo_dv@protonmail.com>
4 */
5
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
8
9 / {
10 model = "Pine64 Star64";
11 compatible = "pine64,star64", "starfive,jh7110";
12 aliases {
13 ethernet1 = &gmac1;
14 };
15 };
16
17 &gmac0 {
18 starfive,tx-use-rgmii-clk;
19 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
20 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
21 };
22
23 &gmac1 {
24 phy-handle = <&phy1>;
25 phy-mode = "rgmii-id";
26 starfive,tx-use-rgmii-clk;
27 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
28 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
29 status = "okay";
30
31 mdio {
32 #address-cells = <1>;
33 #size-cells = <0>;
34 compatible = "snps,dwmac-mdio";
35
36 phy1: ethernet-phy@1 {
37 reg = <1>;
38 };
39 };
40 };
41
42 &pcie1 {
43 status = "okay";
44 };
45
46 &phy0 {
47 rx-internal-delay-ps = <1500>;
48 motorcomm,rx-clk-drv-microamp = <2910>;
49 motorcomm,rx-data-drv-microamp = <2910>;
50 motorcomm,tx-clk-adj-enabled;
51 motorcomm,tx-clk-10-inverted;
52 motorcomm,tx-clk-100-inverted;
53 motorcomm,tx-clk-1000-inverted;
54 };
55
56 &phy1 {
57 rx-internal-delay-ps = <0>;
58 tx-internal-delay-ps = <300>;
59 motorcomm,rx-clk-drv-microamp = <2910>;
60 motorcomm,rx-data-drv-microamp = <2910>;
61 motorcomm,tx-clk-adj-enabled;
62 motorcomm,tx-clk-10-inverted;
63 motorcomm,tx-clk-100-inverted;
64 };
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