1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
5 */
6
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
12
13 / {
14 compatible = "starfive,jh7110";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus: cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 S7_0: cpu@0 {
23 compatible = "sifive,s7", "riscv";
24 reg = <0>;
25 device_type = "cpu";
26 i-cache-block-size = <64>;
27 i-cache-sets = <64>;
28 i-cache-size = <16384>;
29 next-level-cache = <&ccache>;
30 riscv,isa = "rv64imac_zba_zbb";
31 riscv,isa-base = "rv64i";
32 riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr",
33 "zifencei", "zihpm";
34 status = "disabled";
35
36 cpu0_intc: interrupt-controller {
37 compatible = "riscv,cpu-intc";
38 interrupt-controller;
39 #interrupt-cells = <1>;
40 };
41 };
42
43 U74_1: cpu@1 {
44 compatible = "sifive,u74-mc", "riscv";
45 reg = <1>;
46 d-cache-block-size = <64>;
47 d-cache-sets = <64>;
48 d-cache-size = <32768>;
49 d-tlb-sets = <1>;
50 d-tlb-size = <40>;
51 device_type = "cpu";
52 i-cache-block-size = <64>;
53 i-cache-sets = <64>;
54 i-cache-size = <32768>;
55 i-tlb-sets = <1>;
56 i-tlb-size = <40>;
57 mmu-type = "riscv,sv39";
58 next-level-cache = <&ccache>;
59 riscv,isa = "rv64imafdc_zba_zbb";
60 riscv,isa-base = "rv64i";
61 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
62 "zicsr", "zifencei", "zihpm";
63 tlb-split;
64 operating-points-v2 = <&cpu_opp>;
65 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
66 clock-names = "cpu";
67 #cooling-cells = <2>;
68
69 cpu1_intc: interrupt-controller {
70 compatible = "riscv,cpu-intc";
71 interrupt-controller;
72 #interrupt-cells = <1>;
73 };
74 };
75
76 U74_2: cpu@2 {
77 compatible = "sifive,u74-mc", "riscv";
78 reg = <2>;
79 d-cache-block-size = <64>;
80 d-cache-sets = <64>;
81 d-cache-size = <32768>;
82 d-tlb-sets = <1>;
83 d-tlb-size = <40>;
84 device_type = "cpu";
85 i-cache-block-size = <64>;
86 i-cache-sets = <64>;
87 i-cache-size = <32768>;
88 i-tlb-sets = <1>;
89 i-tlb-size = <40>;
90 mmu-type = "riscv,sv39";
91 next-level-cache = <&ccache>;
92 riscv,isa = "rv64imafdc_zba_zbb";
93 riscv,isa-base = "rv64i";
94 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
95 "zicsr", "zifencei", "zihpm";
96 tlb-split;
97 operating-points-v2 = <&cpu_opp>;
98 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
99 clock-names = "cpu";
100 #cooling-cells = <2>;
101
102 cpu2_intc: interrupt-controller {
103 compatible = "riscv,cpu-intc";
104 interrupt-controller;
105 #interrupt-cells = <1>;
106 };
107 };
108
109 U74_3: cpu@3 {
110 compatible = "sifive,u74-mc", "riscv";
111 reg = <3>;
112 d-cache-block-size = <64>;
113 d-cache-sets = <64>;
114 d-cache-size = <32768>;
115 d-tlb-sets = <1>;
116 d-tlb-size = <40>;
117 device_type = "cpu";
118 i-cache-block-size = <64>;
119 i-cache-sets = <64>;
120 i-cache-size = <32768>;
121 i-tlb-sets = <1>;
122 i-tlb-size = <40>;
123 mmu-type = "riscv,sv39";
124 next-level-cache = <&ccache>;
125 riscv,isa = "rv64imafdc_zba_zbb";
126 riscv,isa-base = "rv64i";
127 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
128 "zicsr", "zifencei", "zihpm";
129 tlb-split;
130 operating-points-v2 = <&cpu_opp>;
131 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
132 clock-names = "cpu";
133 #cooling-cells = <2>;
134
135 cpu3_intc: interrupt-controller {
136 compatible = "riscv,cpu-intc";
137 interrupt-controller;
138 #interrupt-cells = <1>;
139 };
140 };
141
142 U74_4: cpu@4 {
143 compatible = "sifive,u74-mc", "riscv";
144 reg = <4>;
145 d-cache-block-size = <64>;
146 d-cache-sets = <64>;
147 d-cache-size = <32768>;
148 d-tlb-sets = <1>;
149 d-tlb-size = <40>;
150 device_type = "cpu";
151 i-cache-block-size = <64>;
152 i-cache-sets = <64>;
153 i-cache-size = <32768>;
154 i-tlb-sets = <1>;
155 i-tlb-size = <40>;
156 mmu-type = "riscv,sv39";
157 next-level-cache = <&ccache>;
158 riscv,isa = "rv64imafdc_zba_zbb";
159 riscv,isa-base = "rv64i";
160 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
161 "zicsr", "zifencei", "zihpm";
162 tlb-split;
163 operating-points-v2 = <&cpu_opp>;
164 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
165 clock-names = "cpu";
166 #cooling-cells = <2>;
167
168 cpu4_intc: interrupt-controller {
169 compatible = "riscv,cpu-intc";
170 interrupt-controller;
171 #interrupt-cells = <1>;
172 };
173 };
174
175 cpu-map {
176 cluster0 {
177 core0 {
178 cpu = <&S7_0>;
179 };
180
181 core1 {
182 cpu = <&U74_1>;
183 };
184
185 core2 {
186 cpu = <&U74_2>;
187 };
188
189 core3 {
190 cpu = <&U74_3>;
191 };
192
193 core4 {
194 cpu = <&U74_4>;
195 };
196 };
197 };
198 };
199
200 cpu_opp: opp-table-0 {
201 compatible = "operating-points-v2";
202 opp-shared;
203 opp-375000000 {
204 opp-hz = /bits/ 64 <375000000>;
205 opp-microvolt = <800000>;
206 };
207 opp-500000000 {
208 opp-hz = /bits/ 64 <500000000>;
209 opp-microvolt = <800000>;
210 };
211 opp-750000000 {
212 opp-hz = /bits/ 64 <750000000>;
213 opp-microvolt = <800000>;
214 };
215 opp-1500000000 {
216 opp-hz = /bits/ 64 <1500000000>;
217 opp-microvolt = <1040000>;
218 };
219 };
220
221 thermal-zones {
222 cpu-thermal {
223 polling-delay-passive = <250>;
224 polling-delay = <15000>;
225
226 thermal-sensors = <&sfctemp>;
227
228 cooling-maps {
229 map0 {
230 trip = <&cpu_alert0>;
231 cooling-device =
232 <&U74_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
233 <&U74_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
234 <&U74_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
235 <&U74_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
236 };
237 };
238
239 trips {
240 cpu_alert0: cpu-alert0 {
241 /* milliCelsius */
242 temperature = <85000>;
243 hysteresis = <2000>;
244 type = "passive";
245 };
246
247 cpu-crit {
248 /* milliCelsius */
249 temperature = <100000>;
250 hysteresis = <2000>;
251 type = "critical";
252 };
253 };
254 };
255 };
256
257 dvp_clk: dvp-clock {
258 compatible = "fixed-clock";
259 clock-output-names = "dvp_clk";
260 #clock-cells = <0>;
261 };
262 gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
263 compatible = "fixed-clock";
264 clock-output-names = "gmac0_rgmii_rxin";
265 #clock-cells = <0>;
266 };
267
268 gmac0_rmii_refin: gmac0-rmii-refin-clock {
269 compatible = "fixed-clock";
270 clock-output-names = "gmac0_rmii_refin";
271 #clock-cells = <0>;
272 };
273
274 gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
275 compatible = "fixed-clock";
276 clock-output-names = "gmac1_rgmii_rxin";
277 #clock-cells = <0>;
278 };
279
280 gmac1_rmii_refin: gmac1-rmii-refin-clock {
281 compatible = "fixed-clock";
282 clock-output-names = "gmac1_rmii_refin";
283 #clock-cells = <0>;
284 };
285
286 hdmitx0_pixelclk: hdmitx0-pixel-clock {
287 compatible = "fixed-clock";
288 clock-output-names = "hdmitx0_pixelclk";
289 #clock-cells = <0>;
290 };
291
292 i2srx_bclk_ext: i2srx-bclk-ext-clock {
293 compatible = "fixed-clock";
294 clock-output-names = "i2srx_bclk_ext";
295 #clock-cells = <0>;
296 };
297
298 i2srx_lrck_ext: i2srx-lrck-ext-clock {
299 compatible = "fixed-clock";
300 clock-output-names = "i2srx_lrck_ext";
301 #clock-cells = <0>;
302 };
303
304 i2stx_bclk_ext: i2stx-bclk-ext-clock {
305 compatible = "fixed-clock";
306 clock-output-names = "i2stx_bclk_ext";
307 #clock-cells = <0>;
308 };
309
310 i2stx_lrck_ext: i2stx-lrck-ext-clock {
311 compatible = "fixed-clock";
312 clock-output-names = "i2stx_lrck_ext";
313 #clock-cells = <0>;
314 };
315
316 mclk_ext: mclk-ext-clock {
317 compatible = "fixed-clock";
318 clock-output-names = "mclk_ext";
319 #clock-cells = <0>;
320 };
321
322 osc: oscillator {
323 compatible = "fixed-clock";
324 clock-output-names = "osc";
325 #clock-cells = <0>;
326 };
327
328 rtc_osc: rtc-oscillator {
329 compatible = "fixed-clock";
330 clock-output-names = "rtc_osc";
331 #clock-cells = <0>;
332 };
333
334 stmmac_axi_setup: stmmac-axi-config {
335 snps,lpi_en;
336 snps,wr_osr_lmt = <15>;
337 snps,rd_osr_lmt = <15>;
338 snps,blen = <256 128 64 32 0 0 0>;
339 };
340
341 tdm_ext: tdm-ext-clock {
342 compatible = "fixed-clock";
343 clock-output-names = "tdm_ext";
344 #clock-cells = <0>;
345 };
346
347 soc {
348 compatible = "simple-bus";
349 interrupt-parent = <&plic>;
350 #address-cells = <2>;
351 #size-cells = <2>;
352 ranges;
353
354 clint: timer@2000000 {
355 compatible = "starfive,jh7110-clint", "sifive,clint0";
356 reg = <0x0 0x2000000 0x0 0x10000>;
357 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
358 <&cpu1_intc 3>, <&cpu1_intc 7>,
359 <&cpu2_intc 3>, <&cpu2_intc 7>,
360 <&cpu3_intc 3>, <&cpu3_intc 7>,
361 <&cpu4_intc 3>, <&cpu4_intc 7>;
362 };
363
364 ccache: cache-controller@2010000 {
365 compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
366 reg = <0x0 0x2010000 0x0 0x4000>;
367 interrupts = <1>, <3>, <4>, <2>;
368 cache-block-size = <64>;
369 cache-level = <2>;
370 cache-sets = <2048>;
371 cache-size = <2097152>;
372 cache-unified;
373 };
374
375 plic: interrupt-controller@c000000 {
376 compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
377 reg = <0x0 0xc000000 0x0 0x4000000>;
378 interrupts-extended = <&cpu0_intc 11>,
379 <&cpu1_intc 11>, <&cpu1_intc 9>,
380 <&cpu2_intc 11>, <&cpu2_intc 9>,
381 <&cpu3_intc 11>, <&cpu3_intc 9>,
382 <&cpu4_intc 11>, <&cpu4_intc 9>;
383 interrupt-controller;
384 #interrupt-cells = <1>;
385 #address-cells = <0>;
386 riscv,ndev = <136>;
387 };
388
389 uart0: serial@10000000 {
390 compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
391 reg = <0x0 0x10000000 0x0 0x10000>;
392 clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
393 <&syscrg JH7110_SYSCLK_UART0_APB>;
394 clock-names = "baudclk", "apb_pclk";
395 resets = <&syscrg JH7110_SYSRST_UART0_APB>,
396 <&syscrg JH7110_SYSRST_UART0_CORE>;
397 interrupts = <32>;
398 reg-io-width = <4>;
399 reg-shift = <2>;
400 status = "disabled";
401 };
402
403 uart1: serial@10010000 {
404 compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
405 reg = <0x0 0x10010000 0x0 0x10000>;
406 clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
407 <&syscrg JH7110_SYSCLK_UART1_APB>;
408 clock-names = "baudclk", "apb_pclk";
409 resets = <&syscrg JH7110_SYSRST_UART1_APB>,
410 <&syscrg JH7110_SYSRST_UART1_CORE>;
411 interrupts = <33>;
412 reg-io-width = <4>;
413 reg-shift = <2>;
414 status = "disabled";
415 };
416
417 uart2: serial@10020000 {
418 compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
419 reg = <0x0 0x10020000 0x0 0x10000>;
420 clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
421 <&syscrg JH7110_SYSCLK_UART2_APB>;
422 clock-names = "baudclk", "apb_pclk";
423 resets = <&syscrg JH7110_SYSRST_UART2_APB>,
424 <&syscrg JH7110_SYSRST_UART2_CORE>;
425 interrupts = <34>;
426 reg-io-width = <4>;
427 reg-shift = <2>;
428 status = "disabled";
429 };
430
431 i2c0: i2c@10030000 {
432 compatible = "snps,designware-i2c";
433 reg = <0x0 0x10030000 0x0 0x10000>;
434 clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>;
435 clock-names = "ref";
436 resets = <&syscrg JH7110_SYSRST_I2C0_APB>;
437 interrupts = <35>;
438 #address-cells = <1>;
439 #size-cells = <0>;
440 status = "disabled";
441 };
442
443 i2c1: i2c@10040000 {
444 compatible = "snps,designware-i2c";
445 reg = <0x0 0x10040000 0x0 0x10000>;
446 clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>;
447 clock-names = "ref";
448 resets = <&syscrg JH7110_SYSRST_I2C1_APB>;
449 interrupts = <36>;
450 #address-cells = <1>;
451 #size-cells = <0>;
452 status = "disabled";
453 };
454
455 i2c2: i2c@10050000 {
456 compatible = "snps,designware-i2c";
457 reg = <0x0 0x10050000 0x0 0x10000>;
458 clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>;
459 clock-names = "ref";
460 resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
461 interrupts = <37>;
462 #address-cells = <1>;
463 #size-cells = <0>;
464 status = "disabled";
465 };
466
467 spi0: spi@10060000 {
468 compatible = "arm,pl022", "arm,primecell";
469 reg = <0x0 0x10060000 0x0 0x10000>;
470 clocks = <&syscrg JH7110_SYSCLK_SPI0_APB>,
471 <&syscrg JH7110_SYSCLK_SPI0_APB>;
472 clock-names = "sspclk", "apb_pclk";
473 resets = <&syscrg JH7110_SYSRST_SPI0_APB>;
474 interrupts = <38>;
475 arm,primecell-periphid = <0x00041022>;
476 num-cs = <1>;
477 #address-cells = <1>;
478 #size-cells = <0>;
479 status = "disabled";
480 };
481
482 spi1: spi@10070000 {
483 compatible = "arm,pl022", "arm,primecell";
484 reg = <0x0 0x10070000 0x0 0x10000>;
485 clocks = <&syscrg JH7110_SYSCLK_SPI1_APB>,
486 <&syscrg JH7110_SYSCLK_SPI1_APB>;
487 clock-names = "sspclk", "apb_pclk";
488 resets = <&syscrg JH7110_SYSRST_SPI1_APB>;
489 interrupts = <39>;
490 arm,primecell-periphid = <0x00041022>;
491 num-cs = <1>;
492 #address-cells = <1>;
493 #size-cells = <0>;
494 status = "disabled";
495 };
496
497 spi2: spi@10080000 {
498 compatible = "arm,pl022", "arm,primecell";
499 reg = <0x0 0x10080000 0x0 0x10000>;
500 clocks = <&syscrg JH7110_SYSCLK_SPI2_APB>,
501 <&syscrg JH7110_SYSCLK_SPI2_APB>;
502 clock-names = "sspclk", "apb_pclk";
503 resets = <&syscrg JH7110_SYSRST_SPI2_APB>;
504 interrupts = <40>;
505 arm,primecell-periphid = <0x00041022>;
506 num-cs = <1>;
507 #address-cells = <1>;
508 #size-cells = <0>;
509 status = "disabled";
510 };
511
512 tdm: tdm@10090000 {
513 compatible = "starfive,jh7110-tdm";
514 reg = <0x0 0x10090000 0x0 0x1000>;
515 clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>,
516 <&syscrg JH7110_SYSCLK_TDM_APB>,
517 <&syscrg JH7110_SYSCLK_TDM_INTERNAL>,
518 <&syscrg JH7110_SYSCLK_TDM_TDM>,
519 <&syscrg JH7110_SYSCLK_MCLK_INNER>,
520 <&tdm_ext>;
521 clock-names = "tdm_ahb", "tdm_apb",
522 "tdm_internal", "tdm",
523 "mclk_inner", "tdm_ext";
524 resets = <&syscrg JH7110_SYSRST_TDM_AHB>,
525 <&syscrg JH7110_SYSRST_TDM_APB>,
526 <&syscrg JH7110_SYSRST_TDM_CORE>;
527 dmas = <&dma 20>, <&dma 21>;
528 dma-names = "rx","tx";
529 #sound-dai-cells = <0>;
530 status = "disabled";
531 };
532
533 i2srx: i2s@100e0000 {
534 compatible = "starfive,jh7110-i2srx";
535 reg = <0x0 0x100e0000 0x0 0x1000>;
536 clocks = <&syscrg JH7110_SYSCLK_I2SRX_BCLK_MST>,
537 <&syscrg JH7110_SYSCLK_I2SRX_APB>,
538 <&syscrg JH7110_SYSCLK_MCLK>,
539 <&syscrg JH7110_SYSCLK_MCLK_INNER>,
540 <&mclk_ext>,
541 <&syscrg JH7110_SYSCLK_I2SRX_BCLK>,
542 <&syscrg JH7110_SYSCLK_I2SRX_LRCK>,
543 <&i2srx_bclk_ext>,
544 <&i2srx_lrck_ext>;
545 clock-names = "i2sclk", "apb", "mclk",
546 "mclk_inner", "mclk_ext", "bclk",
547 "lrck", "bclk_ext", "lrck_ext";
548 resets = <&syscrg JH7110_SYSRST_I2SRX_APB>,
549 <&syscrg JH7110_SYSRST_I2SRX_BCLK>;
550 dmas = <0>, <&dma 24>;
551 dma-names = "tx", "rx";
552 starfive,syscon = <&sys_syscon 0x18 0x2>;
553 #sound-dai-cells = <0>;
554 status = "disabled";
555 };
556
557 pwmdac: pwmdac@100b0000 {
558 compatible = "starfive,jh7110-pwmdac";
559 reg = <0x0 0x100b0000 0x0 0x1000>;
560 clocks = <&syscrg JH7110_SYSCLK_PWMDAC_APB>,
561 <&syscrg JH7110_SYSCLK_PWMDAC_CORE>;
562 clock-names = "apb", "core";
563 resets = <&syscrg JH7110_SYSRST_PWMDAC_APB>;
564 dmas = <&dma 22>;
565 dma-names = "tx";
566 #sound-dai-cells = <0>;
567 status = "disabled";
568 };
569
570 usb0: usb@10100000 {
571 compatible = "starfive,jh7110-usb";
572 ranges = <0x0 0x0 0x10100000 0x100000>;
573 #address-cells = <1>;
574 #size-cells = <1>;
575 starfive,stg-syscon = <&stg_syscon 0x4>;
576 clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>,
577 <&stgcrg JH7110_STGCLK_USB0_STB>,
578 <&stgcrg JH7110_STGCLK_USB0_APB>,
579 <&stgcrg JH7110_STGCLK_USB0_AXI>,
580 <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>;
581 clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
582 resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>,
583 <&stgcrg JH7110_STGRST_USB0_APB>,
584 <&stgcrg JH7110_STGRST_USB0_AXI>,
585 <&stgcrg JH7110_STGRST_USB0_UTMI_APB>;
586 reset-names = "pwrup", "apb", "axi", "utmi_apb";
587 status = "disabled";
588
589 usb_cdns3: usb@0 {
590 compatible = "cdns,usb3";
591 reg = <0x0 0x10000>,
592 <0x10000 0x10000>,
593 <0x20000 0x10000>;
594 reg-names = "otg", "xhci", "dev";
595 interrupts = <100>, <108>, <110>;
596 interrupt-names = "host", "peripheral", "otg";
597 phys = <&usbphy0>;
598 phy-names = "cdns3,usb2-phy";
599 };
600 };
601
602 usbphy0: phy@10200000 {
603 compatible = "starfive,jh7110-usb-phy";
604 reg = <0x0 0x10200000 0x0 0x10000>;
605 clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
606 <&stgcrg JH7110_STGCLK_USB0_APP_125>;
607 clock-names = "125m", "app_125m";
608 #phy-cells = <0>;
609 };
610
611 pciephy0: phy@10210000 {
612 compatible = "starfive,jh7110-pcie-phy";
613 reg = <0x0 0x10210000 0x0 0x10000>;
614 #phy-cells = <0>;
615 };
616
617 pciephy1: phy@10220000 {
618 compatible = "starfive,jh7110-pcie-phy";
619 reg = <0x0 0x10220000 0x0 0x10000>;
620 #phy-cells = <0>;
621 };
622
623 stgcrg: clock-controller@10230000 {
624 compatible = "starfive,jh7110-stgcrg";
625 reg = <0x0 0x10230000 0x0 0x10000>;
626 clocks = <&osc>,
627 <&syscrg JH7110_SYSCLK_HIFI4_CORE>,
628 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
629 <&syscrg JH7110_SYSCLK_USB_125M>,
630 <&syscrg JH7110_SYSCLK_CPU_BUS>,
631 <&syscrg JH7110_SYSCLK_HIFI4_AXI>,
632 <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
633 <&syscrg JH7110_SYSCLK_APB_BUS>;
634 clock-names = "osc", "hifi4_core",
635 "stg_axiahb", "usb_125m",
636 "cpu_bus", "hifi4_axi",
637 "nocstg_bus", "apb_bus";
638 #clock-cells = <1>;
639 #reset-cells = <1>;
640 };
641
642 stg_syscon: syscon@10240000 {
643 compatible = "starfive,jh7110-stg-syscon", "syscon";
644 reg = <0x0 0x10240000 0x0 0x1000>;
645 };
646
647 uart3: serial@12000000 {
648 compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
649 reg = <0x0 0x12000000 0x0 0x10000>;
650 clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
651 <&syscrg JH7110_SYSCLK_UART3_APB>;
652 clock-names = "baudclk", "apb_pclk";
653 resets = <&syscrg JH7110_SYSRST_UART3_APB>,
654 <&syscrg JH7110_SYSRST_UART3_CORE>;
655 interrupts = <45>;
656 reg-io-width = <4>;
657 reg-shift = <2>;
658 status = "disabled";
659 };
660
661 uart4: serial@12010000 {
662 compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
663 reg = <0x0 0x12010000 0x0 0x10000>;
664 clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
665 <&syscrg JH7110_SYSCLK_UART4_APB>;
666 clock-names = "baudclk", "apb_pclk";
667 resets = <&syscrg JH7110_SYSRST_UART4_APB>,
668 <&syscrg JH7110_SYSRST_UART4_CORE>;
669 interrupts = <46>;
670 reg-io-width = <4>;
671 reg-shift = <2>;
672 status = "disabled";
673 };
674
675 uart5: serial@12020000 {
676 compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
677 reg = <0x0 0x12020000 0x0 0x10000>;
678 clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
679 <&syscrg JH7110_SYSCLK_UART5_APB>;
680 clock-names = "baudclk", "apb_pclk";
681 resets = <&syscrg JH7110_SYSRST_UART5_APB>,
682 <&syscrg JH7110_SYSRST_UART5_CORE>;
683 interrupts = <47>;
684 reg-io-width = <4>;
685 reg-shift = <2>;
686 status = "disabled";
687 };
688
689 i2c3: i2c@12030000 {
690 compatible = "snps,designware-i2c";
691 reg = <0x0 0x12030000 0x0 0x10000>;
692 clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>;
693 clock-names = "ref";
694 resets = <&syscrg JH7110_SYSRST_I2C3_APB>;
695 interrupts = <48>;
696 #address-cells = <1>;
697 #size-cells = <0>;
698 status = "disabled";
699 };
700
701 i2c4: i2c@12040000 {
702 compatible = "snps,designware-i2c";
703 reg = <0x0 0x12040000 0x0 0x10000>;
704 clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>;
705 clock-names = "ref";
706 resets = <&syscrg JH7110_SYSRST_I2C4_APB>;
707 interrupts = <49>;
708 #address-cells = <1>;
709 #size-cells = <0>;
710 status = "disabled";
711 };
712
713 i2c5: i2c@12050000 {
714 compatible = "snps,designware-i2c";
715 reg = <0x0 0x12050000 0x0 0x10000>;
716 clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>;
717 clock-names = "ref";
718 resets = <&syscrg JH7110_SYSRST_I2C5_APB>;
719 interrupts = <50>;
720 #address-cells = <1>;
721 #size-cells = <0>;
722 status = "disabled";
723 };
724
725 i2c6: i2c@12060000 {
726 compatible = "snps,designware-i2c";
727 reg = <0x0 0x12060000 0x0 0x10000>;
728 clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>;
729 clock-names = "ref";
730 resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
731 interrupts = <51>;
732 #address-cells = <1>;
733 #size-cells = <0>;
734 status = "disabled";
735 };
736
737 spi3: spi@12070000 {
738 compatible = "arm,pl022", "arm,primecell";
739 reg = <0x0 0x12070000 0x0 0x10000>;
740 clocks = <&syscrg JH7110_SYSCLK_SPI3_APB>,
741 <&syscrg JH7110_SYSCLK_SPI3_APB>;
742 clock-names = "sspclk", "apb_pclk";
743 resets = <&syscrg JH7110_SYSRST_SPI3_APB>;
744 interrupts = <52>;
745 arm,primecell-periphid = <0x00041022>;
746 num-cs = <1>;
747 #address-cells = <1>;
748 #size-cells = <0>;
749 status = "disabled";
750 };
751
752 spi4: spi@12080000 {
753 compatible = "arm,pl022", "arm,primecell";
754 reg = <0x0 0x12080000 0x0 0x10000>;
755 clocks = <&syscrg JH7110_SYSCLK_SPI4_APB>,
756 <&syscrg JH7110_SYSCLK_SPI4_APB>;
757 clock-names = "sspclk", "apb_pclk";
758 resets = <&syscrg JH7110_SYSRST_SPI4_APB>;
759 interrupts = <53>;
760 arm,primecell-periphid = <0x00041022>;
761 num-cs = <1>;
762 #address-cells = <1>;
763 #size-cells = <0>;
764 status = "disabled";
765 };
766
767 spi5: spi@12090000 {
768 compatible = "arm,pl022", "arm,primecell";
769 reg = <0x0 0x12090000 0x0 0x10000>;
770 clocks = <&syscrg JH7110_SYSCLK_SPI5_APB>,
771 <&syscrg JH7110_SYSCLK_SPI5_APB>;
772 clock-names = "sspclk", "apb_pclk";
773 resets = <&syscrg JH7110_SYSRST_SPI5_APB>;
774 interrupts = <54>;
775 arm,primecell-periphid = <0x00041022>;
776 num-cs = <1>;
777 #address-cells = <1>;
778 #size-cells = <0>;
779 status = "disabled";
780 };
781
782 spi6: spi@120a0000 {
783 compatible = "arm,pl022", "arm,primecell";
784 reg = <0x0 0x120A0000 0x0 0x10000>;
785 clocks = <&syscrg JH7110_SYSCLK_SPI6_APB>,
786 <&syscrg JH7110_SYSCLK_SPI6_APB>;
787 clock-names = "sspclk", "apb_pclk";
788 resets = <&syscrg JH7110_SYSRST_SPI6_APB>;
789 interrupts = <55>;
790 arm,primecell-periphid = <0x00041022>;
791 num-cs = <1>;
792 #address-cells = <1>;
793 #size-cells = <0>;
794 status = "disabled";
795 };
796
797 i2stx0: i2s@120b0000 {
798 compatible = "starfive,jh7110-i2stx0";
799 reg = <0x0 0x120b0000 0x0 0x1000>;
800 clocks = <&syscrg JH7110_SYSCLK_I2STX0_BCLK_MST>,
801 <&syscrg JH7110_SYSCLK_I2STX0_APB>,
802 <&syscrg JH7110_SYSCLK_MCLK>,
803 <&syscrg JH7110_SYSCLK_MCLK_INNER>,
804 <&mclk_ext>;
805 clock-names = "i2sclk", "apb", "mclk",
806 "mclk_inner","mclk_ext";
807 resets = <&syscrg JH7110_SYSRST_I2STX0_APB>,
808 <&syscrg JH7110_SYSRST_I2STX0_BCLK>;
809 dmas = <&dma 47>;
810 dma-names = "tx";
811 #sound-dai-cells = <0>;
812 status = "disabled";
813 };
814
815 i2stx1: i2s@120c0000 {
816 compatible = "starfive,jh7110-i2stx1";
817 reg = <0x0 0x120c0000 0x0 0x1000>;
818 clocks = <&syscrg JH7110_SYSCLK_I2STX1_BCLK_MST>,
819 <&syscrg JH7110_SYSCLK_I2STX1_APB>,
820 <&syscrg JH7110_SYSCLK_MCLK>,
821 <&syscrg JH7110_SYSCLK_MCLK_INNER>,
822 <&mclk_ext>,
823 <&syscrg JH7110_SYSCLK_I2STX1_BCLK>,
824 <&syscrg JH7110_SYSCLK_I2STX1_LRCK>,
825 <&i2stx_bclk_ext>,
826 <&i2stx_lrck_ext>;
827 clock-names = "i2sclk", "apb", "mclk",
828 "mclk_inner", "mclk_ext", "bclk",
829 "lrck", "bclk_ext", "lrck_ext";
830 resets = <&syscrg JH7110_SYSRST_I2STX1_APB>,
831 <&syscrg JH7110_SYSRST_I2STX1_BCLK>;
832 dmas = <&dma 48>;
833 dma-names = "tx";
834 #sound-dai-cells = <0>;
835 status = "disabled";
836 };
837
838 pwm: pwm@120d0000 {
839 compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
840 reg = <0x0 0x120d0000 0x0 0x10000>;
841 clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
842 resets = <&syscrg JH7110_SYSRST_PWM_APB>;
843 #pwm-cells = <3>;
844 status = "disabled";
845 };
846
847 sfctemp: temperature-sensor@120e0000 {
848 compatible = "starfive,jh7110-temp";
849 reg = <0x0 0x120e0000 0x0 0x10000>;
850 clocks = <&syscrg JH7110_SYSCLK_TEMP_CORE>,
851 <&syscrg JH7110_SYSCLK_TEMP_APB>;
852 clock-names = "sense", "bus";
853 resets = <&syscrg JH7110_SYSRST_TEMP_CORE>,
854 <&syscrg JH7110_SYSRST_TEMP_APB>;
855 reset-names = "sense", "bus";
856 #thermal-sensor-cells = <0>;
857 };
858
859 qspi: spi@13010000 {
860 compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
861 reg = <0x0 0x13010000 0x0 0x10000>,
862 <0x0 0x21000000 0x0 0x400000>;
863 interrupts = <25>;
864 clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
865 <&syscrg JH7110_SYSCLK_QSPI_AHB>,
866 <&syscrg JH7110_SYSCLK_QSPI_APB>;
867 clock-names = "ref", "ahb", "apb";
868 resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
869 <&syscrg JH7110_SYSRST_QSPI_AHB>,
870 <&syscrg JH7110_SYSRST_QSPI_REF>;
871 reset-names = "qspi", "qspi-ocp", "rstc_ref";
872 cdns,fifo-depth = <256>;
873 cdns,fifo-width = <4>;
874 cdns,trigger-address = <0x0>;
875 status = "disabled";
876 };
877
878 syscrg: clock-controller@13020000 {
879 compatible = "starfive,jh7110-syscrg";
880 reg = <0x0 0x13020000 0x0 0x10000>;
881 clocks = <&osc>, <&gmac1_rmii_refin>,
882 <&gmac1_rgmii_rxin>,
883 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
884 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
885 <&tdm_ext>, <&mclk_ext>,
886 <&pllclk JH7110_PLLCLK_PLL0_OUT>,
887 <&pllclk JH7110_PLLCLK_PLL1_OUT>,
888 <&pllclk JH7110_PLLCLK_PLL2_OUT>;
889 clock-names = "osc", "gmac1_rmii_refin",
890 "gmac1_rgmii_rxin",
891 "i2stx_bclk_ext", "i2stx_lrck_ext",
892 "i2srx_bclk_ext", "i2srx_lrck_ext",
893 "tdm_ext", "mclk_ext",
894 "pll0_out", "pll1_out", "pll2_out";
895 #clock-cells = <1>;
896 #reset-cells = <1>;
897 };
898
899 sys_syscon: syscon@13030000 {
900 compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
901 reg = <0x0 0x13030000 0x0 0x1000>;
902
903 pllclk: clock-controller {
904 compatible = "starfive,jh7110-pll";
905 clocks = <&osc>;
906 #clock-cells = <1>;
907 };
908 };
909
910 sysgpio: pinctrl@13040000 {
911 compatible = "starfive,jh7110-sys-pinctrl";
912 reg = <0x0 0x13040000 0x0 0x10000>;
913 clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
914 resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
915 interrupts = <86>;
916 interrupt-controller;
917 #interrupt-cells = <2>;
918 gpio-controller;
919 #gpio-cells = <2>;
920 };
921
922 watchdog@13070000 {
923 compatible = "starfive,jh7110-wdt";
924 reg = <0x0 0x13070000 0x0 0x10000>;
925 clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
926 <&syscrg JH7110_SYSCLK_WDT_CORE>;
927 clock-names = "apb", "core";
928 resets = <&syscrg JH7110_SYSRST_WDT_APB>,
929 <&syscrg JH7110_SYSRST_WDT_CORE>;
930 };
931
932 crypto: crypto@16000000 {
933 compatible = "starfive,jh7110-crypto";
934 reg = <0x0 0x16000000 0x0 0x4000>;
935 clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
936 <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
937 clock-names = "hclk", "ahb";
938 interrupts = <28>;
939 resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
940 dmas = <&sdma 1 2>, <&sdma 0 2>;
941 dma-names = "tx", "rx";
942 };
943
944 sdma: dma-controller@16008000 {
945 compatible = "arm,pl080", "arm,primecell";
946 arm,primecell-periphid = <0x00041080>;
947 reg = <0x0 0x16008000 0x0 0x4000>;
948 interrupts = <29>;
949 clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>;
950 clock-names = "apb_pclk";
951 resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
952 lli-bus-interface-ahb1;
953 mem-bus-interface-ahb1;
954 memcpy-burst-size = <256>;
955 memcpy-bus-width = <32>;
956 #dma-cells = <2>;
957 };
958
959 rng: rng@1600c000 {
960 compatible = "starfive,jh7110-trng";
961 reg = <0x0 0x1600C000 0x0 0x4000>;
962 clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
963 <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
964 clock-names = "hclk", "ahb";
965 resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
966 interrupts = <30>;
967 };
968
969 mmc0: mmc@16010000 {
970 compatible = "starfive,jh7110-mmc";
971 reg = <0x0 0x16010000 0x0 0x10000>;
972 clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
973 <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
974 clock-names = "biu","ciu";
975 resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
976 reset-names = "reset";
977 interrupts = <74>;
978 fifo-depth = <32>;
979 fifo-watermark-aligned;
980 data-addr = <0>;
981 starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
982 status = "disabled";
983 };
984
985 mmc1: mmc@16020000 {
986 compatible = "starfive,jh7110-mmc";
987 reg = <0x0 0x16020000 0x0 0x10000>;
988 clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
989 <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
990 clock-names = "biu","ciu";
991 resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
992 reset-names = "reset";
993 interrupts = <75>;
994 fifo-depth = <32>;
995 fifo-watermark-aligned;
996 data-addr = <0>;
997 starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
998 status = "disabled";
999 };
1000
1001 gmac0: ethernet@16030000 {
1002 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
1003 reg = <0x0 0x16030000 0x0 0x10000>;
1004 clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
1005 <&aoncrg JH7110_AONCLK_GMAC0_AHB>,
1006 <&syscrg JH7110_SYSCLK_GMAC0_PTP>,
1007 <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
1008 <&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
1009 clock-names = "stmmaceth", "pclk", "ptp_ref",
1010 "tx", "gtx";
1011 resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
1012 <&aoncrg JH7110_AONRST_GMAC0_AHB>;
1013 reset-names = "stmmaceth", "ahb";
1014 interrupts = <7>, <6>, <5>;
1015 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1016 rx-fifo-depth = <2048>;
1017 tx-fifo-depth = <2048>;
1018 snps,multicast-filter-bins = <64>;
1019 snps,perfect-filter-entries = <256>;
1020 snps,fixed-burst;
1021 snps,no-pbl-x8;
1022 snps,force_thresh_dma_mode;
1023 snps,axi-config = <&stmmac_axi_setup>;
1024 snps,tso;
1025 snps,en-tx-lpi-clockgating;
1026 snps,txpbl = <16>;
1027 snps,rxpbl = <16>;
1028 starfive,syscon = <&aon_syscon 0xc 0x12>;
1029 status = "disabled";
1030 };
1031
1032 gmac1: ethernet@16040000 {
1033 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
1034 reg = <0x0 0x16040000 0x0 0x10000>;
1035 clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
1036 <&syscrg JH7110_SYSCLK_GMAC1_AHB>,
1037 <&syscrg JH7110_SYSCLK_GMAC1_PTP>,
1038 <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>,
1039 <&syscrg JH7110_SYSCLK_GMAC1_GTXC>;
1040 clock-names = "stmmaceth", "pclk", "ptp_ref",
1041 "tx", "gtx";
1042 resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
1043 <&syscrg JH7110_SYSRST_GMAC1_AHB>;
1044 reset-names = "stmmaceth", "ahb";
1045 interrupts = <78>, <77>, <76>;
1046 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1047 rx-fifo-depth = <2048>;
1048 tx-fifo-depth = <2048>;
1049 snps,multicast-filter-bins = <64>;
1050 snps,perfect-filter-entries = <256>;
1051 snps,fixed-burst;
1052 snps,no-pbl-x8;
1053 snps,force_thresh_dma_mode;
1054 snps,axi-config = <&stmmac_axi_setup>;
1055 snps,tso;
1056 snps,en-tx-lpi-clockgating;
1057 snps,txpbl = <16>;
1058 snps,rxpbl = <16>;
1059 starfive,syscon = <&sys_syscon 0x90 0x2>;
1060 status = "disabled";
1061 };
1062
1063 dma: dma-controller@16050000 {
1064 compatible = "starfive,jh7110-axi-dma";
1065 reg = <0x0 0x16050000 0x0 0x10000>;
1066 clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
1067 <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
1068 clock-names = "core-clk", "cfgr-clk";
1069 resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
1070 <&stgcrg JH7110_STGRST_DMA1P_AHB>;
1071 interrupts = <73>;
1072 #dma-cells = <1>;
1073 dma-channels = <4>;
1074 snps,dma-masters = <1>;
1075 snps,data-width = <3>;
1076 snps,block-size = <65536 65536 65536 65536>;
1077 snps,priority = <0 1 2 3>;
1078 snps,axi-max-burst-len = <16>;
1079 };
1080
1081 aoncrg: clock-controller@17000000 {
1082 compatible = "starfive,jh7110-aoncrg";
1083 reg = <0x0 0x17000000 0x0 0x10000>;
1084 clocks = <&osc>, <&gmac0_rmii_refin>,
1085 <&gmac0_rgmii_rxin>,
1086 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
1087 <&syscrg JH7110_SYSCLK_APB_BUS>,
1088 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
1089 <&rtc_osc>;
1090 clock-names = "osc", "gmac0_rmii_refin",
1091 "gmac0_rgmii_rxin", "stg_axiahb",
1092 "apb_bus", "gmac0_gtxclk",
1093 "rtc_osc";
1094 #clock-cells = <1>;
1095 #reset-cells = <1>;
1096 };
1097
1098 aon_syscon: syscon@17010000 {
1099 compatible = "starfive,jh7110-aon-syscon", "syscon";
1100 reg = <0x0 0x17010000 0x0 0x1000>;
1101 #power-domain-cells = <1>;
1102 };
1103
1104 aongpio: pinctrl@17020000 {
1105 compatible = "starfive,jh7110-aon-pinctrl";
1106 reg = <0x0 0x17020000 0x0 0x10000>;
1107 resets = <&aoncrg JH7110_AONRST_IOMUX>;
1108 interrupts = <85>;
1109 interrupt-controller;
1110 #interrupt-cells = <2>;
1111 gpio-controller;
1112 #gpio-cells = <2>;
1113 };
1114
1115 pwrc: power-controller@17030000 {
1116 compatible = "starfive,jh7110-pmu";
1117 reg = <0x0 0x17030000 0x0 0x10000>;
1118 interrupts = <111>;
1119 #power-domain-cells = <1>;
1120 };
1121
1122 csi2rx: csi@19800000 {
1123 compatible = "starfive,jh7110-csi2rx", "cdns,csi2rx";
1124 reg = <0x0 0x19800000 0x0 0x10000>;
1125 clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>,
1126 <&ispcrg JH7110_ISPCLK_VIN_APB>,
1127 <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF0>,
1128 <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF1>,
1129 <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF2>,
1130 <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF3>;
1131 clock-names = "sys_clk", "p_clk",
1132 "pixel_if0_clk", "pixel_if1_clk",
1133 "pixel_if2_clk", "pixel_if3_clk";
1134 resets = <&ispcrg JH7110_ISPRST_VIN_SYS>,
1135 <&ispcrg JH7110_ISPRST_VIN_APB>,
1136 <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF0>,
1137 <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF1>,
1138 <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF2>,
1139 <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF3>;
1140 reset-names = "sys", "reg_bank",
1141 "pixel_if0", "pixel_if1",
1142 "pixel_if2", "pixel_if3";
1143 phys = <&csi_phy>;
1144 phy-names = "dphy";
1145 status = "disabled";
1146 };
1147
1148 ispcrg: clock-controller@19810000 {
1149 compatible = "starfive,jh7110-ispcrg";
1150 reg = <0x0 0x19810000 0x0 0x10000>;
1151 clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
1152 <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
1153 <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
1154 <&dvp_clk>;
1155 clock-names = "isp_top_core", "isp_top_axi",
1156 "noc_bus_isp_axi", "dvp_clk";
1157 resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
1158 <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
1159 <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
1160 #clock-cells = <1>;
1161 #reset-cells = <1>;
1162 power-domains = <&pwrc JH7110_PD_ISP>;
1163 };
1164
1165 csi_phy: phy@19820000 {
1166 compatible = "starfive,jh7110-dphy-rx";
1167 reg = <0x0 0x19820000 0x0 0x10000>;
1168 clocks = <&ispcrg JH7110_ISPCLK_M31DPHY_CFG_IN>,
1169 <&ispcrg JH7110_ISPCLK_M31DPHY_REF_IN>,
1170 <&ispcrg JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0>;
1171 clock-names = "cfg", "ref", "tx";
1172 resets = <&ispcrg JH7110_ISPRST_M31DPHY_HW>,
1173 <&ispcrg JH7110_ISPRST_M31DPHY_B09_AON>;
1174 power-domains = <&aon_syscon JH7110_AON_PD_DPHY_RX>;
1175 #phy-cells = <0>;
1176 };
1177
1178 camss: isp@19840000 {
1179 compatible = "starfive,jh7110-camss";
1180 reg = <0x0 0x19840000 0x0 0x10000>,
1181 <0x0 0x19870000 0x0 0x30000>;
1182 reg-names = "syscon", "isp";
1183 clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
1184 <&ispcrg JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C>,
1185 <&ispcrg JH7110_ISPCLK_DVP_INV>,
1186 <&ispcrg JH7110_ISPCLK_VIN_P_AXI_WR>,
1187 <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>,
1188 <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
1189 <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>;
1190 clock-names = "apb_func", "wrapper_clk_c", "dvp_inv",
1191 "axiwr", "mipi_rx0_pxl", "ispcore_2x",
1192 "isp_axi";
1193 resets = <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_P>,
1194 <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_C>,
1195 <&ispcrg JH7110_ISPRST_VIN_P_AXI_RD>,
1196 <&ispcrg JH7110_ISPRST_VIN_P_AXI_WR>,
1197 <&syscrg JH7110_SYSRST_ISP_TOP>,
1198 <&syscrg JH7110_SYSRST_ISP_TOP_AXI>;
1199 reset-names = "wrapper_p", "wrapper_c", "axird",
1200 "axiwr", "isp_top_n", "isp_top_axi";
1201 power-domains = <&pwrc JH7110_PD_ISP>;
1202 interrupts = <92>, <87>, <90>, <88>;
1203 status = "disabled";
1204 };
1205
1206 voutcrg: clock-controller@295c0000 {
1207 compatible = "starfive,jh7110-voutcrg";
1208 reg = <0x0 0x295c0000 0x0 0x10000>;
1209 clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
1210 <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
1211 <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
1212 <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
1213 <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
1214 <&hdmitx0_pixelclk>;
1215 clock-names = "vout_src", "vout_top_ahb",
1216 "vout_top_axi", "vout_top_hdmitx0_mclk",
1217 "i2stx0_bclk", "hdmitx0_pixelclk";
1218 resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
1219 #clock-cells = <1>;
1220 #reset-cells = <1>;
1221 power-domains = <&pwrc JH7110_PD_VOUT>;
1222 };
1223
1224 pcie0: pcie@940000000 {
1225 compatible = "starfive,jh7110-pcie";
1226 reg = <0x9 0x40000000 0x0 0x1000000>,
1227 <0x0 0x2b000000 0x0 0x100000>;
1228 reg-names = "cfg", "apb";
1229 linux,pci-domain = <0>;
1230 #address-cells = <3>;
1231 #size-cells = <2>;
1232 #interrupt-cells = <1>;
1233 ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
1234 <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
1235 interrupts = <56>;
1236 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1237 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
1238 <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
1239 <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
1240 <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
1241 msi-controller;
1242 device_type = "pci";
1243 starfive,stg-syscon = <&stg_syscon>;
1244 bus-range = <0x0 0xff>;
1245 clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
1246 <&stgcrg JH7110_STGCLK_PCIE0_TL>,
1247 <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,
1248 <&stgcrg JH7110_STGCLK_PCIE0_APB>;
1249 clock-names = "noc", "tl", "axi_mst0", "apb";
1250 resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>,
1251 <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>,
1252 <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>,
1253 <&stgcrg JH7110_STGRST_PCIE0_BRG>,
1254 <&stgcrg JH7110_STGRST_PCIE0_CORE>,
1255 <&stgcrg JH7110_STGRST_PCIE0_APB>;
1256 reset-names = "mst0", "slv0", "slv", "brg",
1257 "core", "apb";
1258 status = "disabled";
1259
1260 pcie_intc0: interrupt-controller {
1261 #address-cells = <0>;
1262 #interrupt-cells = <1>;
1263 interrupt-controller;
1264 };
1265 };
1266
1267 pcie1: pcie@9c0000000 {
1268 compatible = "starfive,jh7110-pcie";
1269 reg = <0x9 0xc0000000 0x0 0x1000000>,
1270 <0x0 0x2c000000 0x0 0x100000>;
1271 reg-names = "cfg", "apb";
1272 linux,pci-domain = <1>;
1273 #address-cells = <3>;
1274 #size-cells = <2>;
1275 #interrupt-cells = <1>;
1276 ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
1277 <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
1278 interrupts = <57>;
1279 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1280 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>,
1281 <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>,
1282 <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>,
1283 <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>;
1284 msi-controller;
1285 device_type = "pci";
1286 starfive,stg-syscon = <&stg_syscon>;
1287 bus-range = <0x0 0xff>;
1288 clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
1289 <&stgcrg JH7110_STGCLK_PCIE1_TL>,
1290 <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>,
1291 <&stgcrg JH7110_STGCLK_PCIE1_APB>;
1292 clock-names = "noc", "tl", "axi_mst0", "apb";
1293 resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>,
1294 <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>,
1295 <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>,
1296 <&stgcrg JH7110_STGRST_PCIE1_BRG>,
1297 <&stgcrg JH7110_STGRST_PCIE1_CORE>,
1298 <&stgcrg JH7110_STGRST_PCIE1_APB>;
1299 reset-names = "mst0", "slv0", "slv", "brg",
1300 "core", "apb";
1301 status = "disabled";
1302
1303 pcie_intc1: interrupt-controller {
1304 #address-cells = <0>;
1305 #interrupt-cells = <1>;
1306 interrupt-controller;
1307 };
1308 };
1309 };
1310 };
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