1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2021 Alibaba Group Holding Limited.
4 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
5 */
6
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
9
10 / {
11 compatible = "thead,th1520";
12 #address-cells = <2>;
13 #size-cells = <2>;
14
15 cpus: cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <3000000>;
19
20 c910_0: cpu@0 {
21 compatible = "thead,c910", "riscv";
22 device_type = "cpu";
23 riscv,isa = "rv64imafdc";
24 riscv,isa-base = "rv64i";
25 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
26 "zifencei", "zihpm";
27 reg = <0>;
28 i-cache-block-size = <64>;
29 i-cache-size = <65536>;
30 i-cache-sets = <512>;
31 d-cache-block-size = <64>;
32 d-cache-size = <65536>;
33 d-cache-sets = <512>;
34 next-level-cache = <&l2_cache>;
35 mmu-type = "riscv,sv39";
36
37 cpu0_intc: interrupt-controller {
38 compatible = "riscv,cpu-intc";
39 interrupt-controller;
40 #interrupt-cells = <1>;
41 };
42 };
43
44 c910_1: cpu@1 {
45 compatible = "thead,c910", "riscv";
46 device_type = "cpu";
47 riscv,isa = "rv64imafdc";
48 riscv,isa-base = "rv64i";
49 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
50 "zifencei", "zihpm";
51 reg = <1>;
52 i-cache-block-size = <64>;
53 i-cache-size = <65536>;
54 i-cache-sets = <512>;
55 d-cache-block-size = <64>;
56 d-cache-size = <65536>;
57 d-cache-sets = <512>;
58 next-level-cache = <&l2_cache>;
59 mmu-type = "riscv,sv39";
60
61 cpu1_intc: interrupt-controller {
62 compatible = "riscv,cpu-intc";
63 interrupt-controller;
64 #interrupt-cells = <1>;
65 };
66 };
67
68 c910_2: cpu@2 {
69 compatible = "thead,c910", "riscv";
70 device_type = "cpu";
71 riscv,isa = "rv64imafdc";
72 riscv,isa-base = "rv64i";
73 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
74 "zifencei", "zihpm";
75 reg = <2>;
76 i-cache-block-size = <64>;
77 i-cache-size = <65536>;
78 i-cache-sets = <512>;
79 d-cache-block-size = <64>;
80 d-cache-size = <65536>;
81 d-cache-sets = <512>;
82 next-level-cache = <&l2_cache>;
83 mmu-type = "riscv,sv39";
84
85 cpu2_intc: interrupt-controller {
86 compatible = "riscv,cpu-intc";
87 interrupt-controller;
88 #interrupt-cells = <1>;
89 };
90 };
91
92 c910_3: cpu@3 {
93 compatible = "thead,c910", "riscv";
94 device_type = "cpu";
95 riscv,isa = "rv64imafdc";
96 riscv,isa-base = "rv64i";
97 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
98 "zifencei", "zihpm";
99 reg = <3>;
100 i-cache-block-size = <64>;
101 i-cache-size = <65536>;
102 i-cache-sets = <512>;
103 d-cache-block-size = <64>;
104 d-cache-size = <65536>;
105 d-cache-sets = <512>;
106 next-level-cache = <&l2_cache>;
107 mmu-type = "riscv,sv39";
108
109 cpu3_intc: interrupt-controller {
110 compatible = "riscv,cpu-intc";
111 interrupt-controller;
112 #interrupt-cells = <1>;
113 };
114 };
115
116 l2_cache: l2-cache {
117 compatible = "cache";
118 cache-block-size = <64>;
119 cache-level = <2>;
120 cache-size = <1048576>;
121 cache-sets = <1024>;
122 cache-unified;
123 };
124 };
125
126 pmu {
127 compatible = "riscv,pmu";
128 riscv,event-to-mhpmcounters =
129 <0x00003 0x00003 0x0007fff8>,
130 <0x00004 0x00004 0x0007fff8>,
131 <0x00005 0x00005 0x0007fff8>,
132 <0x00006 0x00006 0x0007fff8>,
133 <0x00007 0x00007 0x0007fff8>,
134 <0x00008 0x00008 0x0007fff8>,
135 <0x00009 0x00009 0x0007fff8>,
136 <0x0000a 0x0000a 0x0007fff8>,
137 <0x10000 0x10000 0x0007fff8>,
138 <0x10001 0x10001 0x0007fff8>,
139 <0x10002 0x10002 0x0007fff8>,
140 <0x10003 0x10003 0x0007fff8>,
141 <0x10010 0x10010 0x0007fff8>,
142 <0x10011 0x10011 0x0007fff8>,
143 <0x10012 0x10012 0x0007fff8>,
144 <0x10013 0x10013 0x0007fff8>;
145 riscv,event-to-mhpmevent =
146 <0x00003 0x00000000 0x00000001>,
147 <0x00004 0x00000000 0x00000002>,
148 <0x00006 0x00000000 0x00000006>,
149 <0x00005 0x00000000 0x00000007>,
150 <0x00007 0x00000000 0x00000008>,
151 <0x00008 0x00000000 0x00000009>,
152 <0x00009 0x00000000 0x0000000a>,
153 <0x0000a 0x00000000 0x0000000b>,
154 <0x10000 0x00000000 0x0000000c>,
155 <0x10001 0x00000000 0x0000000d>,
156 <0x10002 0x00000000 0x0000000e>,
157 <0x10003 0x00000000 0x0000000f>,
158 <0x10010 0x00000000 0x00000010>,
159 <0x10011 0x00000000 0x00000011>,
160 <0x10012 0x00000000 0x00000012>,
161 <0x10013 0x00000000 0x00000013>;
162 riscv,raw-event-to-mhpmcounters =
163 <0x00000000 0x00000001 0xffffffff 0xffffffff 0x0007fff8>,
164 <0x00000000 0x00000002 0xffffffff 0xffffffff 0x0007fff8>,
165 <0x00000000 0x00000003 0xffffffff 0xffffffff 0x0007fff8>,
166 <0x00000000 0x00000004 0xffffffff 0xffffffff 0x0007fff8>,
167 <0x00000000 0x00000005 0xffffffff 0xffffffff 0x0007fff8>,
168 <0x00000000 0x00000006 0xffffffff 0xffffffff 0x0007fff8>,
169 <0x00000000 0x00000007 0xffffffff 0xffffffff 0x0007fff8>,
170 <0x00000000 0x00000008 0xffffffff 0xffffffff 0x0007fff8>,
171 <0x00000000 0x00000009 0xffffffff 0xffffffff 0x0007fff8>,
172 <0x00000000 0x0000000a 0xffffffff 0xffffffff 0x0007fff8>,
173 <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x0007fff8>,
174 <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x0007fff8>,
175 <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x0007fff8>,
176 <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x0007fff8>,
177 <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x0007fff8>,
178 <0x00000000 0x00000010 0xffffffff 0xffffffff 0x0007fff8>,
179 <0x00000000 0x00000011 0xffffffff 0xffffffff 0x0007fff8>,
180 <0x00000000 0x00000012 0xffffffff 0xffffffff 0x0007fff8>,
181 <0x00000000 0x00000013 0xffffffff 0xffffffff 0x0007fff8>,
182 <0x00000000 0x00000014 0xffffffff 0xffffffff 0x0007fff8>,
183 <0x00000000 0x00000015 0xffffffff 0xffffffff 0x0007fff8>,
184 <0x00000000 0x00000016 0xffffffff 0xffffffff 0x0007fff8>,
185 <0x00000000 0x00000017 0xffffffff 0xffffffff 0x0007fff8>,
186 <0x00000000 0x00000018 0xffffffff 0xffffffff 0x0007fff8>,
187 <0x00000000 0x00000019 0xffffffff 0xffffffff 0x0007fff8>,
188 <0x00000000 0x0000001a 0xffffffff 0xffffffff 0x0007fff8>,
189 <0x00000000 0x0000001b 0xffffffff 0xffffffff 0x0007fff8>,
190 <0x00000000 0x0000001c 0xffffffff 0xffffffff 0x0007fff8>,
191 <0x00000000 0x0000001d 0xffffffff 0xffffffff 0x0007fff8>,
192 <0x00000000 0x0000001e 0xffffffff 0xffffffff 0x0007fff8>,
193 <0x00000000 0x0000001f 0xffffffff 0xffffffff 0x0007fff8>,
194 <0x00000000 0x00000020 0xffffffff 0xffffffff 0x0007fff8>,
195 <0x00000000 0x00000021 0xffffffff 0xffffffff 0x0007fff8>,
196 <0x00000000 0x00000022 0xffffffff 0xffffffff 0x0007fff8>,
197 <0x00000000 0x00000023 0xffffffff 0xffffffff 0x0007fff8>,
198 <0x00000000 0x00000024 0xffffffff 0xffffffff 0x0007fff8>,
199 <0x00000000 0x00000025 0xffffffff 0xffffffff 0x0007fff8>,
200 <0x00000000 0x00000026 0xffffffff 0xffffffff 0x0007fff8>,
201 <0x00000000 0x00000027 0xffffffff 0xffffffff 0x0007fff8>,
202 <0x00000000 0x00000028 0xffffffff 0xffffffff 0x0007fff8>,
203 <0x00000000 0x00000029 0xffffffff 0xffffffff 0x0007fff8>,
204 <0x00000000 0x0000002a 0xffffffff 0xffffffff 0x0007fff8>;
205 };
206
207 osc: oscillator {
208 compatible = "fixed-clock";
209 clock-output-names = "osc_24m";
210 #clock-cells = <0>;
211 };
212
213 osc_32k: 32k-oscillator {
214 compatible = "fixed-clock";
215 clock-output-names = "osc_32k";
216 #clock-cells = <0>;
217 };
218
219 soc {
220 compatible = "simple-bus";
221 interrupt-parent = <&plic>;
222 #address-cells = <2>;
223 #size-cells = <2>;
224 dma-noncoherent;
225 ranges;
226
227 plic: interrupt-controller@ffd8000000 {
228 compatible = "thead,th1520-plic", "thead,c900-plic";
229 reg = <0xff 0xd8000000 0x0 0x01000000>;
230 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
231 <&cpu1_intc 11>, <&cpu1_intc 9>,
232 <&cpu2_intc 11>, <&cpu2_intc 9>,
233 <&cpu3_intc 11>, <&cpu3_intc 9>;
234 interrupt-controller;
235 #address-cells = <0>;
236 #interrupt-cells = <2>;
237 riscv,ndev = <240>;
238 };
239
240 clint: timer@ffdc000000 {
241 compatible = "thead,th1520-clint", "thead,c900-clint";
242 reg = <0xff 0xdc000000 0x0 0x00010000>;
243 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
244 <&cpu1_intc 3>, <&cpu1_intc 7>,
245 <&cpu2_intc 3>, <&cpu2_intc 7>,
246 <&cpu3_intc 3>, <&cpu3_intc 7>;
247 };
248
249 spi0: spi@ffe700c000 {
250 compatible = "thead,th1520-spi", "snps,dw-apb-ssi";
251 reg = <0xff 0xe700c000 0x0 0x1000>;
252 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&clk CLK_SPI>;
254 #address-cells = <1>;
255 #size-cells = <0>;
256 status = "disabled";
257 };
258
259 uart0: serial@ffe7014000 {
260 compatible = "snps,dw-apb-uart";
261 reg = <0xff 0xe7014000 0x0 0x100>;
262 interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>;
264 clock-names = "baudclk", "apb_pclk";
265 reg-shift = <2>;
266 reg-io-width = <4>;
267 status = "disabled";
268 };
269
270 emmc: mmc@ffe7080000 {
271 compatible = "thead,th1520-dwcmshc";
272 reg = <0xff 0xe7080000 0x0 0x10000>;
273 interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&clk CLK_EMMC_SDIO>;
275 clock-names = "core";
276 status = "disabled";
277 };
278
279 sdio0: mmc@ffe7090000 {
280 compatible = "thead,th1520-dwcmshc";
281 reg = <0xff 0xe7090000 0x0 0x10000>;
282 interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&clk CLK_EMMC_SDIO>;
284 clock-names = "core";
285 status = "disabled";
286 };
287
288 sdio1: mmc@ffe70a0000 {
289 compatible = "thead,th1520-dwcmshc";
290 reg = <0xff 0xe70a0000 0x0 0x10000>;
291 interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&clk CLK_EMMC_SDIO>;
293 clock-names = "core";
294 status = "disabled";
295 };
296
297 uart1: serial@ffe7f00000 {
298 compatible = "snps,dw-apb-uart";
299 reg = <0xff 0xe7f00000 0x0 0x100>;
300 interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>;
302 clock-names = "baudclk", "apb_pclk";
303 reg-shift = <2>;
304 reg-io-width = <4>;
305 status = "disabled";
306 };
307
308 uart3: serial@ffe7f04000 {
309 compatible = "snps,dw-apb-uart";
310 reg = <0xff 0xe7f04000 0x0 0x100>;
311 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>;
313 clock-names = "baudclk", "apb_pclk";
314 reg-shift = <2>;
315 reg-io-width = <4>;
316 status = "disabled";
317 };
318
319 gpio2: gpio@ffe7f34000 {
320 compatible = "snps,dw-apb-gpio";
321 reg = <0xff 0xe7f34000 0x0 0x1000>;
322 #address-cells = <1>;
323 #size-cells = <0>;
324 clocks = <&clk CLK_GPIO2>;
325
326 portc: gpio-controller@0 {
327 compatible = "snps,dw-apb-gpio-port";
328 gpio-controller;
329 #gpio-cells = <2>;
330 ngpios = <32>;
331 reg = <0>;
332 interrupt-controller;
333 #interrupt-cells = <2>;
334 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
335 };
336 };
337
338 gpio3: gpio@ffe7f38000 {
339 compatible = "snps,dw-apb-gpio";
340 reg = <0xff 0xe7f38000 0x0 0x1000>;
341 #address-cells = <1>;
342 #size-cells = <0>;
343 clocks = <&clk CLK_GPIO3>;
344
345 portd: gpio-controller@0 {
346 compatible = "snps,dw-apb-gpio-port";
347 gpio-controller;
348 #gpio-cells = <2>;
349 ngpios = <32>;
350 reg = <0>;
351 interrupt-controller;
352 #interrupt-cells = <2>;
353 interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
354 };
355 };
356
357 gpio0: gpio@ffec005000 {
358 compatible = "snps,dw-apb-gpio";
359 reg = <0xff 0xec005000 0x0 0x1000>;
360 #address-cells = <1>;
361 #size-cells = <0>;
362 clocks = <&clk CLK_GPIO0>;
363
364 porta: gpio-controller@0 {
365 compatible = "snps,dw-apb-gpio-port";
366 gpio-controller;
367 #gpio-cells = <2>;
368 ngpios = <32>;
369 reg = <0>;
370 interrupt-controller;
371 #interrupt-cells = <2>;
372 interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
373 };
374 };
375
376 gpio1: gpio@ffec006000 {
377 compatible = "snps,dw-apb-gpio";
378 reg = <0xff 0xec006000 0x0 0x1000>;
379 #address-cells = <1>;
380 #size-cells = <0>;
381 clocks = <&clk CLK_GPIO1>;
382
383 portb: gpio-controller@0 {
384 compatible = "snps,dw-apb-gpio-port";
385 gpio-controller;
386 #gpio-cells = <2>;
387 ngpios = <32>;
388 reg = <0>;
389 interrupt-controller;
390 #interrupt-cells = <2>;
391 interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
392 };
393 };
394
395 uart2: serial@ffec010000 {
396 compatible = "snps,dw-apb-uart";
397 reg = <0xff 0xec010000 0x0 0x4000>;
398 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
399 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>;
400 clock-names = "baudclk", "apb_pclk";
401 reg-shift = <2>;
402 reg-io-width = <4>;
403 status = "disabled";
404 };
405
406 clk: clock-controller@ffef010000 {
407 compatible = "thead,th1520-clk-ap";
408 reg = <0xff 0xef010000 0x0 0x1000>;
409 clocks = <&osc>;
410 #clock-cells = <1>;
411 };
412
413 dmac0: dma-controller@ffefc00000 {
414 compatible = "snps,axi-dma-1.01a";
415 reg = <0xff 0xefc00000 0x0 0x1000>;
416 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&clk CLK_PERI_APB_PCLK>, <&clk CLK_PERI_APB_PCLK>;
418 clock-names = "core-clk", "cfgr-clk";
419 #dma-cells = <1>;
420 dma-channels = <4>;
421 snps,block-size = <65536 65536 65536 65536>;
422 snps,priority = <0 1 2 3>;
423 snps,dma-masters = <1>;
424 snps,data-width = <4>;
425 snps,axi-max-burst-len = <16>;
426 status = "disabled";
427 };
428
429 timer0: timer@ffefc32000 {
430 compatible = "snps,dw-apb-timer";
431 reg = <0xff 0xefc32000 0x0 0x14>;
432 clocks = <&clk CLK_PERI_APB_PCLK>;
433 clock-names = "timer";
434 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
435 status = "disabled";
436 };
437
438 timer1: timer@ffefc32014 {
439 compatible = "snps,dw-apb-timer";
440 reg = <0xff 0xefc32014 0x0 0x14>;
441 clocks = <&clk CLK_PERI_APB_PCLK>;
442 clock-names = "timer";
443 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
444 status = "disabled";
445 };
446
447 timer2: timer@ffefc32028 {
448 compatible = "snps,dw-apb-timer";
449 reg = <0xff 0xefc32028 0x0 0x14>;
450 clocks = <&clk CLK_PERI_APB_PCLK>;
451 clock-names = "timer";
452 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
453 status = "disabled";
454 };
455
456 timer3: timer@ffefc3203c {
457 compatible = "snps,dw-apb-timer";
458 reg = <0xff 0xefc3203c 0x0 0x14>;
459 clocks = <&clk CLK_PERI_APB_PCLK>;
460 clock-names = "timer";
461 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
462 status = "disabled";
463 };
464
465 uart4: serial@fff7f08000 {
466 compatible = "snps,dw-apb-uart";
467 reg = <0xff 0xf7f08000 0x0 0x4000>;
468 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>;
470 clock-names = "baudclk", "apb_pclk";
471 reg-shift = <2>;
472 reg-io-width = <4>;
473 status = "disabled";
474 };
475
476 uart5: serial@fff7f0c000 {
477 compatible = "snps,dw-apb-uart";
478 reg = <0xff 0xf7f0c000 0x0 0x4000>;
479 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>;
481 clock-names = "baudclk", "apb_pclk";
482 reg-shift = <2>;
483 reg-io-width = <4>;
484 status = "disabled";
485 };
486
487 timer4: timer@ffffc33000 {
488 compatible = "snps,dw-apb-timer";
489 reg = <0xff 0xffc33000 0x0 0x14>;
490 clocks = <&clk CLK_PERI_APB_PCLK>;
491 clock-names = "timer";
492 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
493 status = "disabled";
494 };
495
496 timer5: timer@ffffc33014 {
497 compatible = "snps,dw-apb-timer";
498 reg = <0xff 0xffc33014 0x0 0x14>;
499 clocks = <&clk CLK_PERI_APB_PCLK>;
500 clock-names = "timer";
501 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
502 status = "disabled";
503 };
504
505 timer6: timer@ffffc33028 {
506 compatible = "snps,dw-apb-timer";
507 reg = <0xff 0xffc33028 0x0 0x14>;
508 clocks = <&clk CLK_PERI_APB_PCLK>;
509 clock-names = "timer";
510 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
511 status = "disabled";
512 };
513
514 timer7: timer@ffffc3303c {
515 compatible = "snps,dw-apb-timer";
516 reg = <0xff 0xffc3303c 0x0 0x14>;
517 clocks = <&clk CLK_PERI_APB_PCLK>;
518 clock-names = "timer";
519 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
520 status = "disabled";
521 };
522
523 ao_gpio0: gpio@fffff41000 {
524 compatible = "snps,dw-apb-gpio";
525 reg = <0xff 0xfff41000 0x0 0x1000>;
526 #address-cells = <1>;
527 #size-cells = <0>;
528
529 porte: gpio-controller@0 {
530 compatible = "snps,dw-apb-gpio-port";
531 gpio-controller;
532 #gpio-cells = <2>;
533 ngpios = <32>;
534 reg = <0>;
535 interrupt-controller;
536 #interrupt-cells = <2>;
537 interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
538 };
539 };
540
541 ao_gpio1: gpio@fffff52000 {
542 compatible = "snps,dw-apb-gpio";
543 reg = <0xff 0xfff52000 0x0 0x1000>;
544 #address-cells = <1>;
545 #size-cells = <0>;
546
547 portf: gpio-controller@0 {
548 compatible = "snps,dw-apb-gpio-port";
549 gpio-controller;
550 #gpio-cells = <2>;
551 ngpios = <32>;
552 reg = <0>;
553 interrupt-controller;
554 #interrupt-cells = <2>;
555 interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
556 };
557 };
558 };
559 };
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