1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copied from arch/arm64/include/asm/hwcap.h
4 *
5 * Copyright (C) 2012 ARM Ltd.
6 * Copyright (C) 2017 SiFive
7 */
8 #ifndef _ASM_RISCV_HWCAP_H
9 #define _ASM_RISCV_HWCAP_H
10
11 #include <uapi/asm/hwcap.h>
12
13 #define RISCV_ISA_EXT_a ('a' - 'a')
14 #define RISCV_ISA_EXT_c ('c' - 'a')
15 #define RISCV_ISA_EXT_d ('d' - 'a')
16 #define RISCV_ISA_EXT_f ('f' - 'a')
17 #define RISCV_ISA_EXT_h ('h' - 'a')
18 #define RISCV_ISA_EXT_i ('i' - 'a')
19 #define RISCV_ISA_EXT_m ('m' - 'a')
20 #define RISCV_ISA_EXT_q ('q' - 'a')
21 #define RISCV_ISA_EXT_v ('v' - 'a')
22
23 /*
24 * These macros represent the logical IDs of each multi-letter RISC-V ISA
25 * extension and are used in the ISA bitmap. The logical IDs start from
26 * RISCV_ISA_EXT_BASE, which allows the 0-25 range to be reserved for single
27 * letter extensions. The maximum, RISCV_ISA_EXT_MAX, is defined in order
28 * to allocate the bitmap and may be increased when necessary.
29 *
30 * New extensions should just be added to the bottom, rather than added
31 * alphabetically, in order to avoid unnecessary shuffling.
32 */
33 #define RISCV_ISA_EXT_BASE 26
34
35 #define RISCV_ISA_EXT_SSCOFPMF 26
36 #define RISCV_ISA_EXT_SSTC 27
37 #define RISCV_ISA_EXT_SVINVAL 28
38 #define RISCV_ISA_EXT_SVPBMT 29
39 #define RISCV_ISA_EXT_ZBB 30
40 #define RISCV_ISA_EXT_ZICBOM 31
41 #define RISCV_ISA_EXT_ZIHINTPAUSE 32
42 #define RISCV_ISA_EXT_SVNAPOT 33
43 #define RISCV_ISA_EXT_ZICBOZ 34
44 #define RISCV_ISA_EXT_SMAIA 35
45 #define RISCV_ISA_EXT_SSAIA 36
46 #define RISCV_ISA_EXT_ZBA 37
47 #define RISCV_ISA_EXT_ZBS 38
48 #define RISCV_ISA_EXT_ZICNTR 39
49 #define RISCV_ISA_EXT_ZICSR 40
50 #define RISCV_ISA_EXT_ZIFENCEI 41
51 #define RISCV_ISA_EXT_ZIHPM 42
52 #define RISCV_ISA_EXT_SMSTATEEN 43
53 #define RISCV_ISA_EXT_ZICOND 44
54 #define RISCV_ISA_EXT_ZBC 45
55 #define RISCV_ISA_EXT_ZBKB 46
56 #define RISCV_ISA_EXT_ZBKC 47
57 #define RISCV_ISA_EXT_ZBKX 48
58 #define RISCV_ISA_EXT_ZKND 49
59 #define RISCV_ISA_EXT_ZKNE 50
60 #define RISCV_ISA_EXT_ZKNH 51
61 #define RISCV_ISA_EXT_ZKR 52
62 #define RISCV_ISA_EXT_ZKSED 53
63 #define RISCV_ISA_EXT_ZKSH 54
64 #define RISCV_ISA_EXT_ZKT 55
65 #define RISCV_ISA_EXT_ZVBB 56
66 #define RISCV_ISA_EXT_ZVBC 57
67 #define RISCV_ISA_EXT_ZVKB 58
68 #define RISCV_ISA_EXT_ZVKG 59
69 #define RISCV_ISA_EXT_ZVKNED 60
70 #define RISCV_ISA_EXT_ZVKNHA 61
71 #define RISCV_ISA_EXT_ZVKNHB 62
72 #define RISCV_ISA_EXT_ZVKSED 63
73 #define RISCV_ISA_EXT_ZVKSH 64
74 #define RISCV_ISA_EXT_ZVKT 65
75 #define RISCV_ISA_EXT_ZFH 66
76 #define RISCV_ISA_EXT_ZFHMIN 67
77 #define RISCV_ISA_EXT_ZIHINTNTL 68
78 #define RISCV_ISA_EXT_ZVFH 69
79 #define RISCV_ISA_EXT_ZVFHMIN 70
80 #define RISCV_ISA_EXT_ZFA 71
81 #define RISCV_ISA_EXT_ZTSO 72
82 #define RISCV_ISA_EXT_ZACAS 73
83 #define RISCV_ISA_EXT_ZVE32X 74
84 #define RISCV_ISA_EXT_ZVE32F 75
85 #define RISCV_ISA_EXT_ZVE64X 76
86 #define RISCV_ISA_EXT_ZVE64F 77
87 #define RISCV_ISA_EXT_ZVE64D 78
88 #define RISCV_ISA_EXT_ZIMOP 79
89 #define RISCV_ISA_EXT_ZCA 80
90 #define RISCV_ISA_EXT_ZCB 81
91 #define RISCV_ISA_EXT_ZCD 82
92 #define RISCV_ISA_EXT_ZCF 83
93 #define RISCV_ISA_EXT_ZCMOP 84
94 #define RISCV_ISA_EXT_ZAWRS 85
95
96 #define RISCV_ISA_EXT_XLINUXENVCFG 127
97
98 #define RISCV_ISA_EXT_MAX 128
99 #define RISCV_ISA_EXT_INVALID U32_MAX
100
101 #ifdef CONFIG_RISCV_M_MODE
102 #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA
103 #else
104 #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA
105 #endif
106
107 #endif /* _ASM_RISCV_HWCAP_H */
108
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