1 /* SPDX-License-Identifier: GPL-2.0 */
2
3 #ifndef _ASM_RISCV_IMAGE_H
4 #define _ASM_RISCV_IMAGE_H
5
6 #define RISCV_IMAGE_MAGIC "RISCV\0\0\0"
7 #define RISCV_IMAGE_MAGIC2 "RSC\x05"
8
9 #define RISCV_IMAGE_FLAG_BE_SHIFT 0
10 #define RISCV_IMAGE_FLAG_BE_MASK 0x1
11
12 #define RISCV_IMAGE_FLAG_LE 0
13 #define RISCV_IMAGE_FLAG_BE 1
14
15 #ifdef CONFIG_CPU_BIG_ENDIAN
16 #error conversion of header fields to LE not yet implemented
17 #else
18 #define __HEAD_FLAG_BE RISCV_IMAGE_FLAG_LE
19 #endif
20
21 #define __HEAD_FLAG(field) (__HEAD_FLAG_##field << \
22 RISCV_IMAGE_FLAG_##field##_SHIFT)
23
24 #define __HEAD_FLAGS (__HEAD_FLAG(BE))
25
26 #define RISCV_HEADER_VERSION_MAJOR 0
27 #define RISCV_HEADER_VERSION_MINOR 2
28
29 #define RISCV_HEADER_VERSION (RISCV_HEADER_VERSION_MAJOR << 16 | \
30 RISCV_HEADER_VERSION_MINOR)
31
32 #ifndef __ASSEMBLY__
33 /**
34 * struct riscv_image_header - riscv kernel image header
35 * @code0: Executable code
36 * @code1: Executable code
37 * @text_offset: Image load offset (little endian)
38 * @image_size: Effective Image size (little endian)
39 * @flags: kernel flags (little endian)
40 * @version: version
41 * @res1: reserved
42 * @res2: reserved
43 * @magic: Magic number (RISC-V specific; deprecated)
44 * @magic2: Magic number 2 (to match the ARM64 'magic' field pos)
45 * @res3: reserved (will be used for PE COFF offset)
46 *
47 * The intention is for this header format to be shared between multiple
48 * architectures to avoid a proliferation of image header formats.
49 */
50
51 struct riscv_image_header {
52 u32 code0;
53 u32 code1;
54 u64 text_offset;
55 u64 image_size;
56 u64 flags;
57 u32 version;
58 u32 res1;
59 u64 res2;
60 u64 magic;
61 u32 magic2;
62 u32 res3;
63 };
64 #endif /* __ASSEMBLY__ */
65 #endif /* _ASM_RISCV_IMAGE_H */
66
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