1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012 Regents of the University of California
4 */
5
6 #ifndef _ASM_RISCV_PGTABLE_H
7 #define _ASM_RISCV_PGTABLE_H
8
9 #include <linux/mmzone.h>
10 #include <linux/sizes.h>
11
12 #include <asm/pgtable-bits.h>
13
14 #ifndef CONFIG_MMU
15 #define KERNEL_LINK_ADDR PAGE_OFFSET
16 #define KERN_VIRT_SIZE (UL(-1))
17 #else
18
19 #define ADDRESS_SPACE_END (UL(-1))
20
21 #ifdef CONFIG_64BIT
22 /* Leave 2GB for kernel and BPF at the end of the address space */
23 #define KERNEL_LINK_ADDR (ADDRESS_SPACE_END - SZ_2G + 1)
24 #else
25 #define KERNEL_LINK_ADDR PAGE_OFFSET
26 #endif
27
28 /* Number of entries in the page global directory */
29 #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t))
30 /* Number of entries in the page table */
31 #define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t))
32
33 /*
34 * Half of the kernel address space (1/4 of the entries of the page global
35 * directory) is for the direct mapping.
36 */
37 #define KERN_VIRT_SIZE ((PTRS_PER_PGD / 2 * PGDIR_SIZE) / 2)
38
39 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1)
40 #define VMALLOC_END PAGE_OFFSET
41 #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE)
42
43 #define BPF_JIT_REGION_SIZE (SZ_128M)
44 #ifdef CONFIG_64BIT
45 #define BPF_JIT_REGION_START (BPF_JIT_REGION_END - BPF_JIT_REGION_SIZE)
46 #define BPF_JIT_REGION_END (MODULES_END)
47 #else
48 #define BPF_JIT_REGION_START (PAGE_OFFSET - BPF_JIT_REGION_SIZE)
49 #define BPF_JIT_REGION_END (VMALLOC_END)
50 #endif
51
52 /* Modules always live before the kernel */
53 #ifdef CONFIG_64BIT
54 /* This is used to define the end of the KASAN shadow region */
55 #define MODULES_LOWEST_VADDR (KERNEL_LINK_ADDR - SZ_2G)
56 #define MODULES_VADDR (PFN_ALIGN((unsigned long)&_end) - SZ_2G)
57 #define MODULES_END (PFN_ALIGN((unsigned long)&_start))
58 #else
59 #define MODULES_VADDR VMALLOC_START
60 #define MODULES_END VMALLOC_END
61 #endif
62
63 /*
64 * Roughly size the vmemmap space to be large enough to fit enough
65 * struct pages to map half the virtual address space. Then
66 * position vmemmap directly below the VMALLOC region.
67 */
68 #define VA_BITS_SV32 32
69 #ifdef CONFIG_64BIT
70 #define VA_BITS_SV39 39
71 #define VA_BITS_SV48 48
72 #define VA_BITS_SV57 57
73
74 #define VA_BITS (pgtable_l5_enabled ? \
75 VA_BITS_SV57 : (pgtable_l4_enabled ? VA_BITS_SV48 : VA_BITS_SV39))
76 #else
77 #define VA_BITS VA_BITS_SV32
78 #endif
79
80 #define VMEMMAP_SHIFT \
81 (VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT)
82 #define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT)
83 #define VMEMMAP_END VMALLOC_START
84 #define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE)
85
86 /*
87 * Define vmemmap for pfn_to_page & page_to_pfn calls. Needed if kernel
88 * is configured with CONFIG_SPARSEMEM_VMEMMAP enabled.
89 */
90 #define vmemmap ((struct page *)VMEMMAP_START - (phys_ram_base >> PAGE_SHIFT))
91
92 #define PCI_IO_SIZE SZ_16M
93 #define PCI_IO_END VMEMMAP_START
94 #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE)
95
96 #define FIXADDR_TOP PCI_IO_START
97 #ifdef CONFIG_64BIT
98 #define MAX_FDT_SIZE PMD_SIZE
99 #define FIX_FDT_SIZE (MAX_FDT_SIZE + SZ_2M)
100 #define FIXADDR_SIZE (PMD_SIZE + FIX_FDT_SIZE)
101 #else
102 #define MAX_FDT_SIZE PGDIR_SIZE
103 #define FIX_FDT_SIZE MAX_FDT_SIZE
104 #define FIXADDR_SIZE (PGDIR_SIZE + FIX_FDT_SIZE)
105 #endif
106 #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
107
108 #endif
109
110 #ifdef CONFIG_XIP_KERNEL
111 #define XIP_OFFSET SZ_32M
112 #define XIP_OFFSET_MASK (SZ_32M - 1)
113 #else
114 #define XIP_OFFSET 0
115 #endif
116
117 #ifndef __ASSEMBLY__
118
119 #include <asm/page.h>
120 #include <asm/tlbflush.h>
121 #include <linux/mm_types.h>
122 #include <asm/compat.h>
123
124 #define __page_val_to_pfn(_val) (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT)
125
126 #ifdef CONFIG_64BIT
127 #include <asm/pgtable-64.h>
128
129 #define VA_USER_SV39 (UL(1) << (VA_BITS_SV39 - 1))
130 #define VA_USER_SV48 (UL(1) << (VA_BITS_SV48 - 1))
131 #define VA_USER_SV57 (UL(1) << (VA_BITS_SV57 - 1))
132
133 #define MMAP_VA_BITS_64 ((VA_BITS >= VA_BITS_SV48) ? VA_BITS_SV48 : VA_BITS)
134 #define MMAP_MIN_VA_BITS_64 (VA_BITS_SV39)
135 #define MMAP_VA_BITS (is_compat_task() ? VA_BITS_SV32 : MMAP_VA_BITS_64)
136 #define MMAP_MIN_VA_BITS (is_compat_task() ? VA_BITS_SV32 : MMAP_MIN_VA_BITS_64)
137 #else
138 #include <asm/pgtable-32.h>
139 #endif /* CONFIG_64BIT */
140
141 #include <linux/page_table_check.h>
142
143 #ifdef CONFIG_XIP_KERNEL
144 #define XIP_FIXUP(addr) ({ \
145 uintptr_t __a = (uintptr_t)(addr); \
146 (__a >= CONFIG_XIP_PHYS_ADDR && \
147 __a < CONFIG_XIP_PHYS_ADDR + XIP_OFFSET * 2) ? \
148 __a - CONFIG_XIP_PHYS_ADDR + CONFIG_PHYS_RAM_BASE - XIP_OFFSET :\
149 __a; \
150 })
151 #else
152 #define XIP_FIXUP(addr) (addr)
153 #endif /* CONFIG_XIP_KERNEL */
154
155 struct pt_alloc_ops {
156 pte_t *(*get_pte_virt)(phys_addr_t pa);
157 phys_addr_t (*alloc_pte)(uintptr_t va);
158 #ifndef __PAGETABLE_PMD_FOLDED
159 pmd_t *(*get_pmd_virt)(phys_addr_t pa);
160 phys_addr_t (*alloc_pmd)(uintptr_t va);
161 pud_t *(*get_pud_virt)(phys_addr_t pa);
162 phys_addr_t (*alloc_pud)(uintptr_t va);
163 p4d_t *(*get_p4d_virt)(phys_addr_t pa);
164 phys_addr_t (*alloc_p4d)(uintptr_t va);
165 #endif
166 };
167
168 extern struct pt_alloc_ops pt_ops __meminitdata;
169
170 #ifdef CONFIG_MMU
171 /* Number of PGD entries that a user-mode program can use */
172 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
173
174 /* Page protection bits */
175 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER)
176
177 #define PAGE_NONE __pgprot(_PAGE_PROT_NONE | _PAGE_READ)
178 #define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ)
179 #define PAGE_WRITE __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE)
180 #define PAGE_EXEC __pgprot(_PAGE_BASE | _PAGE_EXEC)
181 #define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
182 #define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \
183 _PAGE_EXEC | _PAGE_WRITE)
184
185 #define PAGE_COPY PAGE_READ
186 #define PAGE_COPY_EXEC PAGE_READ_EXEC
187 #define PAGE_SHARED PAGE_WRITE
188 #define PAGE_SHARED_EXEC PAGE_WRITE_EXEC
189
190 #define _PAGE_KERNEL (_PAGE_READ \
191 | _PAGE_WRITE \
192 | _PAGE_PRESENT \
193 | _PAGE_ACCESSED \
194 | _PAGE_DIRTY \
195 | _PAGE_GLOBAL)
196
197 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
198 #define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE)
199 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC)
200 #define PAGE_KERNEL_READ_EXEC __pgprot((_PAGE_KERNEL & ~_PAGE_WRITE) \
201 | _PAGE_EXEC)
202
203 #define PAGE_TABLE __pgprot(_PAGE_TABLE)
204
205 #define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO)
206 #define PAGE_KERNEL_IO __pgprot(_PAGE_IOREMAP)
207
208 extern pgd_t swapper_pg_dir[];
209 extern pgd_t trampoline_pg_dir[];
210 extern pgd_t early_pg_dir[];
211
212 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
213 static inline int pmd_present(pmd_t pmd)
214 {
215 /*
216 * Checking for _PAGE_LEAF is needed too because:
217 * When splitting a THP, split_huge_page() will temporarily clear
218 * the present bit, in this situation, pmd_present() and
219 * pmd_trans_huge() still needs to return true.
220 */
221 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE | _PAGE_LEAF));
222 }
223 #else
224 static inline int pmd_present(pmd_t pmd)
225 {
226 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE));
227 }
228 #endif
229
230 static inline int pmd_none(pmd_t pmd)
231 {
232 return (pmd_val(pmd) == 0);
233 }
234
235 static inline int pmd_bad(pmd_t pmd)
236 {
237 return !pmd_present(pmd) || (pmd_val(pmd) & _PAGE_LEAF);
238 }
239
240 #define pmd_leaf pmd_leaf
241 static inline bool pmd_leaf(pmd_t pmd)
242 {
243 return pmd_present(pmd) && (pmd_val(pmd) & _PAGE_LEAF);
244 }
245
246 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
247 {
248 WRITE_ONCE(*pmdp, pmd);
249 }
250
251 static inline void pmd_clear(pmd_t *pmdp)
252 {
253 set_pmd(pmdp, __pmd(0));
254 }
255
256 static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot)
257 {
258 unsigned long prot_val = pgprot_val(prot);
259
260 ALT_THEAD_PMA(prot_val);
261
262 return __pgd((pfn << _PAGE_PFN_SHIFT) | prot_val);
263 }
264
265 static inline unsigned long _pgd_pfn(pgd_t pgd)
266 {
267 return __page_val_to_pfn(pgd_val(pgd));
268 }
269
270 static inline struct page *pmd_page(pmd_t pmd)
271 {
272 return pfn_to_page(__page_val_to_pfn(pmd_val(pmd)));
273 }
274
275 static inline unsigned long pmd_page_vaddr(pmd_t pmd)
276 {
277 return (unsigned long)pfn_to_virt(__page_val_to_pfn(pmd_val(pmd)));
278 }
279
280 static inline pte_t pmd_pte(pmd_t pmd)
281 {
282 return __pte(pmd_val(pmd));
283 }
284
285 static inline pte_t pud_pte(pud_t pud)
286 {
287 return __pte(pud_val(pud));
288 }
289
290 #ifdef CONFIG_RISCV_ISA_SVNAPOT
291 #include <asm/cpufeature.h>
292
293 static __always_inline bool has_svnapot(void)
294 {
295 return riscv_has_extension_likely(RISCV_ISA_EXT_SVNAPOT);
296 }
297
298 static inline unsigned long pte_napot(pte_t pte)
299 {
300 return pte_val(pte) & _PAGE_NAPOT;
301 }
302
303 static inline pte_t pte_mknapot(pte_t pte, unsigned int order)
304 {
305 int pos = order - 1 + _PAGE_PFN_SHIFT;
306 unsigned long napot_bit = BIT(pos);
307 unsigned long napot_mask = ~GENMASK(pos, _PAGE_PFN_SHIFT);
308
309 return __pte((pte_val(pte) & napot_mask) | napot_bit | _PAGE_NAPOT);
310 }
311
312 #else
313
314 static __always_inline bool has_svnapot(void) { return false; }
315
316 static inline unsigned long pte_napot(pte_t pte)
317 {
318 return 0;
319 }
320
321 #endif /* CONFIG_RISCV_ISA_SVNAPOT */
322
323 /* Yields the page frame number (PFN) of a page table entry */
324 static inline unsigned long pte_pfn(pte_t pte)
325 {
326 unsigned long res = __page_val_to_pfn(pte_val(pte));
327
328 if (has_svnapot() && pte_napot(pte))
329 res = res & (res - 1UL);
330
331 return res;
332 }
333
334 #define pte_page(x) pfn_to_page(pte_pfn(x))
335
336 /* Constructs a page table entry */
337 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
338 {
339 unsigned long prot_val = pgprot_val(prot);
340
341 ALT_THEAD_PMA(prot_val);
342
343 return __pte((pfn << _PAGE_PFN_SHIFT) | prot_val);
344 }
345
346 #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
347
348 static inline int pte_present(pte_t pte)
349 {
350 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE));
351 }
352
353 #define pte_accessible pte_accessible
354 static inline unsigned long pte_accessible(struct mm_struct *mm, pte_t a)
355 {
356 if (pte_val(a) & _PAGE_PRESENT)
357 return true;
358
359 if ((pte_val(a) & _PAGE_PROT_NONE) &&
360 atomic_read(&mm->tlb_flush_pending))
361 return true;
362
363 return false;
364 }
365
366 static inline int pte_none(pte_t pte)
367 {
368 return (pte_val(pte) == 0);
369 }
370
371 static inline int pte_write(pte_t pte)
372 {
373 return pte_val(pte) & _PAGE_WRITE;
374 }
375
376 static inline int pte_exec(pte_t pte)
377 {
378 return pte_val(pte) & _PAGE_EXEC;
379 }
380
381 static inline int pte_user(pte_t pte)
382 {
383 return pte_val(pte) & _PAGE_USER;
384 }
385
386 static inline int pte_huge(pte_t pte)
387 {
388 return pte_present(pte) && (pte_val(pte) & _PAGE_LEAF);
389 }
390
391 static inline int pte_dirty(pte_t pte)
392 {
393 return pte_val(pte) & _PAGE_DIRTY;
394 }
395
396 static inline int pte_young(pte_t pte)
397 {
398 return pte_val(pte) & _PAGE_ACCESSED;
399 }
400
401 static inline int pte_special(pte_t pte)
402 {
403 return pte_val(pte) & _PAGE_SPECIAL;
404 }
405
406 #ifdef CONFIG_ARCH_HAS_PTE_DEVMAP
407 static inline int pte_devmap(pte_t pte)
408 {
409 return pte_val(pte) & _PAGE_DEVMAP;
410 }
411 #endif
412
413 /* static inline pte_t pte_rdprotect(pte_t pte) */
414
415 static inline pte_t pte_wrprotect(pte_t pte)
416 {
417 return __pte(pte_val(pte) & ~(_PAGE_WRITE));
418 }
419
420 /* static inline pte_t pte_mkread(pte_t pte) */
421
422 static inline pte_t pte_mkwrite_novma(pte_t pte)
423 {
424 return __pte(pte_val(pte) | _PAGE_WRITE);
425 }
426
427 /* static inline pte_t pte_mkexec(pte_t pte) */
428
429 static inline pte_t pte_mkdirty(pte_t pte)
430 {
431 return __pte(pte_val(pte) | _PAGE_DIRTY);
432 }
433
434 static inline pte_t pte_mkclean(pte_t pte)
435 {
436 return __pte(pte_val(pte) & ~(_PAGE_DIRTY));
437 }
438
439 static inline pte_t pte_mkyoung(pte_t pte)
440 {
441 return __pte(pte_val(pte) | _PAGE_ACCESSED);
442 }
443
444 static inline pte_t pte_mkold(pte_t pte)
445 {
446 return __pte(pte_val(pte) & ~(_PAGE_ACCESSED));
447 }
448
449 static inline pte_t pte_mkspecial(pte_t pte)
450 {
451 return __pte(pte_val(pte) | _PAGE_SPECIAL);
452 }
453
454 static inline pte_t pte_mkdevmap(pte_t pte)
455 {
456 return __pte(pte_val(pte) | _PAGE_DEVMAP);
457 }
458
459 static inline pte_t pte_mkhuge(pte_t pte)
460 {
461 return pte;
462 }
463
464 #ifdef CONFIG_RISCV_ISA_SVNAPOT
465 #define pte_leaf_size(pte) (pte_napot(pte) ? \
466 napot_cont_size(napot_cont_order(pte)) :\
467 PAGE_SIZE)
468 #endif
469
470 #ifdef CONFIG_NUMA_BALANCING
471 /*
472 * See the comment in include/asm-generic/pgtable.h
473 */
474 static inline int pte_protnone(pte_t pte)
475 {
476 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)) == _PAGE_PROT_NONE;
477 }
478
479 static inline int pmd_protnone(pmd_t pmd)
480 {
481 return pte_protnone(pmd_pte(pmd));
482 }
483 #endif
484
485 /* Modify page protection bits */
486 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
487 {
488 unsigned long newprot_val = pgprot_val(newprot);
489
490 ALT_THEAD_PMA(newprot_val);
491
492 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | newprot_val);
493 }
494
495 #define pgd_ERROR(e) \
496 pr_err("%s:%d: bad pgd " PTE_FMT ".\n", __FILE__, __LINE__, pgd_val(e))
497
498
499 /* Commit new configuration to MMU hardware */
500 static inline void update_mmu_cache_range(struct vm_fault *vmf,
501 struct vm_area_struct *vma, unsigned long address,
502 pte_t *ptep, unsigned int nr)
503 {
504 /*
505 * The kernel assumes that TLBs don't cache invalid entries, but
506 * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a
507 * cache flush; it is necessary even after writing invalid entries.
508 * Relying on flush_tlb_fix_spurious_fault would suffice, but
509 * the extra traps reduce performance. So, eagerly SFENCE.VMA.
510 */
511 while (nr--)
512 local_flush_tlb_page(address + nr * PAGE_SIZE);
513 }
514 #define update_mmu_cache(vma, addr, ptep) \
515 update_mmu_cache_range(NULL, vma, addr, ptep, 1)
516
517 #define update_mmu_tlb_range(vma, addr, ptep, nr) \
518 update_mmu_cache_range(NULL, vma, addr, ptep, nr)
519
520 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
521 unsigned long address, pmd_t *pmdp)
522 {
523 pte_t *ptep = (pte_t *)pmdp;
524
525 update_mmu_cache(vma, address, ptep);
526 }
527
528 #define __HAVE_ARCH_PTE_SAME
529 static inline int pte_same(pte_t pte_a, pte_t pte_b)
530 {
531 return pte_val(pte_a) == pte_val(pte_b);
532 }
533
534 /*
535 * Certain architectures need to do special things when PTEs within
536 * a page table are directly modified. Thus, the following hook is
537 * made available.
538 */
539 static inline void set_pte(pte_t *ptep, pte_t pteval)
540 {
541 WRITE_ONCE(*ptep, pteval);
542 }
543
544 void flush_icache_pte(struct mm_struct *mm, pte_t pte);
545
546 static inline void __set_pte_at(struct mm_struct *mm, pte_t *ptep, pte_t pteval)
547 {
548 if (pte_present(pteval) && pte_exec(pteval))
549 flush_icache_pte(mm, pteval);
550
551 set_pte(ptep, pteval);
552 }
553
554 #define PFN_PTE_SHIFT _PAGE_PFN_SHIFT
555
556 static inline void set_ptes(struct mm_struct *mm, unsigned long addr,
557 pte_t *ptep, pte_t pteval, unsigned int nr)
558 {
559 page_table_check_ptes_set(mm, ptep, pteval, nr);
560
561 for (;;) {
562 __set_pte_at(mm, ptep, pteval);
563 if (--nr == 0)
564 break;
565 ptep++;
566 pte_val(pteval) += 1 << _PAGE_PFN_SHIFT;
567 }
568 }
569 #define set_ptes set_ptes
570
571 static inline void pte_clear(struct mm_struct *mm,
572 unsigned long addr, pte_t *ptep)
573 {
574 __set_pte_at(mm, ptep, __pte(0));
575 }
576
577 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS /* defined in mm/pgtable.c */
578 extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
579 pte_t *ptep, pte_t entry, int dirty);
580 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG /* defined in mm/pgtable.c */
581 extern int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long address,
582 pte_t *ptep);
583
584 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
585 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
586 unsigned long address, pte_t *ptep)
587 {
588 pte_t pte = __pte(atomic_long_xchg((atomic_long_t *)ptep, 0));
589
590 page_table_check_pte_clear(mm, pte);
591
592 return pte;
593 }
594
595 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
596 static inline void ptep_set_wrprotect(struct mm_struct *mm,
597 unsigned long address, pte_t *ptep)
598 {
599 atomic_long_and(~(unsigned long)_PAGE_WRITE, (atomic_long_t *)ptep);
600 }
601
602 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
603 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
604 unsigned long address, pte_t *ptep)
605 {
606 /*
607 * This comment is borrowed from x86, but applies equally to RISC-V:
608 *
609 * Clearing the accessed bit without a TLB flush
610 * doesn't cause data corruption. [ It could cause incorrect
611 * page aging and the (mistaken) reclaim of hot pages, but the
612 * chance of that should be relatively low. ]
613 *
614 * So as a performance optimization don't flush the TLB when
615 * clearing the accessed bit, it will eventually be flushed by
616 * a context switch or a VM operation anyway. [ In the rare
617 * event of it not getting flushed for a long time the delay
618 * shouldn't really matter because there's no real memory
619 * pressure for swapout to react to. ]
620 */
621 return ptep_test_and_clear_young(vma, address, ptep);
622 }
623
624 #define pgprot_nx pgprot_nx
625 static inline pgprot_t pgprot_nx(pgprot_t _prot)
626 {
627 return __pgprot(pgprot_val(_prot) & ~_PAGE_EXEC);
628 }
629
630 #define pgprot_noncached pgprot_noncached
631 static inline pgprot_t pgprot_noncached(pgprot_t _prot)
632 {
633 unsigned long prot = pgprot_val(_prot);
634
635 prot &= ~_PAGE_MTMASK;
636 prot |= _PAGE_IO;
637
638 return __pgprot(prot);
639 }
640
641 #define pgprot_writecombine pgprot_writecombine
642 static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
643 {
644 unsigned long prot = pgprot_val(_prot);
645
646 prot &= ~_PAGE_MTMASK;
647 prot |= _PAGE_NOCACHE;
648
649 return __pgprot(prot);
650 }
651
652 /*
653 * THP functions
654 */
655 static inline pmd_t pte_pmd(pte_t pte)
656 {
657 return __pmd(pte_val(pte));
658 }
659
660 static inline pmd_t pmd_mkhuge(pmd_t pmd)
661 {
662 return pmd;
663 }
664
665 static inline pmd_t pmd_mkinvalid(pmd_t pmd)
666 {
667 return __pmd(pmd_val(pmd) & ~(_PAGE_PRESENT|_PAGE_PROT_NONE));
668 }
669
670 #define __pmd_to_phys(pmd) (__page_val_to_pfn(pmd_val(pmd)) << PAGE_SHIFT)
671
672 static inline unsigned long pmd_pfn(pmd_t pmd)
673 {
674 return ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT);
675 }
676
677 #define __pud_to_phys(pud) (__page_val_to_pfn(pud_val(pud)) << PAGE_SHIFT)
678
679 #define pud_pfn pud_pfn
680 static inline unsigned long pud_pfn(pud_t pud)
681 {
682 return ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT);
683 }
684
685 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
686 {
687 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
688 }
689
690 #define pmd_write pmd_write
691 static inline int pmd_write(pmd_t pmd)
692 {
693 return pte_write(pmd_pte(pmd));
694 }
695
696 #define pud_write pud_write
697 static inline int pud_write(pud_t pud)
698 {
699 return pte_write(pud_pte(pud));
700 }
701
702 #define pmd_dirty pmd_dirty
703 static inline int pmd_dirty(pmd_t pmd)
704 {
705 return pte_dirty(pmd_pte(pmd));
706 }
707
708 #define pmd_young pmd_young
709 static inline int pmd_young(pmd_t pmd)
710 {
711 return pte_young(pmd_pte(pmd));
712 }
713
714 static inline int pmd_user(pmd_t pmd)
715 {
716 return pte_user(pmd_pte(pmd));
717 }
718
719 static inline pmd_t pmd_mkold(pmd_t pmd)
720 {
721 return pte_pmd(pte_mkold(pmd_pte(pmd)));
722 }
723
724 static inline pmd_t pmd_mkyoung(pmd_t pmd)
725 {
726 return pte_pmd(pte_mkyoung(pmd_pte(pmd)));
727 }
728
729 static inline pmd_t pmd_mkwrite_novma(pmd_t pmd)
730 {
731 return pte_pmd(pte_mkwrite_novma(pmd_pte(pmd)));
732 }
733
734 static inline pmd_t pmd_wrprotect(pmd_t pmd)
735 {
736 return pte_pmd(pte_wrprotect(pmd_pte(pmd)));
737 }
738
739 static inline pmd_t pmd_mkclean(pmd_t pmd)
740 {
741 return pte_pmd(pte_mkclean(pmd_pte(pmd)));
742 }
743
744 static inline pmd_t pmd_mkdirty(pmd_t pmd)
745 {
746 return pte_pmd(pte_mkdirty(pmd_pte(pmd)));
747 }
748
749 static inline pmd_t pmd_mkdevmap(pmd_t pmd)
750 {
751 return pte_pmd(pte_mkdevmap(pmd_pte(pmd)));
752 }
753
754 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
755 pmd_t *pmdp, pmd_t pmd)
756 {
757 page_table_check_pmd_set(mm, pmdp, pmd);
758 return __set_pte_at(mm, (pte_t *)pmdp, pmd_pte(pmd));
759 }
760
761 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr,
762 pud_t *pudp, pud_t pud)
763 {
764 page_table_check_pud_set(mm, pudp, pud);
765 return __set_pte_at(mm, (pte_t *)pudp, pud_pte(pud));
766 }
767
768 #ifdef CONFIG_PAGE_TABLE_CHECK
769 static inline bool pte_user_accessible_page(pte_t pte)
770 {
771 return pte_present(pte) && pte_user(pte);
772 }
773
774 static inline bool pmd_user_accessible_page(pmd_t pmd)
775 {
776 return pmd_leaf(pmd) && pmd_user(pmd);
777 }
778
779 static inline bool pud_user_accessible_page(pud_t pud)
780 {
781 return pud_leaf(pud) && pud_user(pud);
782 }
783 #endif
784
785 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
786 static inline int pmd_trans_huge(pmd_t pmd)
787 {
788 return pmd_leaf(pmd);
789 }
790
791 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
792 static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
793 unsigned long address, pmd_t *pmdp,
794 pmd_t entry, int dirty)
795 {
796 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty);
797 }
798
799 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
800 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
801 unsigned long address, pmd_t *pmdp)
802 {
803 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
804 }
805
806 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
807 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
808 unsigned long address, pmd_t *pmdp)
809 {
810 pmd_t pmd = __pmd(atomic_long_xchg((atomic_long_t *)pmdp, 0));
811
812 page_table_check_pmd_clear(mm, pmd);
813
814 return pmd;
815 }
816
817 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
818 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
819 unsigned long address, pmd_t *pmdp)
820 {
821 ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
822 }
823
824 #define pmdp_establish pmdp_establish
825 static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
826 unsigned long address, pmd_t *pmdp, pmd_t pmd)
827 {
828 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd);
829 return __pmd(atomic_long_xchg((atomic_long_t *)pmdp, pmd_val(pmd)));
830 }
831
832 #define pmdp_collapse_flush pmdp_collapse_flush
833 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
834 unsigned long address, pmd_t *pmdp);
835 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
836
837 /*
838 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
839 * are !pte_none() && !pte_present().
840 *
841 * Format of swap PTE:
842 * bit 0: _PAGE_PRESENT (zero)
843 * bit 1 to 3: _PAGE_LEAF (zero)
844 * bit 5: _PAGE_PROT_NONE (zero)
845 * bit 6: exclusive marker
846 * bits 7 to 11: swap type
847 * bits 12 to XLEN-1: swap offset
848 */
849 #define __SWP_TYPE_SHIFT 7
850 #define __SWP_TYPE_BITS 5
851 #define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1)
852 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
853
854 #define MAX_SWAPFILES_CHECK() \
855 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
856
857 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
858 #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT)
859 #define __swp_entry(type, offset) ((swp_entry_t) \
860 { (((type) & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT) | \
861 ((offset) << __SWP_OFFSET_SHIFT) })
862
863 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
864 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
865
866 static inline int pte_swp_exclusive(pte_t pte)
867 {
868 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
869 }
870
871 static inline pte_t pte_swp_mkexclusive(pte_t pte)
872 {
873 return __pte(pte_val(pte) | _PAGE_SWP_EXCLUSIVE);
874 }
875
876 static inline pte_t pte_swp_clear_exclusive(pte_t pte)
877 {
878 return __pte(pte_val(pte) & ~_PAGE_SWP_EXCLUSIVE);
879 }
880
881 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
882 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) })
883 #define __swp_entry_to_pmd(swp) __pmd((swp).val)
884 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
885
886 /*
887 * In the RV64 Linux scheme, we give the user half of the virtual-address space
888 * and give the kernel the other (upper) half.
889 */
890 #ifdef CONFIG_64BIT
891 #define KERN_VIRT_START (-(BIT(VA_BITS)) + TASK_SIZE)
892 #else
893 #define KERN_VIRT_START FIXADDR_START
894 #endif
895
896 /*
897 * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32.
898 * Note that PGDIR_SIZE must evenly divide TASK_SIZE.
899 * Task size is:
900 * - 0x9fc00000 (~2.5GB) for RV32.
901 * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu
902 * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu
903 * - 0x100000000000000 ( 64PB) for RV64 using SV57 mmu
904 *
905 * Note that PGDIR_SIZE must evenly divide TASK_SIZE since "RISC-V
906 * Instruction Set Manual Volume II: Privileged Architecture" states that
907 * "load and store effective addresses, which are 64bits, must have bits
908 * 63–48 all equal to bit 47, or else a page-fault exception will occur."
909 * Similarly for SV57, bits 63–57 must be equal to bit 56.
910 */
911 #ifdef CONFIG_64BIT
912 #define TASK_SIZE_64 (PGDIR_SIZE * PTRS_PER_PGD / 2)
913 #define TASK_SIZE_MAX LONG_MAX
914
915 #ifdef CONFIG_COMPAT
916 #define TASK_SIZE_32 (_AC(0x80000000, UL) - PAGE_SIZE)
917 #define TASK_SIZE (is_compat_task() ? \
918 TASK_SIZE_32 : TASK_SIZE_64)
919 #else
920 #define TASK_SIZE TASK_SIZE_64
921 #endif
922
923 #else
924 #define TASK_SIZE FIXADDR_START
925 #endif
926
927 #else /* CONFIG_MMU */
928
929 #define PAGE_SHARED __pgprot(0)
930 #define PAGE_KERNEL __pgprot(0)
931 #define swapper_pg_dir NULL
932 #define TASK_SIZE _AC(-1, UL)
933 #define VMALLOC_START _AC(0, UL)
934 #define VMALLOC_END TASK_SIZE
935
936 #endif /* !CONFIG_MMU */
937
938 extern char _start[];
939 extern void *_dtb_early_va;
940 extern uintptr_t _dtb_early_pa;
941 #if defined(CONFIG_XIP_KERNEL) && defined(CONFIG_MMU)
942 #define dtb_early_va (*(void **)XIP_FIXUP(&_dtb_early_va))
943 #define dtb_early_pa (*(uintptr_t *)XIP_FIXUP(&_dtb_early_pa))
944 #else
945 #define dtb_early_va _dtb_early_va
946 #define dtb_early_pa _dtb_early_pa
947 #endif /* CONFIG_XIP_KERNEL */
948 extern u64 satp_mode;
949
950 void paging_init(void);
951 void misc_mem_init(void);
952
953 /*
954 * ZERO_PAGE is a global shared page that is always zero,
955 * used for zero-mapped memory areas, etc.
956 */
957 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
958 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
959
960 #endif /* !__ASSEMBLY__ */
961
962 #endif /* _ASM_RISCV_PGTABLE_H */
963
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.