1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_RISCV_SYNC_CORE_H
3 #define _ASM_RISCV_SYNC_CORE_H
4
5 /*
6 * RISC-V implements return to user-space through an xRET instruction,
7 * which is not core serializing.
8 */
9 static inline void sync_core_before_usermode(void)
10 {
11 asm volatile ("fence.i" ::: "memory");
12 }
13
14 #ifdef CONFIG_SMP
15 /*
16 * Ensure the next switch_mm() on every CPU issues a core serializing
17 * instruction for the given @mm.
18 */
19 static inline void prepare_sync_core_cmd(struct mm_struct *mm)
20 {
21 cpumask_setall(&mm->context.icache_stale_mask);
22 }
23 #else
24 static inline void prepare_sync_core_cmd(struct mm_struct *mm)
25 {
26 }
27 #endif /* CONFIG_SMP */
28
29 #endif /* _ASM_RISCV_SYNC_CORE_H */
30
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