1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copied from arch/arm64/kernel/cpufeature.c
4 *
5 * Copyright (C) 2015 ARM Ltd.
6 * Copyright (C) 2017 SiFive
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/bitmap.h>
11 #include <linux/cpu.h>
12 #include <linux/cpuhotplug.h>
13 #include <linux/ctype.h>
14 #include <linux/log2.h>
15 #include <linux/memory.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <asm/acpi.h>
19 #include <asm/alternative.h>
20 #include <asm/cacheflush.h>
21 #include <asm/cpufeature.h>
22 #include <asm/hwcap.h>
23 #include <asm/patch.h>
24 #include <asm/processor.h>
25 #include <asm/sbi.h>
26 #include <asm/vector.h>
27 #include <asm/vendor_extensions.h>
28
29 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
30
31 unsigned long elf_hwcap __read_mostly;
32
33 /* Host ISA bitmap */
34 static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
35
36 /* Per-cpu ISA extensions. */
37 struct riscv_isainfo hart_isa[NR_CPUS];
38
39 /**
40 * riscv_isa_extension_base() - Get base extension word
41 *
42 * @isa_bitmap: ISA bitmap to use
43 * Return: base extension word as unsigned long value
44 *
45 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
46 */
47 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap)
48 {
49 if (!isa_bitmap)
50 return riscv_isa[0];
51 return isa_bitmap[0];
52 }
53 EXPORT_SYMBOL_GPL(riscv_isa_extension_base);
54
55 /**
56 * __riscv_isa_extension_available() - Check whether given extension
57 * is available or not
58 *
59 * @isa_bitmap: ISA bitmap to use
60 * @bit: bit position of the desired extension
61 * Return: true or false
62 *
63 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
64 */
65 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsigned int bit)
66 {
67 const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa;
68
69 if (bit >= RISCV_ISA_EXT_MAX)
70 return false;
71
72 return test_bit(bit, bmap) ? true : false;
73 }
74 EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
75
76 static int riscv_ext_zicbom_validate(const struct riscv_isa_ext_data *data,
77 const unsigned long *isa_bitmap)
78 {
79 if (!riscv_cbom_block_size) {
80 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n");
81 return -EINVAL;
82 }
83 if (!is_power_of_2(riscv_cbom_block_size)) {
84 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n");
85 return -EINVAL;
86 }
87 return 0;
88 }
89
90 static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data,
91 const unsigned long *isa_bitmap)
92 {
93 if (!riscv_cboz_block_size) {
94 pr_err("Zicboz detected in ISA string, disabling as no cboz-block-size found\n");
95 return -EINVAL;
96 }
97 if (!is_power_of_2(riscv_cboz_block_size)) {
98 pr_err("Zicboz disabled as cboz-block-size present, but is not a power-of-2\n");
99 return -EINVAL;
100 }
101 return 0;
102 }
103
104 static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data,
105 const unsigned long *isa_bitmap)
106 {
107 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA))
108 return 0;
109
110 return -EPROBE_DEFER;
111 }
112 static int riscv_ext_zcd_validate(const struct riscv_isa_ext_data *data,
113 const unsigned long *isa_bitmap)
114 {
115 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) &&
116 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d))
117 return 0;
118
119 return -EPROBE_DEFER;
120 }
121
122 static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data,
123 const unsigned long *isa_bitmap)
124 {
125 if (IS_ENABLED(CONFIG_64BIT))
126 return -EINVAL;
127
128 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) &&
129 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f))
130 return 0;
131
132 return -EPROBE_DEFER;
133 }
134
135 static const unsigned int riscv_zk_bundled_exts[] = {
136 RISCV_ISA_EXT_ZBKB,
137 RISCV_ISA_EXT_ZBKC,
138 RISCV_ISA_EXT_ZBKX,
139 RISCV_ISA_EXT_ZKND,
140 RISCV_ISA_EXT_ZKNE,
141 RISCV_ISA_EXT_ZKR,
142 RISCV_ISA_EXT_ZKT,
143 };
144
145 static const unsigned int riscv_zkn_bundled_exts[] = {
146 RISCV_ISA_EXT_ZBKB,
147 RISCV_ISA_EXT_ZBKC,
148 RISCV_ISA_EXT_ZBKX,
149 RISCV_ISA_EXT_ZKND,
150 RISCV_ISA_EXT_ZKNE,
151 RISCV_ISA_EXT_ZKNH,
152 };
153
154 static const unsigned int riscv_zks_bundled_exts[] = {
155 RISCV_ISA_EXT_ZBKB,
156 RISCV_ISA_EXT_ZBKC,
157 RISCV_ISA_EXT_ZKSED,
158 RISCV_ISA_EXT_ZKSH
159 };
160
161 #define RISCV_ISA_EXT_ZVKN \
162 RISCV_ISA_EXT_ZVKNED, \
163 RISCV_ISA_EXT_ZVKNHB, \
164 RISCV_ISA_EXT_ZVKB, \
165 RISCV_ISA_EXT_ZVKT
166
167 static const unsigned int riscv_zvkn_bundled_exts[] = {
168 RISCV_ISA_EXT_ZVKN
169 };
170
171 static const unsigned int riscv_zvknc_bundled_exts[] = {
172 RISCV_ISA_EXT_ZVKN,
173 RISCV_ISA_EXT_ZVBC
174 };
175
176 static const unsigned int riscv_zvkng_bundled_exts[] = {
177 RISCV_ISA_EXT_ZVKN,
178 RISCV_ISA_EXT_ZVKG
179 };
180
181 #define RISCV_ISA_EXT_ZVKS \
182 RISCV_ISA_EXT_ZVKSED, \
183 RISCV_ISA_EXT_ZVKSH, \
184 RISCV_ISA_EXT_ZVKB, \
185 RISCV_ISA_EXT_ZVKT
186
187 static const unsigned int riscv_zvks_bundled_exts[] = {
188 RISCV_ISA_EXT_ZVKS
189 };
190
191 static const unsigned int riscv_zvksc_bundled_exts[] = {
192 RISCV_ISA_EXT_ZVKS,
193 RISCV_ISA_EXT_ZVBC
194 };
195
196 static const unsigned int riscv_zvksg_bundled_exts[] = {
197 RISCV_ISA_EXT_ZVKS,
198 RISCV_ISA_EXT_ZVKG
199 };
200
201 static const unsigned int riscv_zvbb_exts[] = {
202 RISCV_ISA_EXT_ZVKB
203 };
204
205 #define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST \
206 RISCV_ISA_EXT_ZVE64X, \
207 RISCV_ISA_EXT_ZVE32F, \
208 RISCV_ISA_EXT_ZVE32X
209
210 #define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST \
211 RISCV_ISA_EXT_ZVE64F, \
212 RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
213
214 #define RISCV_ISA_EXT_V_IMPLY_LIST \
215 RISCV_ISA_EXT_ZVE64D, \
216 RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
217
218 static const unsigned int riscv_zve32f_exts[] = {
219 RISCV_ISA_EXT_ZVE32X
220 };
221
222 static const unsigned int riscv_zve64f_exts[] = {
223 RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
224 };
225
226 static const unsigned int riscv_zve64d_exts[] = {
227 RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
228 };
229
230 static const unsigned int riscv_v_exts[] = {
231 RISCV_ISA_EXT_V_IMPLY_LIST
232 };
233
234 static const unsigned int riscv_zve64x_exts[] = {
235 RISCV_ISA_EXT_ZVE32X,
236 RISCV_ISA_EXT_ZVE64X
237 };
238
239 /*
240 * While the [ms]envcfg CSRs were not defined until version 1.12 of the RISC-V
241 * privileged ISA, the existence of the CSRs is implied by any extension which
242 * specifies [ms]envcfg bit(s). Hence, we define a custom ISA extension for the
243 * existence of the CSR, and treat it as a subset of those other extensions.
244 */
245 static const unsigned int riscv_xlinuxenvcfg_exts[] = {
246 RISCV_ISA_EXT_XLINUXENVCFG
247 };
248
249 /*
250 * Zc* spec states that:
251 * - C always implies Zca
252 * - C+F implies Zcf (RV32 only)
253 * - C+D implies Zcd
254 *
255 * These extensions will be enabled and then validated depending on the
256 * availability of F/D RV32.
257 */
258 static const unsigned int riscv_c_exts[] = {
259 RISCV_ISA_EXT_ZCA,
260 RISCV_ISA_EXT_ZCF,
261 RISCV_ISA_EXT_ZCD,
262 };
263
264 /*
265 * The canonical order of ISA extension names in the ISA string is defined in
266 * chapter 27 of the unprivileged specification.
267 *
268 * Ordinarily, for in-kernel data structures, this order is unimportant but
269 * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo.
270 *
271 * The specification uses vague wording, such as should, when it comes to
272 * ordering, so for our purposes the following rules apply:
273 *
274 * 1. All multi-letter extensions must be separated from other extensions by an
275 * underscore.
276 *
277 * 2. Additional standard extensions (starting with 'Z') must be sorted after
278 * single-letter extensions and before any higher-privileged extensions.
279 *
280 * 3. The first letter following the 'Z' conventionally indicates the most
281 * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
282 * If multiple 'Z' extensions are named, they must be ordered first by
283 * category, then alphabetically within a category.
284 *
285 * 3. Standard supervisor-level extensions (starting with 'S') must be listed
286 * after standard unprivileged extensions. If multiple supervisor-level
287 * extensions are listed, they must be ordered alphabetically.
288 *
289 * 4. Standard machine-level extensions (starting with 'Zxm') must be listed
290 * after any lower-privileged, standard extensions. If multiple
291 * machine-level extensions are listed, they must be ordered
292 * alphabetically.
293 *
294 * 5. Non-standard extensions (starting with 'X') must be listed after all
295 * standard extensions. If multiple non-standard extensions are listed, they
296 * must be ordered alphabetically.
297 *
298 * An example string following the order is:
299 * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux
300 *
301 * New entries to this struct should follow the ordering rules described above.
302 */
303 const struct riscv_isa_ext_data riscv_isa_ext[] = {
304 __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i),
305 __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m),
306 __RISCV_ISA_EXT_DATA(a, RISCV_ISA_EXT_a),
307 __RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f),
308 __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
309 __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
310 __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts),
311 __RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts),
312 __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
313 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts,
314 riscv_ext_zicbom_validate),
315 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts,
316 riscv_ext_zicboz_validate),
317 __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
318 __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
319 __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),
320 __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),
321 __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL),
322 __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
323 __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
324 __RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP),
325 __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
326 __RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS),
327 __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
328 __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
329 __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
330 __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA),
331 __RISCV_ISA_EXT_DATA_VALIDATE(zcb, RISCV_ISA_EXT_ZCB, riscv_ext_zca_depends),
332 __RISCV_ISA_EXT_DATA_VALIDATE(zcd, RISCV_ISA_EXT_ZCD, riscv_ext_zcd_validate),
333 __RISCV_ISA_EXT_DATA_VALIDATE(zcf, RISCV_ISA_EXT_ZCF, riscv_ext_zcf_validate),
334 __RISCV_ISA_EXT_DATA_VALIDATE(zcmop, RISCV_ISA_EXT_ZCMOP, riscv_ext_zca_depends),
335 __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
336 __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
337 __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
338 __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB),
339 __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC),
340 __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX),
341 __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
342 __RISCV_ISA_EXT_BUNDLE(zk, riscv_zk_bundled_exts),
343 __RISCV_ISA_EXT_BUNDLE(zkn, riscv_zkn_bundled_exts),
344 __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND),
345 __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE),
346 __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH),
347 __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR),
348 __RISCV_ISA_EXT_BUNDLE(zks, riscv_zks_bundled_exts),
349 __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT),
350 __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED),
351 __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH),
352 __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
353 __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
354 __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
355 __RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts),
356 __RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X),
357 __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
358 __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
359 __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),
360 __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
361 __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
362 __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
363 __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG),
364 __RISCV_ISA_EXT_BUNDLE(zvkn, riscv_zvkn_bundled_exts),
365 __RISCV_ISA_EXT_BUNDLE(zvknc, riscv_zvknc_bundled_exts),
366 __RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED),
367 __RISCV_ISA_EXT_BUNDLE(zvkng, riscv_zvkng_bundled_exts),
368 __RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA),
369 __RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB),
370 __RISCV_ISA_EXT_BUNDLE(zvks, riscv_zvks_bundled_exts),
371 __RISCV_ISA_EXT_BUNDLE(zvksc, riscv_zvksc_bundled_exts),
372 __RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED),
373 __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH),
374 __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts),
375 __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT),
376 __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
377 __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
378 __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
379 __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
380 __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
381 __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
382 __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
383 __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
384 };
385
386 const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
387
388 static void riscv_isa_set_ext(const struct riscv_isa_ext_data *ext, unsigned long *bitmap)
389 {
390 if (ext->id != RISCV_ISA_EXT_INVALID)
391 set_bit(ext->id, bitmap);
392
393 for (int i = 0; i < ext->subset_ext_size; i++) {
394 if (ext->subset_ext_ids[i] != RISCV_ISA_EXT_INVALID)
395 set_bit(ext->subset_ext_ids[i], bitmap);
396 }
397 }
398
399 static const struct riscv_isa_ext_data *riscv_get_isa_ext_data(unsigned int ext_id)
400 {
401 for (int i = 0; i < riscv_isa_ext_count; i++) {
402 if (riscv_isa_ext[i].id == ext_id)
403 return &riscv_isa_ext[i];
404 }
405
406 return NULL;
407 }
408
409 /*
410 * "Resolve" a source ISA bitmap into one that matches kernel configuration as
411 * well as correct extension dependencies. Some extensions depends on specific
412 * kernel configuration to be usable (V needs CONFIG_RISCV_ISA_V for instance)
413 * and this function will actually validate all the extensions provided in
414 * source_isa into the resolved_isa based on extensions validate() callbacks.
415 */
416 static void __init riscv_resolve_isa(unsigned long *source_isa,
417 unsigned long *resolved_isa, unsigned long *this_hwcap,
418 unsigned long *isa2hwcap)
419 {
420 bool loop;
421 const struct riscv_isa_ext_data *ext;
422 DECLARE_BITMAP(prev_resolved_isa, RISCV_ISA_EXT_MAX);
423 int max_loop_count = riscv_isa_ext_count, ret;
424 unsigned int bit;
425
426 do {
427 loop = false;
428 if (max_loop_count-- < 0) {
429 pr_err("Failed to reach a stable ISA state\n");
430 return;
431 }
432 bitmap_copy(prev_resolved_isa, resolved_isa, RISCV_ISA_EXT_MAX);
433 for_each_set_bit(bit, source_isa, RISCV_ISA_EXT_MAX) {
434 ext = riscv_get_isa_ext_data(bit);
435
436 if (ext && ext->validate) {
437 ret = ext->validate(ext, resolved_isa);
438 if (ret == -EPROBE_DEFER) {
439 loop = true;
440 continue;
441 } else if (ret) {
442 /* Disable the extension entirely */
443 clear_bit(bit, source_isa);
444 continue;
445 }
446 }
447
448 set_bit(bit, resolved_isa);
449 /* No need to keep it in source isa now that it is enabled */
450 clear_bit(bit, source_isa);
451
452 /* Single letter extensions get set in hwcap */
453 if (bit < RISCV_ISA_EXT_BASE)
454 *this_hwcap |= isa2hwcap[bit];
455 }
456 } while (loop && memcmp(prev_resolved_isa, resolved_isa, sizeof(prev_resolved_isa)));
457 }
458
459 static void __init match_isa_ext(const char *name, const char *name_end, unsigned long *bitmap)
460 {
461 for (int i = 0; i < riscv_isa_ext_count; i++) {
462 const struct riscv_isa_ext_data *ext = &riscv_isa_ext[i];
463
464 if ((name_end - name == strlen(ext->name)) &&
465 !strncasecmp(name, ext->name, name_end - name)) {
466 riscv_isa_set_ext(ext, bitmap);
467 break;
468 }
469 }
470 }
471
472 static void __init riscv_parse_isa_string(const char *isa, unsigned long *bitmap)
473 {
474 /*
475 * For all possible cpus, we have already validated in
476 * the boot process that they at least contain "rv" and
477 * whichever of "32"/"64" this kernel supports, and so this
478 * section can be skipped.
479 */
480 isa += 4;
481
482 while (*isa) {
483 const char *ext = isa++;
484 const char *ext_end = isa;
485 bool ext_err = false;
486
487 switch (*ext) {
488 case 'x':
489 case 'X':
490 if (acpi_disabled)
491 pr_warn_once("Vendor extensions are ignored in riscv,isa. Use riscv,isa-extensions instead.");
492 /*
493 * To skip an extension, we find its end.
494 * As multi-letter extensions must be split from other multi-letter
495 * extensions with an "_", the end of a multi-letter extension will
496 * either be the null character or the "_" at the start of the next
497 * multi-letter extension.
498 */
499 for (; *isa && *isa != '_'; ++isa)
500 ;
501 ext_err = true;
502 break;
503 case 's':
504 /*
505 * Workaround for invalid single-letter 's' & 'u' (QEMU).
506 * No need to set the bit in riscv_isa as 's' & 'u' are
507 * not valid ISA extensions. It works unless the first
508 * multi-letter extension in the ISA string begins with
509 * "Su" and is not prefixed with an underscore.
510 */
511 if (ext[-1] != '_' && ext[1] == 'u') {
512 ++isa;
513 ext_err = true;
514 break;
515 }
516 fallthrough;
517 case 'S':
518 case 'z':
519 case 'Z':
520 /*
521 * Before attempting to parse the extension itself, we find its end.
522 * As multi-letter extensions must be split from other multi-letter
523 * extensions with an "_", the end of a multi-letter extension will
524 * either be the null character or the "_" at the start of the next
525 * multi-letter extension.
526 *
527 * Next, as the extensions version is currently ignored, we
528 * eliminate that portion. This is done by parsing backwards from
529 * the end of the extension, removing any numbers. This may be a
530 * major or minor number however, so the process is repeated if a
531 * minor number was found.
532 *
533 * ext_end is intended to represent the first character *after* the
534 * name portion of an extension, but will be decremented to the last
535 * character itself while eliminating the extensions version number.
536 * A simple re-increment solves this problem.
537 */
538 for (; *isa && *isa != '_'; ++isa)
539 if (unlikely(!isalnum(*isa)))
540 ext_err = true;
541
542 ext_end = isa;
543 if (unlikely(ext_err))
544 break;
545
546 if (!isdigit(ext_end[-1]))
547 break;
548
549 while (isdigit(*--ext_end))
550 ;
551
552 if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) {
553 ++ext_end;
554 break;
555 }
556
557 while (isdigit(*--ext_end))
558 ;
559
560 ++ext_end;
561 break;
562 default:
563 /*
564 * Things are a little easier for single-letter extensions, as they
565 * are parsed forwards.
566 *
567 * After checking that our starting position is valid, we need to
568 * ensure that, when isa was incremented at the start of the loop,
569 * that it arrived at the start of the next extension.
570 *
571 * If we are already on a non-digit, there is nothing to do. Either
572 * we have a multi-letter extension's _, or the start of an
573 * extension.
574 *
575 * Otherwise we have found the current extension's major version
576 * number. Parse past it, and a subsequent p/minor version number
577 * if present. The `p` extension must not appear immediately after
578 * a number, so there is no fear of missing it.
579 *
580 */
581 if (unlikely(!isalpha(*ext))) {
582 ext_err = true;
583 break;
584 }
585
586 if (!isdigit(*isa))
587 break;
588
589 while (isdigit(*++isa))
590 ;
591
592 if (tolower(*isa) != 'p')
593 break;
594
595 if (!isdigit(*++isa)) {
596 --isa;
597 break;
598 }
599
600 while (isdigit(*++isa))
601 ;
602
603 break;
604 }
605
606 /*
607 * The parser expects that at the start of an iteration isa points to the
608 * first character of the next extension. As we stop parsing an extension
609 * on meeting a non-alphanumeric character, an extra increment is needed
610 * where the succeeding extension is a multi-letter prefixed with an "_".
611 */
612 if (*isa == '_')
613 ++isa;
614
615 if (unlikely(ext_err))
616 continue;
617
618 match_isa_ext(ext, ext_end, bitmap);
619 }
620 }
621
622 static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap)
623 {
624 struct device_node *node;
625 const char *isa;
626 int rc;
627 struct acpi_table_header *rhct;
628 acpi_status status;
629 unsigned int cpu;
630 u64 boot_vendorid;
631 u64 boot_archid;
632
633 if (!acpi_disabled) {
634 status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct);
635 if (ACPI_FAILURE(status))
636 return;
637 }
638
639 boot_vendorid = riscv_get_mvendorid();
640 boot_archid = riscv_get_marchid();
641
642 for_each_possible_cpu(cpu) {
643 struct riscv_isainfo *isainfo = &hart_isa[cpu];
644 unsigned long this_hwcap = 0;
645 DECLARE_BITMAP(source_isa, RISCV_ISA_EXT_MAX) = { 0 };
646
647 if (acpi_disabled) {
648 node = of_cpu_device_node_get(cpu);
649 if (!node) {
650 pr_warn("Unable to find cpu node\n");
651 continue;
652 }
653
654 rc = of_property_read_string(node, "riscv,isa", &isa);
655 of_node_put(node);
656 if (rc) {
657 pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
658 continue;
659 }
660 } else {
661 rc = acpi_get_riscv_isa(rhct, cpu, &isa);
662 if (rc < 0) {
663 pr_warn("Unable to get ISA for the hart - %d\n", cpu);
664 continue;
665 }
666 }
667
668 riscv_parse_isa_string(isa, source_isa);
669
670 /*
671 * These ones were as they were part of the base ISA when the
672 * port & dt-bindings were upstreamed, and so can be set
673 * unconditionally where `i` is in riscv,isa on DT systems.
674 */
675 if (acpi_disabled) {
676 set_bit(RISCV_ISA_EXT_ZICSR, source_isa);
677 set_bit(RISCV_ISA_EXT_ZIFENCEI, source_isa);
678 set_bit(RISCV_ISA_EXT_ZICNTR, source_isa);
679 set_bit(RISCV_ISA_EXT_ZIHPM, source_isa);
680 }
681
682 /*
683 * "V" in ISA strings is ambiguous in practice: it should mean
684 * just the standard V-1.0 but vendors aren't well behaved.
685 * Many vendors with T-Head CPU cores which implement the 0.7.1
686 * version of the vector specification put "v" into their DTs.
687 * CPU cores with the ratified spec will contain non-zero
688 * marchid.
689 */
690 if (acpi_disabled && boot_vendorid == THEAD_VENDOR_ID && boot_archid == 0x0) {
691 this_hwcap &= ~isa2hwcap[RISCV_ISA_EXT_v];
692 clear_bit(RISCV_ISA_EXT_v, source_isa);
693 }
694
695 riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap);
696
697 /*
698 * All "okay" hart should have same isa. Set HWCAP based on
699 * common capabilities of every "okay" hart, in case they don't
700 * have.
701 */
702 if (elf_hwcap)
703 elf_hwcap &= this_hwcap;
704 else
705 elf_hwcap = this_hwcap;
706
707 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
708 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
709 else
710 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
711 }
712
713 if (!acpi_disabled && rhct)
714 acpi_put_table((struct acpi_table_header *)rhct);
715 }
716
717 static void __init riscv_fill_cpu_vendor_ext(struct device_node *cpu_node, int cpu)
718 {
719 if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT))
720 return;
721
722 for (int i = 0; i < riscv_isa_vendor_ext_list_size; i++) {
723 struct riscv_isa_vendor_ext_data_list *ext_list = riscv_isa_vendor_ext_list[i];
724
725 for (int j = 0; j < ext_list->ext_data_count; j++) {
726 const struct riscv_isa_ext_data ext = ext_list->ext_data[j];
727 struct riscv_isavendorinfo *isavendorinfo = &ext_list->per_hart_isa_bitmap[cpu];
728
729 if (of_property_match_string(cpu_node, "riscv,isa-extensions",
730 ext.property) < 0)
731 continue;
732
733 /*
734 * Assume that subset extensions are all members of the
735 * same vendor.
736 */
737 if (ext.subset_ext_size)
738 for (int k = 0; k < ext.subset_ext_size; k++)
739 set_bit(ext.subset_ext_ids[k], isavendorinfo->isa);
740
741 set_bit(ext.id, isavendorinfo->isa);
742 }
743 }
744 }
745
746 /*
747 * Populate all_harts_isa_bitmap for each vendor with all of the extensions that
748 * are shared across CPUs for that vendor.
749 */
750 static void __init riscv_fill_vendor_ext_list(int cpu)
751 {
752 if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT))
753 return;
754
755 for (int i = 0; i < riscv_isa_vendor_ext_list_size; i++) {
756 struct riscv_isa_vendor_ext_data_list *ext_list = riscv_isa_vendor_ext_list[i];
757
758 if (!ext_list->is_initialized) {
759 bitmap_copy(ext_list->all_harts_isa_bitmap.isa,
760 ext_list->per_hart_isa_bitmap[cpu].isa,
761 RISCV_ISA_VENDOR_EXT_MAX);
762 ext_list->is_initialized = true;
763 } else {
764 bitmap_and(ext_list->all_harts_isa_bitmap.isa,
765 ext_list->all_harts_isa_bitmap.isa,
766 ext_list->per_hart_isa_bitmap[cpu].isa,
767 RISCV_ISA_VENDOR_EXT_MAX);
768 }
769 }
770 }
771
772 static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap)
773 {
774 unsigned int cpu;
775
776 for_each_possible_cpu(cpu) {
777 unsigned long this_hwcap = 0;
778 struct device_node *cpu_node;
779 struct riscv_isainfo *isainfo = &hart_isa[cpu];
780 DECLARE_BITMAP(source_isa, RISCV_ISA_EXT_MAX) = { 0 };
781
782 cpu_node = of_cpu_device_node_get(cpu);
783 if (!cpu_node) {
784 pr_warn("Unable to find cpu node\n");
785 continue;
786 }
787
788 if (!of_property_present(cpu_node, "riscv,isa-extensions")) {
789 of_node_put(cpu_node);
790 continue;
791 }
792
793 for (int i = 0; i < riscv_isa_ext_count; i++) {
794 const struct riscv_isa_ext_data *ext = &riscv_isa_ext[i];
795
796 if (of_property_match_string(cpu_node, "riscv,isa-extensions",
797 ext->property) < 0)
798 continue;
799
800 riscv_isa_set_ext(ext, source_isa);
801 }
802
803 riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap);
804 riscv_fill_cpu_vendor_ext(cpu_node, cpu);
805
806 of_node_put(cpu_node);
807
808 /*
809 * All "okay" harts should have same isa. Set HWCAP based on
810 * common capabilities of every "okay" hart, in case they don't.
811 */
812 if (elf_hwcap)
813 elf_hwcap &= this_hwcap;
814 else
815 elf_hwcap = this_hwcap;
816
817 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
818 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
819 else
820 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
821
822 riscv_fill_vendor_ext_list(cpu);
823 }
824
825 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
826 return -ENOENT;
827
828 return 0;
829 }
830
831 #ifdef CONFIG_RISCV_ISA_FALLBACK
832 bool __initdata riscv_isa_fallback = true;
833 #else
834 bool __initdata riscv_isa_fallback;
835 static int __init riscv_isa_fallback_setup(char *__unused)
836 {
837 riscv_isa_fallback = true;
838 return 1;
839 }
840 early_param("riscv_isa_fallback", riscv_isa_fallback_setup);
841 #endif
842
843 void __init riscv_fill_hwcap(void)
844 {
845 char print_str[NUM_ALPHA_EXTS + 1];
846 unsigned long isa2hwcap[26] = {0};
847 int i, j;
848
849 isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I;
850 isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M;
851 isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A;
852 isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;
853 isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;
854 isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;
855 isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V;
856
857 if (!acpi_disabled) {
858 riscv_fill_hwcap_from_isa_string(isa2hwcap);
859 } else {
860 int ret = riscv_fill_hwcap_from_ext_list(isa2hwcap);
861
862 if (ret && riscv_isa_fallback) {
863 pr_info("Falling back to deprecated \"riscv,isa\"\n");
864 riscv_fill_hwcap_from_isa_string(isa2hwcap);
865 }
866 }
867
868 /*
869 * We don't support systems with F but without D, so mask those out
870 * here.
871 */
872 if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {
873 pr_info("This kernel does not support systems with F but not D\n");
874 elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
875 }
876
877 if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ZVE32X)) {
878 /*
879 * This cannot fail when called on the boot hart
880 */
881 riscv_v_setup_vsize();
882 }
883
884 if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
885 /*
886 * ISA string in device tree might have 'v' flag, but
887 * CONFIG_RISCV_ISA_V is disabled in kernel.
888 * Clear V flag in elf_hwcap if CONFIG_RISCV_ISA_V is disabled.
889 */
890 if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
891 elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
892 }
893
894 memset(print_str, 0, sizeof(print_str));
895 for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
896 if (riscv_isa[0] & BIT_MASK(i))
897 print_str[j++] = (char)('a' + i);
898 pr_info("riscv: base ISA extensions %s\n", print_str);
899
900 memset(print_str, 0, sizeof(print_str));
901 for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
902 if (elf_hwcap & BIT_MASK(i))
903 print_str[j++] = (char)('a' + i);
904 pr_info("riscv: ELF capabilities %s\n", print_str);
905 }
906
907 unsigned long riscv_get_elf_hwcap(void)
908 {
909 unsigned long hwcap;
910
911 hwcap = (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1));
912
913 if (!riscv_v_vstate_ctrl_user_allowed())
914 hwcap &= ~COMPAT_HWCAP_ISA_V;
915
916 return hwcap;
917 }
918
919 void riscv_user_isa_enable(void)
920 {
921 if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ))
922 csr_set(CSR_ENVCFG, ENVCFG_CBZE);
923 }
924
925 #ifdef CONFIG_RISCV_ALTERNATIVE
926 /*
927 * Alternative patch sites consider 48 bits when determining when to patch
928 * the old instruction sequence with the new. These bits are broken into a
929 * 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the
930 * patch site is for an erratum, identified by the 32-bit patch ID. When
931 * the vendor ID is zero, the patch site is for a cpufeature. cpufeatures
932 * further break down patch ID into two 16-bit numbers. The lower 16 bits
933 * are the cpufeature ID and the upper 16 bits are used for a value specific
934 * to the cpufeature and patch site. If the upper 16 bits are zero, then it
935 * implies no specific value is specified. cpufeatures that want to control
936 * patching on a per-site basis will provide non-zero values and implement
937 * checks here. The checks return true when patching should be done, and
938 * false otherwise.
939 */
940 static bool riscv_cpufeature_patch_check(u16 id, u16 value)
941 {
942 if (!value)
943 return true;
944
945 switch (id) {
946 case RISCV_ISA_EXT_ZICBOZ:
947 /*
948 * Zicboz alternative applications provide the maximum
949 * supported block size order, or zero when it doesn't
950 * matter. If the current block size exceeds the maximum,
951 * then the alternative cannot be applied.
952 */
953 return riscv_cboz_block_size <= (1U << value);
954 }
955
956 return false;
957 }
958
959 void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
960 struct alt_entry *end,
961 unsigned int stage)
962 {
963 struct alt_entry *alt;
964 void *oldptr, *altptr;
965 u16 id, value, vendor;
966
967 if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
968 return;
969
970 for (alt = begin; alt < end; alt++) {
971 id = PATCH_ID_CPUFEATURE_ID(alt->patch_id);
972 vendor = PATCH_ID_CPUFEATURE_ID(alt->vendor_id);
973
974 /*
975 * Any alternative with a patch_id that is less than
976 * RISCV_ISA_EXT_MAX is interpreted as a standard extension.
977 *
978 * Any alternative with patch_id that is greater than or equal
979 * to RISCV_VENDOR_EXT_ALTERNATIVES_BASE is interpreted as a
980 * vendor extension.
981 */
982 if (id < RISCV_ISA_EXT_MAX) {
983 /*
984 * This patch should be treated as errata so skip
985 * processing here.
986 */
987 if (alt->vendor_id != 0)
988 continue;
989
990 if (!__riscv_isa_extension_available(NULL, id))
991 continue;
992
993 value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id);
994 if (!riscv_cpufeature_patch_check(id, value))
995 continue;
996 } else if (id >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE) {
997 if (!__riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor,
998 id - RISCV_VENDOR_EXT_ALTERNATIVES_BASE))
999 continue;
1000 } else {
1001 WARN(1, "This extension id:%d is not in ISA extension list", id);
1002 continue;
1003 }
1004
1005 oldptr = ALT_OLD_PTR(alt);
1006 altptr = ALT_ALT_PTR(alt);
1007
1008 mutex_lock(&text_mutex);
1009 patch_text_nosync(oldptr, altptr, alt->alt_len);
1010 riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr);
1011 mutex_unlock(&text_mutex);
1012 }
1013 }
1014 #endif
1015
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.